From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9439C1B6D06 for ; Fri, 15 Nov 2024 13:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677198; cv=none; b=RZBQpMHQ/SAJVTjPfWPHvXPKs0+IN/2MfLaBe3VQvC3Jz9Yizv441oakhdJ0XGSGqjHzW4qUeElwrsSUcu+jo8Ycb2J2uLMXIP1nkHaShwVesSecKaDzEGekIp37pe+p36rFsFJvLuz+v62TWxc4DrrwCtwGSp3NHU4ELG1U9Xg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677198; c=relaxed/simple; bh=02hfe2356yWnCCnK/LwUSmT+Q/joPYGw55r39LSXYk4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n26csWaSQDmwDumcVZvGLZI/d4TibtI4cfjflbNgU89Ei6Q6ZVWJxttgAwZtGm0oyItqOu9VEaJYa/NWAbh21iQee1/h9MCITaqC1t9X4FC85IkiVjhXdlydQNcsTguNOFPX1w7MLXxzjfqLAIpY9zTyB4wLBC/QrqyapYSbgkk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=JycdyV6g; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="JycdyV6g" Received: by mail.gandi.net (Postfix) with ESMTPA id 2270F20009; Fri, 15 Nov 2024 13:26:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677194; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=icTZu7vpeiRlHtvFDbI5TYKHSlVIZoYt0or7QxZkF+w=; b=JycdyV6g5asO9KALxp3/nLfKyzKLE0OPlk3303JC98kgKVJbkaBu0siQmBRyGw4gyYzKG0 0qYSeyy0moleIVuNBkTwrb6PFvygReTVfW7UqRHumP0AGSa3iy5OAwhH4mU3ZALanoNeeQ rcHQ2FEzV6rUvoHwmOllJkp3IsBonoorLMusIe2HkVa2hyAh+oggTq6SLMIsxw4ZZP65qv u+u4V0mxG8fgx1itnpwm6k0AiJj5OVYplZjGsL00t0P5+io0QVHOixhoQJve8cL92OM8ZC MEqBSWguZZ7ssoaQucaxrDrmQzzz6fAEZt8UJdnUh2/beAe1LucRfScbnvlkMw== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 01/10] memory: ti-aemif: Store timings parameter in number of cycles - 1 Date: Fri, 15 Nov 2024 14:26:22 +0100 Message-ID: <20241115132631.264609-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" The CS configuration register expects timings to be expressed in 'number of cycles - 1' but they are stored in ns in the struct aemif_cs_data. So at init, the timings currently set are converted to ns by aemif_get_hw_params(), updated with values from the device-tree properties, and then converted back to 'number of cycles - 1' before being applied. Store the timings directly in 'number of cycles - 1' instead of nanoseconds. Perform the conversion from nanosecond during the device-tree parsing. Remove aemif_cycles_to_nsec() as it isn't used anymore. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 137 ++++++++++++++++++++++---------------- 1 file changed, 80 insertions(+), 57 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index d54dc3cfff73..bd0c49ba1939 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -80,28 +80,28 @@ ASIZE_MAX) =20 /** - * struct aemif_cs_data: structure to hold cs parameters + * struct aemif_cs_data: structure to hold CS parameters * @cs: chip-select number - * @wstrobe: write strobe width, ns - * @rstrobe: read strobe width, ns - * @wsetup: write setup width, ns - * @whold: write hold width, ns - * @rsetup: read setup width, ns - * @rhold: read hold width, ns - * @ta: minimum turn around time, ns + * @wstrobe: write strobe width, number of cycles - 1 + * @rstrobe: read strobe width, number of cycles - 1 + * @wsetup: write setup width, number of cycles - 1 + * @whold: write hold width, number of cycles - 1 + * @rsetup: read setup width, number of cycles - 1 + * @rhold: read hold width, number of cycles - 1 + * @ta: minimum turn around time, number of cycles - 1 * @enable_ss: enable/disable select strobe mode * @enable_ew: enable/disable extended wait mode * @asize: width of the asynchronous device's data bus */ struct aemif_cs_data { u8 cs; - u16 wstrobe; - u16 rstrobe; - u8 wsetup; - u8 whold; - u8 rsetup; - u8 rhold; - u8 ta; + u32 wstrobe; + u32 rstrobe; + u32 wsetup; + u32 whold; + u32 rsetup; + u32 rhold; + u32 ta; u8 enable_ss; u8 enable_ew; u8 asize; @@ -175,26 +175,18 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; - unsigned long clk_rate =3D aemif->clk_rate; unsigned offset; u32 set, val; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); - rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); - rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); - rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); - whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); - wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); - wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); - - if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || - whold < 0 || wstrobe < 0 || wsetup < 0) { - dev_err(&pdev->dev, "%s: cannot get suitable timings\n", - __func__); - return -EINVAL; - } + ta =3D data->ta; + rhold =3D data->rhold; + rstrobe =3D data->rstrobe; + rsetup =3D data->rsetup; + whold =3D data->whold; + wstrobe =3D data->wstrobe; + wsetup =3D data->wsetup; =20 set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); @@ -213,11 +205,6 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) return 0; } =20 -static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) -{ - return ((val + 1) * NSEC_PER_MSEC) / clk_rate; -} - /** * aemif_get_hw_params - function to read hw register values * @pdev: platform device to read for @@ -231,19 +218,18 @@ static void aemif_get_hw_params(struct platform_devic= e *pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - unsigned long clk_rate =3D aemif->clk_rate; u32 val, offset; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; val =3D readl(aemif->base + offset); =20 - data->ta =3D aemif_cycles_to_nsec(TA_VAL(val), clk_rate); - data->rhold =3D aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate); - data->rstrobe =3D aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate); - data->rsetup =3D aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate); - data->whold =3D aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate); - data->wstrobe =3D aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate); - data->wsetup =3D aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate); + data->ta =3D TA_VAL(val); + data->rhold =3D RHOLD_VAL(val); + data->rstrobe =3D RSTROBE_VAL(val); + data->rsetup =3D RSETUP_VAL(val); + data->whold =3D WHOLD_VAL(val); + data->wstrobe =3D WSTROBE_VAL(val); + data->wsetup =3D WSETUP_VAL(val); data->enable_ew =3D EW_VAL(val); data->enable_ss =3D SSTROBE_VAL(val); data->asize =3D val & ASIZE_MAX; @@ -261,7 +247,9 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, struct device_node *np) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); + unsigned long clk_rate =3D aemif->clk_rate; struct aemif_cs_data *data; + int ret; u32 cs; u32 val; =20 @@ -287,26 +275,61 @@ static int of_aemif_parse_abus_config(struct platform= _device *pdev, aemif_get_hw_params(pdev, aemif->num_cs++); =20 /* override the values from device node */ - if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) - data->ta =3D val; + if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, TA_MAX); + if (ret < 0) + return ret; =20 - if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) - data->rhold =3D val; + data->ta =3D ret; + } =20 - if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) - data->rstrobe =3D val; + if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, RHOLD_MAX); + if (ret < 0) + return ret; =20 - if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) - data->rsetup =3D val; + data->rhold =3D ret; + } =20 - if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) - data->whold =3D val; + if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, RSTROBE_MAX); + if (ret < 0) + return ret; =20 - if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) - data->wstrobe =3D val; + data->rstrobe =3D ret; + } =20 - if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) - data->wsetup =3D val; + if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, RSETUP_MAX); + if (ret < 0) + return ret; + + data->rsetup =3D ret; + } + + if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, WHOLD_MAX); + if (ret < 0) + return ret; + + data->whold =3D ret; + } + + if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, WSTROBE_MAX); + if (ret < 0) + return ret; + + data->wstrobe =3D ret; + } + + if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) { + ret =3D aemif_calc_rate(pdev, val, clk_rate, WSETUP_MAX); + if (ret < 0) + return ret; + + data->wsetup =3D ret; + } =20 if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) if (val =3D=3D 16) --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD5251BC08B for ; Fri, 15 Nov 2024 13:26:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677198; cv=none; b=IELdv5xEZdOhJBuX/a354tgRUW3Jt9em1SaMsNKF1KmBABciL8HQT3dbndf9Ek63DiNxTMoDJGJeGVOegnqDzlo9P2Ij5yKfPVhYPwB2fSUvNGajQIii5ENW2EAPMC5bCcXwwE26nFbwcKvX+ocVAocDBp4znkcrRGW2O4AyK08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677198; c=relaxed/simple; bh=oY59SY6A6wqY/ptcdG2ON7Jn8L80m9u4SbJJfcOy3fc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=khG6kq1WSgPK9+cq1/kf7+w29aITBVI6UzSFTkze0W/9HCpmdaYJsmXW2nonvDNMysh2ydE6EERChWeHEN6OaUjgSByftb6GO5qyw6dUtP3SIFhaLEmaDzA0a+w7V7ARcahztm7kGHYu/N0IpJBCaaSmJ1KALIIBwW/l8j2q5oE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=iDYt4TIz; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="iDYt4TIz" Received: by mail.gandi.net (Postfix) with ESMTPA id C27AE2000A; Fri, 15 Nov 2024 13:26:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677195; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BOO57gCrd7kA1kaHAYAJHP1GvAJRJefE1dAecm/19NU=; b=iDYt4TIzHr8+xIODoea7yrM2qFW2zm4jTncX33Zx04rUY7qPZeO9m4e6/edL58GDsvhp4n GjJA2z/K3UTok+8dqxyVopUp9QgWs4fw1BOOdAVJhbrUxJoi84O0qt8Ui+9uLNy/nTyLwz xiNgfED64pWf2ivKlfR/5EVKT52LxiyULJE5hXu1YOl+udl2LUKJbjzuM9wEWVxQJtY1bS JS8LBWETImXtwkbb5Zx1AtxI/Wu3RTRUwCNrfJ0nbfCW9jWmHwx/Li0qsWPjNtEF/+JoPf bLvu40SVZCQe+fBroW8ut68nGlCb46gjf69tBEu9+fehf1oosU8IQCGrt9eFpA== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 02/10] memory: ti-aemif: Remove unnecessary local variables Date: Fri, 15 Nov 2024 14:26:23 +0100 Message-ID: <20241115132631.264609-3-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" CS timings are copied to local variables that are then used as is, without any modifications. Remove these unneeded local variables and deal directly with the timings stored in the struct aemif_cs_data. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index bd0c49ba1939..6a751a23d41a 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -174,22 +174,14 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned offset; u32 set, val; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D data->ta; - rhold =3D data->rhold; - rstrobe =3D data->rstrobe; - rsetup =3D data->rsetup; - whold =3D data->whold; - wstrobe =3D data->wstrobe; - wsetup =3D data->wsetup; - - set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | - WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + set =3D TA(data->ta) | + RHOLD(data->rhold) | RSTROBE(data->rstrobe) | RSETUP(data->rsetup) | + WHOLD(data->whold) | WSTROBE(data->wstrobe) | WSETUP(data->wsetup); =20 set |=3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA1281BC9EB for ; Fri, 15 Nov 2024 13:26:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; cv=none; b=SZGuzonr6yE38aXtxHxR4tPtK4MPgscwFKu0wm9+oRdFBQfrlHMRxpogkMCQXIpLIsfMPIqFRH2VQjZJRqTgmUih3z9ikf5aE3lkNOyWQIe/vU41tleLcwf3LmWbQC6XtrPnxrs4rYts3h+OZTBl6MOOl/B5vA1YiunFB4HVBXQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; c=relaxed/simple; bh=dGK1PB3A3vGOl0J9krAIclpt33dKMtjehIeu+tMqcBA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FHPzTFZajNfrInreEKGia89l/2zTnRqKqU54uQnqLYogu3O25doIT5s5jZ7Xkaeiw3ZWp8ei31lEUqFM3ZKp+Az6OV5R1R5An+8j8x9Z9lqsCzoLKgC0m6HxYp4rPUyIDmm9j2Za02mYQXq5Ffnn1D6SrsaKG+gGwrZ8pHeoc20= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=E33wVMI7; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="E33wVMI7" Received: by mail.gandi.net (Postfix) with ESMTPA id 6CA5C20004; Fri, 15 Nov 2024 13:26:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QiHpJejC3EVTa3EJGMvQU1Fk7sjFr5HV3ka8xV/Pe8U=; b=E33wVMI7vgDcjtpRwTiShitYVZzawMxT1FDsAcCVrCKWWsp0gD6StvhLC7UreK25V7H9iU pFY1NSHIDXGOO7LA8pohy2WjE9FzwmQ1wId6pYGf4r3b/uTkQa7jO/5ixDWtLTAtjjonhK Q4I7MqXNR+wSA5LkfgAHJ98Rr2VDAXD+oQyA/YLJBsZjbk3951DeYyrIU6ILDuDYSO6w98 4lgNskqn5GTECGzDVeFbl414f2MLPppeEAeieqNxR+2dou+UpOgYFeZTiy/6FhdqDub37w xMNqQmZcJ8fQWoksDb6YJO/D2pfvu2iD4rgH+qb6UaVC5vw9LQcDCjIWMulz4w== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 03/10] memory: ti-aemif: Wrap CS timings into a struct Date: Fri, 15 Nov 2024 14:26:24 +0100 Message-ID: <20241115132631.264609-4-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" CS timings are store in the struct aemif_cs_data along with other CS parameters. It isn't convenient for exposing CS timings to other drivers without also exposing the other parameters. Wrap the CS timings in a new the struct aemif_cs_timings to simplify their export in upcoming patches. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 58 ++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 6a751a23d41a..aec6d6464efa 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -78,10 +78,8 @@ WSETUP(WSETUP_MAX) | \ EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ ASIZE_MAX) - /** - * struct aemif_cs_data: structure to hold CS parameters - * @cs: chip-select number + * struct aemif_cs_timings: structure to hold CS timings * @wstrobe: write strobe width, number of cycles - 1 * @rstrobe: read strobe width, number of cycles - 1 * @wsetup: write setup width, number of cycles - 1 @@ -89,12 +87,8 @@ * @rsetup: read setup width, number of cycles - 1 * @rhold: read hold width, number of cycles - 1 * @ta: minimum turn around time, number of cycles - 1 - * @enable_ss: enable/disable select strobe mode - * @enable_ew: enable/disable extended wait mode - * @asize: width of the asynchronous device's data bus */ -struct aemif_cs_data { - u8 cs; +struct aemif_cs_timings { u32 wstrobe; u32 rstrobe; u32 wsetup; @@ -102,6 +96,19 @@ struct aemif_cs_data { u32 rsetup; u32 rhold; u32 ta; +}; + +/** + * struct aemif_cs_data: structure to hold CS parameters + * @timings: timings configuration + * @cs: chip-select number + * @enable_ss: enable/disable select strobe mode + * @enable_ew: enable/disable extended wait mode + * @asize: width of the asynchronous device's data bus + */ +struct aemif_cs_data { + struct aemif_cs_timings timings; + u8 cs; u8 enable_ss; u8 enable_ew; u8 asize; @@ -179,9 +186,10 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - set =3D TA(data->ta) | - RHOLD(data->rhold) | RSTROBE(data->rstrobe) | RSETUP(data->rsetup) | - WHOLD(data->whold) | WSTROBE(data->wstrobe) | WSETUP(data->wsetup); + set =3D TA(data->timings.ta) | + RHOLD(data->timings.rhold) | RSTROBE(data->timings.rstrobe) | + RSETUP(data->timings.rsetup) | WHOLD(data->timings.whold) | + WSTROBE(data->timings.wstrobe) | WSETUP(data->timings.wsetup); =20 set |=3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) @@ -215,13 +223,13 @@ static void aemif_get_hw_params(struct platform_devic= e *pdev, int csnum) offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; val =3D readl(aemif->base + offset); =20 - data->ta =3D TA_VAL(val); - data->rhold =3D RHOLD_VAL(val); - data->rstrobe =3D RSTROBE_VAL(val); - data->rsetup =3D RSETUP_VAL(val); - data->whold =3D WHOLD_VAL(val); - data->wstrobe =3D WSTROBE_VAL(val); - data->wsetup =3D WSETUP_VAL(val); + data->timings.ta =3D TA_VAL(val); + data->timings.rhold =3D RHOLD_VAL(val); + data->timings.rstrobe =3D RSTROBE_VAL(val); + data->timings.rsetup =3D RSETUP_VAL(val); + data->timings.whold =3D WHOLD_VAL(val); + data->timings.wstrobe =3D WSTROBE_VAL(val); + data->timings.wsetup =3D WSETUP_VAL(val); data->enable_ew =3D EW_VAL(val); data->enable_ss =3D SSTROBE_VAL(val); data->asize =3D val & ASIZE_MAX; @@ -272,7 +280,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->ta =3D ret; + data->timings.ta =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) { @@ -280,7 +288,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->rhold =3D ret; + data->timings.rhold =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) { @@ -288,7 +296,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->rstrobe =3D ret; + data->timings.rstrobe =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) { @@ -296,7 +304,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->rsetup =3D ret; + data->timings.rsetup =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) { @@ -304,7 +312,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->whold =3D ret; + data->timings.whold =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) { @@ -312,7 +320,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->wstrobe =3D ret; + data->timings.wstrobe =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) { @@ -320,7 +328,7 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, if (ret < 0) return ret; =20 - data->wsetup =3D ret; + data->timings.wsetup =3D ret; } =20 if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42CF41BCA0E for ; Fri, 15 Nov 2024 13:26:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; cv=none; b=khdtYmPjCdBfhZvTtBqhl26UmgsuDnRZHn8fW/mwB29htUDHeAEQhirvfvzWr866OzsfF1DHkN8jqBw/HESsyrmPJeAkpPxUYbUhtLuRgC6kiD4Gzon8+HC9dqeBX1zIkLpxBzab1ETVagtqMKghYEeWQUQZgnz5qT9btGw6OaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; c=relaxed/simple; bh=ALQUzwiE16xOKYCY/i+LdpNPhpbUZJ1kmnTSIs4zCII=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P7O59L+q9lLxUu4o+MZT01F+6oAm89c5HcqapW/I7ppyNjMI8ZJzFfRJ34TP0kYZ/ghClLLI85b3hDlwwyQSbFWE3RjFh3TaP0IqGgQ5hoDqg37REHWn9EKHWYeTyguMP+oVIlwJshdde20gUIuuA1o4mlZKj8uNp8ycD2Z+qjs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=FCtTBDlG; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="FCtTBDlG" Received: by mail.gandi.net (Postfix) with ESMTPA id 208AB2000D; Fri, 15 Nov 2024 13:26:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BQvszEaafaOGtmCwU5uw9CwjZ8MoXUS0hbG2Xve76Qg=; b=FCtTBDlGQ2miJsQholvB/jA87euFnNj4WPdoQVt3wrc9rmDPmIZZ9/h3ZvsY0RSVGa4Bso PNlvZ1m7hgZqIv+xXqnZNuZkxhM7Rx/RCSDMwmVwBCZevL6i3HyQZnXXUNkQkabGGPE+FY TxHU/pz1NjwfQgjuBJWBFKKzxJq1fhhQE2zsYAUekZostNxl65z5DTjeKTU71vzxDnO6rh SBpJgQfho3WPfBGoCxnomb5B85KBjHPpby4h8CGTOzzey+D8v7r3yC6GVEKDhVne9iXri1 QHgfnhfxEAXUPwl6kgPqyExxeA9Xaf9cESjji/peP5BugtYBL7e8w6h2brE7dg== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 04/10] memory: ti-aemif: Create aemif_check_cs_timings() Date: Fri, 15 Nov 2024 14:26:25 +0100 Message-ID: <20241115132631.264609-5-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" aemif_calc_rate() check the validity of a new computed timing against a 'max' value given as input. This isn't convenient if we want to check the CS timing configuration somewhere else in the code. Wrap the verification of all the chip select's timing configuration into a single function to ease its exportation in upcoming patches. Remove the 'max' input from aemif_calc_rate() as it's no longer used. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 107 +++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 58 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index aec6d6464efa..5c1c6f95185f 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -132,18 +132,48 @@ struct aemif_device { struct aemif_cs_data cs_data[NUM_CS]; }; =20 +/** + * aemif_check_cs_timings - Check the validity of a CS timing configuratio= n. + * @timings: timings configuration + * + * @return: 0 if the timing configuration is valid, negative error number = otherwise. + */ +static int aemif_check_cs_timings(struct aemif_cs_timings *timings) +{ + if (timings->ta > TA_MAX) + return -EINVAL; + + if (timings->rhold > RHOLD_MAX) + return -EINVAL; + + if (timings->rstrobe > RSTROBE_MAX) + return -EINVAL; + + if (timings->rsetup > RSETUP_MAX) + return -EINVAL; + + if (timings->whold > WHOLD_MAX) + return -EINVAL; + + if (timings->wstrobe > WSTROBE_MAX) + return -EINVAL; + + if (timings->wsetup > WSETUP_MAX) + return -EINVAL; + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for * @wanted: The cycle time needed in nanoseconds. * @clk: The input clock rate in kHz. - * @max: The maximum divider value that can be programmed. * * On success, returns the calculated timing value minus 1 for easy * programming into AEMIF timing registers, else negative errno. */ -static int aemif_calc_rate(struct platform_device *pdev, int wanted, - unsigned long clk, int max) +static int aemif_calc_rate(struct platform_device *pdev, int wanted, unsig= ned long clk) { int result; =20 @@ -156,10 +186,6 @@ static int aemif_calc_rate(struct platform_device *pde= v, int wanted, if (result < 0) result =3D 0; =20 - /* ... But configuring tighter timings is not an option. */ - else if (result > max) - result =3D -EINVAL; - return result; } =20 @@ -249,7 +275,6 @@ static int of_aemif_parse_abus_config(struct platform_d= evice *pdev, struct aemif_device *aemif =3D platform_get_drvdata(pdev); unsigned long clk_rate =3D aemif->clk_rate; struct aemif_cs_data *data; - int ret; u32 cs; u32 val; =20 @@ -275,68 +300,34 @@ static int of_aemif_parse_abus_config(struct platform= _device *pdev, aemif_get_hw_params(pdev, aemif->num_cs++); =20 /* override the values from device node */ - if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, TA_MAX); - if (ret < 0) - return ret; - - data->timings.ta =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) + data->timings.ta =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, RHOLD_MAX); - if (ret < 0) - return ret; - - data->timings.rhold =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) + data->timings.rhold =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, RSTROBE_MAX); - if (ret < 0) - return ret; + if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) + data->timings.rstrobe =3D aemif_calc_rate(pdev, val, clk_rate); =20 - data->timings.rstrobe =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) + data->timings.rsetup =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, RSETUP_MAX); - if (ret < 0) - return ret; + if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) + data->timings.whold =3D aemif_calc_rate(pdev, val, clk_rate); =20 - data->timings.rsetup =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) + data->timings.wstrobe =3D aemif_calc_rate(pdev, val, clk_rate); =20 - if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, WHOLD_MAX); - if (ret < 0) - return ret; - - data->timings.whold =3D ret; - } - - if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, WSTROBE_MAX); - if (ret < 0) - return ret; - - data->timings.wstrobe =3D ret; - } - - if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) { - ret =3D aemif_calc_rate(pdev, val, clk_rate, WSETUP_MAX); - if (ret < 0) - return ret; - - data->timings.wsetup =3D ret; - } + if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) + data->timings.wsetup =3D aemif_calc_rate(pdev, val, clk_rate); =20 if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) if (val =3D=3D 16) data->asize =3D 1; data->enable_ew =3D of_property_read_bool(np, "ti,cs-extended-wait-mode"); data->enable_ss =3D of_property_read_bool(np, "ti,cs-select-strobe-mode"); - return 0; + + return aemif_check_cs_timings(&data->timings); } =20 static const struct of_device_id aemif_of_match[] =3D { --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C33F71BDAAF for ; Fri, 15 Nov 2024 13:26:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; cv=none; b=cfLk3SEt3ac9MPEghTzdpebPFUxHTb9Qcw8Mgjv5/0V4IzMUC3wXV12xT4K7kMp9OjAhTOOxZW7YNN3AfEa0PFxeqWb6o/HqVlNFnzaOywucQ/6OqKHxD3Y1L0pfe11yttQwS5HLP8bY8Tmutk9BE21r7BohlYGmQW510ayUURQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; c=relaxed/simple; bh=TgN/rP+ogIi3zekJr5MEk3znfMU8uUpre/kMfy7h0eA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pL/VmA0YGxqvFwQeitOOKgXxx1fk4/Kat+93F3dLyqGi1h//J8FRmDeqkm8N058lbhyKE7TMAmmArRZYxo0jLM7NylOvcMZ5og+pjZMoWStjRhPagiORQ46CEivOSaogidHYxa7wauz9sAHCJCsMK7mxa/vMb1fnRH5O6Q+n9Gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mx41yKQX; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mx41yKQX" Received: by mail.gandi.net (Postfix) with ESMTPA id BBA2A2000B; Fri, 15 Nov 2024 13:26:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SzNrkuGWKWD55JZM/GQ2t5ynM+4vtrlwykyzhs1qoMU=; b=mx41yKQX45BJTNnKZhaXMXRgXCWImkmlAlVK/L4VG7L8f9jxF7h3FvG4zoBEVNqanqA/dw tEiIKrdyi9tKrgo9uA0A7RRwmGkWUNXtxF0AYeujC2lXQjn0vrvxqFai5IZG8zgUSZs2uv 1VdeUOWdtahTe7SWE0hK+sUtbxsBG4MvwFmv9pugtbIQBcIeh8J+FROpiLb+q4rPRNJWyV +xcKwE+d80/UvTb8WszTe+h3BES4kPRQrcXV6AF80ZXjBHp0WSWK1VuQ1btP64ywjU5itE FGghxwBOXE2rIsi8tL6yzsDWzEIC8pL7yAlkYZK2TVecYgCSJOpRrgluO7BOyQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 05/10] memory: ti-aemif: Create aemif_set_cs_timings() Date: Fri, 15 Nov 2024 14:26:26 +0100 Message-ID: <20241115132631.264609-6-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Create an aemif_set_cs_timings() function to isolate the setting of a chip select timing configuration and ease its exportation. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 66 +++++++++++++++++++++++++++++---------- 1 file changed, 50 insertions(+), 16 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 5c1c6f95185f..dae3441e0cd9 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,16 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 =20 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) + /** * struct aemif_cs_timings: structure to hold CS timings * @wstrobe: write strobe width, number of cycles - 1 @@ -164,6 +165,44 @@ static int aemif_check_cs_timings(struct aemif_cs_timi= ngs *timings) return 0; } =20 +/** + * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure + * @timings: timings configuration to set + * + * @return: 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + int ret; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + ret =3D aemif_check_cs_timings(timings); + if (ret) + return ret; + + set =3D TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrob= e) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset =3D A1CR_OFFSET + cs * 4; + + val =3D readl(aemif->base + offset); + val &=3D ~TIMINGS_MASK; + val |=3D set; + writel(val, aemif->base + offset); + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for @@ -212,12 +251,7 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - set =3D TA(data->timings.ta) | - RHOLD(data->timings.rhold) | RSTROBE(data->timings.rstrobe) | - RSETUP(data->timings.rsetup) | WHOLD(data->timings.whold) | - WSTROBE(data->timings.wstrobe) | WSETUP(data->timings.wsetup); - - set |=3D (data->asize & ACR_ASIZE_MASK); + set =3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |=3D ACR_EW_MASK; if (data->enable_ss) @@ -228,7 +262,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) val |=3D set; writel(val, aemif->base + offset); =20 - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->ti= mings); } =20 /** --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A79FF1C07C9 for ; Fri, 15 Nov 2024 13:26:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677201; cv=none; b=B+qIg3QuqFeMCoYPFVxuBFkPIUbERZlpeuOCLvgWzWwxsjNAcUnKUuxSK+A1eyh50e7mdP0/QbVr3UxbOUYbrXf0BE+GLOIC8mrTNX8Uw56K9MXGHyl0duahDzwK7ElgibzbnmbxM/AWsWMXtPK3kwvi4OWHoHm0godpmZ/TmmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677201; c=relaxed/simple; bh=eF/TRHcEg5YaWX5BJ4HH88hIW4y7ybIyq2q2fAzOUto=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l1oI/QHRx2Jtn5xyMowRJhm+H2buaFzPYtdTqxgVFLwhylrVM1XYrTNNjL4dj1cP1yUYuD0x5oBPE3V2pY1awDM0FnwsPkRCWJIALjJUS0sBLYUL9oT8VLEVZBoig7Q24XIzyAOGMsYf2EbwzUpuMm03KjUMxzwuifBova5FIis= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=g7asxWba; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="g7asxWba" Received: by mail.gandi.net (Postfix) with ESMTPA id 5E66F20010; Fri, 15 Nov 2024 13:26:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KAxIY3vEKHi6h86MqObf/1O8IAWyhpfN7P2mnFaeHmA=; b=g7asxWbapX36+XGlwSmvLK4abBAKs30Qm/oU5N53uJZcRkA0MrzatIU7JW7EIG0TeIpVvS GsXmSc4OUvjGLOgcHQM6Q+Xx13q9PPNLMaiu2QWn7hdX2jVB0SBeFfo8yAY1q7HZY7VimO mf/h4fCd4AB6zIfrsZng8R1FhTclaIqbKt1V6u7Qyms8+xoUDjRwQ7jlwE3i5Ky7QngjVZ s8ClkZBsJhWg3J29CXPdKzVCg4qW+2jAoSkktoP+51EAZn1AnGVuO050tYBh0IIJ49S0Ex shmg4awBGNNhPhG6+n3n53ZX6pO3r4VM63OGd6Z2B3fPn/rJRoEvqw9Q1CX/XA== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 06/10] memory: ti-aemif: Export aemif_*_cs_timings() Date: Fri, 15 Nov 2024 14:26:27 +0100 Message-ID: <20241115132631.264609-7-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Export the aemif_set_cs_timing() and aemif_check_cs_timing() symbols so they can be used by other drivers Add a mutex to protect the CS configuration register from concurrent accesses between the AEMIF and its 'children'. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 35 ++++++++++++--------------------- include/linux/memory/ti-aemif.h | 32 ++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 22 deletions(-) create mode 100644 include/linux/memory/ti-aemif.h diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index dae3441e0cd9..519283028eee 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -13,7 +13,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -79,26 +81,6 @@ =20 #define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) =20 -/** - * struct aemif_cs_timings: structure to hold CS timings - * @wstrobe: write strobe width, number of cycles - 1 - * @rstrobe: read strobe width, number of cycles - 1 - * @wsetup: write setup width, number of cycles - 1 - * @whold: write hold width, number of cycles - 1 - * @rsetup: read setup width, number of cycles - 1 - * @rhold: read hold width, number of cycles - 1 - * @ta: minimum turn around time, number of cycles - 1 - */ -struct aemif_cs_timings { - u32 wstrobe; - u32 rstrobe; - u32 wsetup; - u32 whold; - u32 rsetup; - u32 rhold; - u32 ta; -}; - /** * struct aemif_cs_data: structure to hold CS parameters * @timings: timings configuration @@ -123,6 +105,7 @@ struct aemif_cs_data { * @num_cs: number of assigned chip-selects * @cs_offset: start number of cs nodes * @cs_data: array of chip-select settings + * @config_cs_lock: lock used to access CS configuration */ struct aemif_device { void __iomem *base; @@ -131,6 +114,7 @@ struct aemif_device { u8 num_cs; int cs_offset; struct aemif_cs_data cs_data[NUM_CS]; + struct mutex config_cs_lock; }; =20 /** @@ -139,7 +123,7 @@ struct aemif_device { * * @return: 0 if the timing configuration is valid, negative error number = otherwise. */ -static int aemif_check_cs_timings(struct aemif_cs_timings *timings) +int aemif_check_cs_timings(struct aemif_cs_timings *timings) { if (timings->ta > TA_MAX) return -EINVAL; @@ -164,6 +148,7 @@ static int aemif_check_cs_timings(struct aemif_cs_timin= gs *timings) =20 return 0; } +EXPORT_SYMBOL(aemif_check_cs_timings); =20 /** * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. @@ -173,7 +158,7 @@ static int aemif_check_cs_timings(struct aemif_cs_timin= gs *timings) * * @return: 0 on success, else negative errno. */ -static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings) { unsigned int offset; u32 val, set; @@ -195,13 +180,16 @@ static int aemif_set_cs_timings(struct aemif_device *= aemif, u8 cs, struct aemif_ =20 offset =3D A1CR_OFFSET + cs * 4; =20 + mutex_lock(&aemif->config_cs_lock); val =3D readl(aemif->base + offset); val &=3D ~TIMINGS_MASK; val |=3D set; writel(val, aemif->base + offset); + mutex_unlock(&aemif->config_cs_lock); =20 return 0; } +EXPORT_SYMBOL(aemif_set_cs_timings); =20 /** * aemif_calc_rate - calculate timing data. @@ -257,10 +245,12 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) if (data->enable_ss) set |=3D ACR_SSTROBE_MASK; =20 + mutex_lock(&aemif->config_cs_lock); val =3D readl(aemif->base + offset); val &=3D ~CONFIG_MASK; val |=3D set; writel(val, aemif->base + offset); + mutex_unlock(&aemif->config_cs_lock); =20 return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->ti= mings); } @@ -399,6 +389,7 @@ static int aemif_probe(struct platform_device *pdev) if (IS_ERR(aemif->base)) return PTR_ERR(aemif->base); =20 + mutex_init(&aemif->config_cs_lock); if (np) { /* * For every controller device node, there is a cs device node diff --git a/include/linux/memory/ti-aemif.h b/include/linux/memory/ti-aemi= f.h new file mode 100644 index 000000000000..0640d30f6321 --- /dev/null +++ b/include/linux/memory/ti-aemif.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TI_AEMIF_H +#define __TI_AEMIF_H + +/** + * struct aemif_cs_timings: structure to hold CS timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold: read hold width + * @rstrobe: read strobe width + * @rsetup: read setup width + * @whold: write hold width + * @wstrobe: write strobe width + * @wsetup: write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + +struct aemif_device; + +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings); +int aemif_check_cs_timings(struct aemif_cs_timings *timings); + +#endif // __TI_AEMIF_H --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F8AB1C07D7 for ; Fri, 15 Nov 2024 13:26:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677201; cv=none; b=BiKFrZbA09C69pUk+VpgCAtQFEf3RHP1V/0byJtC+3adhSUwFFWk5+WA+iJI7IzVDQuaCLp1oy1hlk3UldYLV0t4Z3rPoKzbSC6BrVomQHhk//SPGbrFCdDRztIomjTH+ayEPIYDcRGQ1erR9sB89jfcWfTMUCxjoMHZzcfkYmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677201; c=relaxed/simple; bh=h6Ixu3RgfB/yKWn7YlzSBsiXSugceNv8TIHypQHazUA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mebub9jmbz5Ug4TO+LtwHWNo6sH+UcsOR2mzi0lH/3bPd712zNGC3JsbVjKSJFkTYJaUkR+DeV5yAQicTfko50qAgk55VB8DtvolXpvH1rhX2m7tHysLyPgP/BIHNG7DFA043C9JvH3c5Ehx0OLnvDq+kisKTuoZkgWP8WFiUyE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ZgOtMjxh; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZgOtMjxh" Received: by mail.gandi.net (Postfix) with ESMTPA id 0854D20012; Fri, 15 Nov 2024 13:26:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677198; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=260i8Kmy1qIGGfd2CxjTGXG+BKpSWuDOsQ7KscW8IdI=; b=ZgOtMjxhfqqfhb5wrw/ZDK8XDQSDWY20uGO3MZUwkVWkmm00QyDJaZw2skYrQVKHys1kCA I1emB6bMqJglIBeq/p+aDxDoO1wdZSK2pflR+t4XTFKS7TuX+scFlSTeYs2YClD44bL2Ez Gtt3Ig5Cd0FGJAOCskYDkCB51Juwfbpee6w4B0nr4ShUOKc4zxIRd26LRuyLVsSsHnhaZW hNzjaOAghVnKpMq+qdcTLuj/5ywSi7YJnDJH++ly3i+GhwUafEICO6vJID818fVc2eOcZ/ yMV6TgXa2hjxNBaisFdNzFuQA0LHZYFj9PNsObjB5em4oqYTYMq7XwODteLHWg== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet , kernel test robot Subject: [PATCH v4 07/10] mtd: rawnand: davinci: Always depends on TI_AEMIF Date: Fri, 15 Nov 2024 14:26:28 +0100 Message-ID: <20241115132631.264609-8-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" DAVINCI_NAND depends on TI_AEMIF only when ARCH_KEYSTONE is selected while the NAND controller is also always a part of the AEMIF controller on DaVinci SoCs. Set a dependency on TI_AEMIF regardless of the selected architecture. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202411020140.3wsKJOSB-lkp@int= el.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202411020957.X1T8T9ZR-lkp@int= el.com/ Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d0aaccf72d78..bb61434347bd 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -279,8 +279,8 @@ config MTD_NAND_SH_FLCTL =20 config MTD_NAND_DAVINCI tristate "DaVinci/Keystone NAND controller" - depends on ARCH_DAVINCI || (ARCH_KEYSTONE && TI_AEMIF) || COMPILE_TEST - depends on HAS_IOMEM + depends on COMPILE_TEST || ARCH_DAVINCI || ARCH_KEYSTONE + depends on HAS_IOMEM && TI_AEMIF help Enable the driver for NAND flash chips on Texas Instruments DaVinci/Keystone processors. --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE1C11C07EC for ; Fri, 15 Nov 2024 13:26:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677202; cv=none; b=YZt4Xd4PFzV5TOXh+2VL4O+yMZmJGKX1hU5V+vEhiAeO+l9M3Dtf90oczKtdbdoN0XiduzD8cWpNLkjwHVeaQ0e+e4hYY7h7lxhI8sbXLGr8i1STtfGLsjcIqGDIaZjnTogScDkxX25Ih9njSoSvsske/Mbg0wWS+GqGhxZv1X8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677202; c=relaxed/simple; bh=deaieWFiVONpNRlAhKMPRKsF7JDojpQ/DZGVZJ9W5Dg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u4m+Ow/3zWtwvGvop6N81z9SZQ/KtoD0gk4aFRH1xs+lv3YXmPnZMr2NwrQtn1W7LKLwLs2UpyU0ZNSB/jgcMPQIvCjKz5v1sXYoCwZthZEEX2LejbFcM6jxQt7T9/Y2dqRiVwqJE5DSSsahA/bWUWzNA3ckENKNG4kk/dWFupY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ZynOMVZY; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZynOMVZY" Received: by mail.gandi.net (Postfix) with ESMTPA id C31252000C; Fri, 15 Nov 2024 13:26:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677199; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=khZM5fFii6r1q+Z9uZi3Zgk6G9+0lCTuTox0qCES4xo=; b=ZynOMVZYONl3nqhnxXedxdo+koInvhB99WVhHxixqXffEeAOqMJ424OiX/aiy1p9x5xm8l JVHGqAf3YbhcY0aPRuTkG2+ymtVHaaB9C5TjYKTwbyKejt6x+46Ar8GCxyWOr9v9xL5tH3 I/1/Rv25ffbONC7afgOBleYVrRqo8dgfjJyDnilaTFvOmsgO/5YA8Z4lrEu2mZOEuO6nkl uIOiB58q8wem4Y8kZ/JtWbZAkRVijpfXXEBUYdZ94YyR+TuH9QskbRXSwiMjLd4BUT7wqy DROgIlPuE69uoZcGPnPHdMqUHZELPuxyByS5pY73NCSjtWeRNcCF/yfBfjJwNQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 08/10] mtd: rawnand: davinci: Order headers alphabetically Date: Fri, 15 Nov 2024 14:26:29 +0100 Message-ID: <20241115132631.264609-9-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Order headers alphabetically for better readability. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36..3c0efbdd789e 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,15 +10,15 @@ * Dirk Behme */ =20 -#include -#include -#include #include #include +#include +#include #include #include -#include #include +#include +#include =20 #define NRCSR_OFFSET 0x00 #define NANDFCR_OFFSET 0x60 --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 847061C1AB1 for ; Fri, 15 Nov 2024 13:26:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677203; cv=none; b=E9tNrohsx9Qyv429gfmX61kECtT9v0xxTnwcgiOrKvb85QPv6ToGFOydairVl8pkGB6TXJVqUMahHnY4eTdcmX923B4ibG+7GQ54wjjaRbhkavEdxlH/FzFdTOVY/IMf6qO2t/kIHt8fkYt/wz0cPDOHZbhi6VSn3S3bRK5lxqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677203; c=relaxed/simple; bh=jq/HxwUks//QkKP3ZJZNN0GtGvXs1KXTbgyq1k0z2kU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qsiGT+eS6qdm30PtBE53WiRnyWbPqrFeABjflMBKKe6R4alq9o7gmhwD7GGU7cJG+B/O6gqFNVVqZoomWK65wlrD4bl8eNirKypqC2r+x49WTbNLWzjkzqMSSOsHVzO2IOu8RoDIOFf3ShrDhYl/hLNxnJ1zpXprSnrPk4L3dxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LOPrsKU7; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LOPrsKU7" Received: by mail.gandi.net (Postfix) with ESMTPA id 789FE2000E; Fri, 15 Nov 2024 13:26:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677200; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ONE5RIDa+M5HrCVn5iTpaeEU6VZHpy9NTdUHLDL3hak=; b=LOPrsKU7gTXIZaZmRF+IRCmbUd0+NVzRXSjTADyKtUipBc5z0VFcVRXW2mi6eH9LaS9c3m fhv18d1YRJkJzHB3zP8u/eWuDRmcqZgIFLbzqy9oMWYZSv2cIGHsxt6OocGKby587vOLxb lhPVmJgnM3zKSG60ll3ZtflV4IaxFVW5/bAKqz+wxi8Yqu+2oLkXE1AkOj1m2RzMtflQBT 8AxqObCZ4l12kFmMeuqczwS1H+JE1y7VxJBAM/iD7Ew2HWRYg6BpAAChQAsyXFZZl0HHw6 5cVrhegjUJZNAoo5hApMUp5kbThVKkzk80FcH1/VzINYUFrV1NFjiQn2tLWHDw== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 09/10] mtd: rawnand: davinci: Add clock resource Date: Fri, 15 Nov 2024 14:26:30 +0100 Message-ID: <20241115132631.264609-10-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" NAND controller has a reference clock inherited from the AEMIF (cf. Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt) This clock isn't used yet by the driver. Add a struct clock in the struct davinci_nand_info so it can be used to compute timings. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 3c0efbdd789e..563045c7ce08 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,6 +10,7 @@ * Dirk Behme */ =20 +#include #include #include #include @@ -117,6 +118,8 @@ struct davinci_nand_info { uint32_t mask_cle; =20 uint32_t core_chipsel; + + struct clk *clk; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -822,6 +825,10 @@ static int nand_davinci_probe(struct platform_device *= pdev) return -EADDRNOTAVAIL; } =20 + info->clk =3D devm_clk_get_enabled(&pdev->dev, "aemif"); + if (IS_ERR(info->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed to get cloc= k"); + info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; --=20 2.47.0 From nobody Fri Nov 22 22:55:25 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 268C61C1F30 for ; Fri, 15 Nov 2024 13:26:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677204; cv=none; b=or3A1EJdacgEjVAeRmLwYMzaVO6fkvGDeWlNVRczHeamft5MdEsqfWmyQEIeUCR6i5vexg5rd8OJkgHdSbKd/4pymqKyKQLOOJTU38Q68CnpGVbIGHgQDuMlrbJblwxkiZWyXvfKc4GUSM/f+dEbqq1DpkPzhx3G4XdRCW0TAgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677204; c=relaxed/simple; bh=pAsRe15o8KtYw/7E0XKTJksMgDoXXLxLoIwfb4FVUuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oU2yIqGmn9EOCfJQIMUaUAbzZhFJ4JVgNVmqzf1ewi9DCNKPZ7a+YBWeenFV9/xFh8y5pPMWhMU2cL9ZBb68qjzr9gBmBhy6yLzM1mL0tDnNAkT9Dbver8Gp2RRYduDA1WAX/k3HohN5fPe4uOgF74i/O+5sb5UVnk6ulfmZLWs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=GcGsMFTD; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="GcGsMFTD" Received: by mail.gandi.net (Postfix) with ESMTPA id 1D0E620013; Fri, 15 Nov 2024 13:26:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677200; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iaf75RKxvR9hDjbOf8OF/9PhJbQC3X5yKc/JDdimNdQ=; b=GcGsMFTDYxbk0wvtc7261WbZXvRpR7fbVh4HPRP5+xlgqlV/q29hxgJhcz1vjFJ3LBzADw Rh3mYESwFnu4omGBJfvbB8oj6t4P+t4xaHAIyVy7HcMEk10DcmBvU0GwehfWBRII464tA2 YpP5SDvgH6SLyMUED3ji7scqemkmtOoC6Svc5OhHi3LaEh+ztEg+wun1N3ezRGnyUW3Q/D AUCcauOEfzQD6X8Ig+GESyUmei9bMdG2KGrlQdwscrcn0UbiV1nuajM33hZHH6m2h4bRlR 0+9j3StxUxrIUlzcTBfimYPxJUeaVs4Ld0rdfZ25Di065zImmgaTZx5z22ssXQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 10/10] mtd: rawnand: davinci: Implement setup_interface() operation Date: Fri, 15 Nov 2024 14:26:31 +0100 Message-ID: <20241115132631.264609-11-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com The setup_interface() operation isn't implemented. It forces the driver to use the ONFI mode 0, though it could use more optimal modes. Implement the setup_interface() operation. It uses the aemif_set_cs_timings() function from the AEMIF driver to update the chip select timings. The calculation of the register's contents is directly extracted from =C2=A720.3.2.3 of the DaVinci TRM [1] MAX_TH_PS and MAX_TSU_PS are the worst case timings based on the Keystone2 and DaVinci datasheets. [1] : https://www.ti.com/lit/ug/spruh77c/spruh77c.pdf Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 79 +++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 563045c7ce08..00627c2783f8 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,9 @@ #define MASK_ALE 0x08 #define MASK_CLE 0x10 =20 +#define MAX_TSU_PS 3000 /* Input setup time in ps */ +#define MAX_TH_PS 1600 /* Input hold time in ps */ + struct davinci_nand_pdata { uint32_t mask_ale; uint32_t mask_cle; @@ -120,6 +124,7 @@ struct davinci_nand_info { uint32_t core_chipsel; =20 struct clk *clk; + struct aemif_device *aemif; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -767,9 +772,82 @@ static int davinci_nand_exec_op(struct nand_chip *chip, return 0; } =20 +#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns))) + +static int davinci_nand_setup_interface(struct nand_chip *chip, int chipnr, + const struct nand_interface_config *conf) +{ + struct davinci_nand_info *info =3D to_davinci_nand(nand_to_mtd(chip)); + const struct nand_sdr_timings *sdr; + struct aemif_cs_timings timings; + s32 cfg, min, cyc_ns; + int ret; + + cyc_ns =3D 1000000000 / clk_get_rate(info->clk); + + sdr =3D nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + cfg =3D TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1; + timings.rsetup =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns), + TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1; + timings.rstrobe =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2; + while ((s32)(timings.rsetup + timings.rstrobe) < min) + timings.rstrobe++; + + cfg =3D TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1; + timings.rhold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tRC_min, cyc_ns) - 3; + while ((s32)(timings.rsetup + timings.rstrobe + timings.rhold) < min) + timings.rhold++; + + cfg =3D TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 10= 00), cyc_ns); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1; + timings.ta =3D cfg > 0 ? cfg : 0; + + cfg =3D TO_CYCLES(sdr->tWP_min, cyc_ns) - 1; + timings.wstrobe =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tALS_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1; + timings.wsetup =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tDS_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe) < min) + timings.wstrobe++; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tALH_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1; + timings.whold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tWC_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe + timings.whold) < min) + timings.whold++; + + dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n", + timings.rsetup, timings.rstrobe, timings.rhold); + dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta); + dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n", + timings.wsetup, timings.wstrobe, timings.whold); + + ret =3D aemif_check_cs_timings(&timings); + if (ret || chipnr =3D=3D NAND_DATA_IFACE_CHECK_ONLY) + return ret; + + return aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings); +} + static const struct nand_controller_ops davinci_nand_controller_ops =3D { .attach_chip =3D davinci_nand_attach_chip, .exec_op =3D davinci_nand_exec_op, + .setup_interface =3D davinci_nand_setup_interface, }; =20 static int nand_davinci_probe(struct platform_device *pdev) @@ -832,6 +910,7 @@ static int nand_davinci_probe(struct platform_device *p= dev) info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; + info->aemif =3D dev_get_drvdata(pdev->dev.parent); =20 mtd =3D nand_to_mtd(&info->chip); mtd->dev.parent =3D &pdev->dev; --=20 2.47.0