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RPM is not available in these SoCs, hence adding new compatible to have the sensor enablement and calibration function. Also add nvmem-cell-names. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Praveenkumar I Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Replace '^s[0-9]+$' with '^tsens_sens[0-9]+_off$'. Based on the review comments, the sensor names have been renamed. For example 's9' has been renamed to 'tsens_sens9_off'. .../bindings/thermal/qcom-tsens.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index a12fddc81955..04a8deb70dd1 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -73,6 +73,8 @@ properties: =20 - description: v2 of TSENS with combined interrupt enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens =20 - description: v2 of TSENS with combined interrupt @@ -209,6 +211,18 @@ properties: - const: s9_p2_backup - const: s10_p1_backup - const: s10_p2_backup + - minItems: 8 + items: + - const: mode + - const: base0 + - const: base1 + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' =20 "#qcom,sensors": description: @@ -268,6 +282,8 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens then: properties: @@ -283,6 +299,8 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 --=20 2.34.1 From nobody Fri Nov 22 22:09:46 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D75E1B4F2F; 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charset="utf-8" Document the QFPROM block found on IPQ5424 Acked-by: Krzysztof Kozlowski Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - No change. 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charset="utf-8" From: Praveenkumar I SoCs without RPM need to enable sensors and calibrate them from the kernel. The IPQ5332 and IPQ5424 use the tsens v2.3.3 IP and do not have RPM. Therefore, add a new calibration function for V2, as the tsens.c calib function only supports V1. Also add new feature_config, ops and data for IPQ5332, IPQ5424. Although the TSENS IP supports 16 sensors, not all are used. The hw_id is used to enable the relevant sensors. Signed-off-by: Praveenkumar I Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Replace fallthrough with break in TWO_PT_CALIB case in tsens_v2_calibrate_sensor() - Update the sensor name during the sensor offset reading in tsens_v2_calibrate_sensor() drivers/thermal/qcom/tsens-v2.c | 176 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 8 +- drivers/thermal/qcom/tsens.h | 4 +- 3 files changed, 186 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v= 2.c index 0cb7301eca6e..5591f19e1857 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -4,13 +4,32 @@ * Copyright (c) 2018, Linaro Limited */ =20 +#include #include #include +#include #include "tsens.h" =20 /* ----- SROT ------ */ #define SROT_HW_VER_OFF 0x0000 #define SROT_CTRL_OFF 0x0004 +#define SROT_MEASURE_PERIOD 0x0008 +#define SROT_Sn_CONVERSION 0x0060 +#define V2_SHIFT_DEFAULT 0x0003 +#define V2_SLOPE_DEFAULT 0x0cd0 +#define V2_CZERO_DEFAULT 0x016a +#define ONE_PT_SLOPE 0x0cd0 +#define TWO_PT_SHIFTED_GAIN 921600 +#define ONE_PT_CZERO_CONST 94 +#define SW_RST_DEASSERT 0x0 +#define SW_RST_ASSERT 0x1 +#define MEASURE_PERIOD_2mSEC 0x1 +#define RSEULT_FORMAT_TEMP 0x1 +#define TSENS_ENABLE 0x1 +#define SENSOR_CONVERSION(n) (((n) * 4) + SROT_Sn_CONVERSION) +#define CONVERSION_SHIFT_MASK GENMASK(24, 23) +#define CONVERSION_SLOPE_MASK GENMASK(22, 10) +#define CONVERSION_CZERO_MASK GENMASK(9, 0) =20 /* ----- TM ------ */ #define TM_INT_EN_OFF 0x0004 @@ -50,6 +69,17 @@ static struct tsens_features ipq8074_feat =3D { .trip_max_temp =3D 204000, }; =20 +static struct tsens_features ipq5332_feat =3D { + .ver_major =3D VER_2_X_NO_RPM, + .crit_int =3D 1, + .combo_int =3D 1, + .adc =3D 0, + .srot_split =3D 1, + .max_sensors =3D 16, + .trip_min_temp =3D 0, + .trip_max_temp =3D 204000, +}; + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] =3D { /* ----- SROT ------ */ /* VERSION */ @@ -59,6 +89,10 @@ static const struct reg_field tsens_v2_regfields[MAX_REG= FIELDS] =3D { /* CTRL_OFF */ [TSENS_EN] =3D REG_FIELD(SROT_CTRL_OFF, 0, 0), [TSENS_SW_RST] =3D REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] =3D REG_FIELD(SROT_CTRL_OFF, 3, 18), + [CODE_OR_TEMP] =3D REG_FIELD(SROT_CTRL_OFF, 21, 21), + + [MAIN_MEASURE_PERIOD] =3D REG_FIELD(SROT_MEASURE_PERIOD, 0, 7), =20 /* ----- TM ------ */ /* INTERRUPT ENABLE */ @@ -104,6 +138,126 @@ static const struct reg_field tsens_v2_regfields[MAX_= REGFIELDS] =3D { [TRDY] =3D REG_FIELD(TM_TRDY_OFF, 0, 0), }; =20 +static int tsens_v2_calibrate_sensor(struct device *dev, struct tsens_sens= or *sensor, + struct regmap *map, u32 mode, u32 base0, u32 base1) +{ + u32 shift =3D V2_SHIFT_DEFAULT; + u32 slope =3D V2_SLOPE_DEFAULT, czero =3D V2_CZERO_DEFAULT, val; + char name[20]; + int ret; + + /* Read offset value */ + ret =3D snprintf(name, sizeof(name), "tsens_sens%d_off", sensor->hw_id); + if (ret < 0) + return ret; + + ret =3D nvmem_cell_read_variable_le_u32(dev, name, &sensor->offset); + if (ret) + return ret; + + /* Based on calib mode, program SHIFT, SLOPE and CZERO */ + switch (mode) { + case TWO_PT_CALIB: + slope =3D (TWO_PT_SHIFTED_GAIN / (base1 - base0)); + + czero =3D (base0 + sensor->offset - ((base1 - base0) / 3)); + + break; + case ONE_PT_CALIB2: + czero =3D base0 + sensor->offset - ONE_PT_CZERO_CONST; + + slope =3D ONE_PT_SLOPE; + + break; + default: + dev_dbg(dev, "calibrationless mode\n"); + } + + val =3D FIELD_PREP(CONVERSION_SHIFT_MASK, shift) | + FIELD_PREP(CONVERSION_SLOPE_MASK, slope) | + FIELD_PREP(CONVERSION_CZERO_MASK, czero); + + regmap_write(map, SENSOR_CONVERSION(sensor->hw_id), val); + + return 0; +} + +static int tsens_v2_calibration(struct tsens_priv *priv) +{ + struct device *dev =3D priv->dev; + u32 mode, base0, base1; + int i, ret; + + if (priv->num_sensors > MAX_SENSORS) + return -EINVAL; + + ret =3D nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + if (ret =3D=3D -ENOENT) + dev_warn(priv->dev, "Calibration data not present in DT\n"); + if (ret < 0) + return ret; + + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + ret =3D nvmem_cell_read_variable_le_u32(priv->dev, "base0", &base0); + if (ret < 0) + return ret; + + ret =3D nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + if (ret < 0) + return ret; + + /* Calibrate each sensor */ + for (i =3D 0; i < priv->num_sensors; i++) { + ret =3D tsens_v2_calibrate_sensor(dev, &priv->sensor[i], priv->srot_map, + mode, base0, base1); + if (ret < 0) + return ret; + } + + return 0; +} + +static int __init init_tsens_v2_no_rpm(struct tsens_priv *priv) +{ + struct device *dev =3D priv->dev; + int i, ret; + u32 val =3D 0; + + ret =3D init_common(priv); + if (ret < 0) + return ret; + + priv->rf[CODE_OR_TEMP] =3D devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[CODE_OR_TEMP]); + if (IS_ERR(priv->rf[CODE_OR_TEMP])) + return PTR_ERR(priv->rf[CODE_OR_TEMP]); + + priv->rf[MAIN_MEASURE_PERIOD] =3D devm_regmap_field_alloc(dev, priv->srot= _map, + priv->fields[MAIN_MEASURE_PERIOD]); + if (IS_ERR(priv->rf[MAIN_MEASURE_PERIOD])) + return PTR_ERR(priv->rf[MAIN_MEASURE_PERIOD]); + + regmap_field_write(priv->rf[TSENS_SW_RST], SW_RST_ASSERT); + + regmap_field_write(priv->rf[MAIN_MEASURE_PERIOD], MEASURE_PERIOD_2mSEC); + + /* Enable available sensors */ + for (i =3D 0; i < priv->num_sensors; i++) + val |=3D 1 << priv->sensor[i].hw_id; + + regmap_field_write(priv->rf[SENSOR_EN], val); + + /* Select temperature format, unit is deci-Celsius */ + regmap_field_write(priv->rf[CODE_OR_TEMP], RSEULT_FORMAT_TEMP); + + regmap_field_write(priv->rf[TSENS_SW_RST], SW_RST_DEASSERT); + + regmap_field_write(priv->rf[TSENS_EN], TSENS_ENABLE); + + return 0; +} + static const struct tsens_ops ops_generic_v2 =3D { .init =3D init_common, .get_temp =3D get_temp_tsens_valid, @@ -122,6 +276,28 @@ struct tsens_plat_data data_ipq8074 =3D { .fields =3D tsens_v2_regfields, }; =20 +static const struct tsens_ops ops_ipq5332 =3D { + .init =3D init_tsens_v2_no_rpm, + .get_temp =3D get_temp_tsens_valid, + .calibrate =3D tsens_v2_calibration, +}; + +struct tsens_plat_data data_ipq5332 =3D { + .num_sensors =3D 5, + .ops =3D &ops_ipq5332, + .hw_ids =3D (unsigned int []){11, 12, 13, 14, 15}, + .feat =3D &ipq5332_feat, + .fields =3D tsens_v2_regfields, +}; + +struct tsens_plat_data data_ipq5424 =3D { + .num_sensors =3D 7, + .ops =3D &ops_ipq5332, + .hw_ids =3D (unsigned int []){9, 10, 11, 12, 13, 14, 15}, + .feat =3D &ipq5332_feat, + .fields =3D tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 =3D { .num_sensors =3D 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 0b4421bf4785..c5409225756f 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -975,7 +975,7 @@ int __init init_common(struct tsens_priv *priv) ret =3D regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; - if (!enabled) { + if (!enabled && (tsens_version(priv) !=3D VER_2_X_NO_RPM)) { dev_err(dev, "%s: device not enabled\n", __func__); ret =3D -ENODEV; goto err_put_device; @@ -1102,6 +1102,12 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend= , tsens_resume); =20 static const struct of_device_id tsens_table[] =3D { { + .compatible =3D "qcom,ipq5332-tsens", + .data =3D &data_ipq5332, + }, { + .compatible =3D "qcom,ipq5424-tsens", + .data =3D &data_ipq5424, + }, { .compatible =3D "qcom,ipq8064-tsens", .data =3D &data_8960, }, { diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index cab39de045b1..ac5358e48f74 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -35,6 +35,7 @@ enum tsens_ver { VER_0_1, VER_1_X, VER_2_X, + VER_2_X_NO_RPM, }; =20 enum tsens_irq_type { @@ -168,6 +169,7 @@ enum regfield_ids { TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, + MAIN_MEASURE_PERIOD, =20 /* ----- TM ------ */ /* TRDY */ @@ -650,6 +652,6 @@ extern struct tsens_plat_data data_8226, data_8909, dat= a_8916, data_8939, data_8 extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; 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charset="utf-8" From: Praveenkumar I IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsens node with nvmem cells for calibration data. Signed-off-by: Praveenkumar I Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Rename s11, s12, s13, s14,and s15 to tsens_sens11_off, tsens_sens12_off, tsens_sens13_off, tsens_sens14_off, and tsens_sens15_off respectively. arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index d3c3e215a15c..d643dafe5846 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -177,6 +177,46 @@ cpu_speed_bin: cpu-speed-bin@1d { reg =3D <0x1d 0x2>; bits =3D <7 2>; }; + + tsens_sens11_off: s11@3a5 { + reg =3D <0x3a5 0x1>; + bits =3D <4 4>; + }; + + tsens_sens12_off: s12@3a6 { + reg =3D <0x3a6 0x1>; + bits =3D <0 4>; + }; + + tsens_sens13_off: s13@3a6 { + reg =3D <0x3a6 0x1>; + bits =3D <4 4>; + }; + + tsens_sens14_off: s14@3ad { + reg =3D <0x3ad 0x2>; + bits =3D <7 4>; + }; + + tsens_sens15_off: s15@3ae { + reg =3D <0x3ae 0x1>; + bits =3D <3 4>; + }; + + tsens_mode: mode@3e1 { + reg =3D <0x3e1 0x1>; + bits =3D <0 3>; + }; + + tsens_base0: base0@3e1 { + reg =3D <0x3e1 0x2>; + bits =3D <3 10>; + }; + + tsens_base1: base1@3e2 { + reg =3D <0x3e2 0x2>; + bits =3D <5 10>; + }; }; =20 rng: rng@e3000 { @@ -186,6 +226,32 @@ rng: rng@e3000 { clock-names =3D "core"; }; =20 + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,ipq5332-tsens"; + reg =3D <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names =3D "mode", + "base0", + "base1", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + interrupts =3D ; + interrupt-names =3D "combined"; + #qcom,sensors =3D <5>; + #thermal-sensor-cells =3D <1>; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5332-tlmm"; reg =3D <0x01000000 0x300000>; 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charset="utf-8" From: Praveenkumar I This patch adds thermal zone nodes for sensors present in IPQ5332. Reviewed-by: Dmitry Baryshkov Signed-off-by: Praveenkumar I Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Add polling-delay-passive and configure with 100 for passive trip points. arch/arm64/boot/dts/qcom/ipq5332.dtsi | 69 +++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index d643dafe5846..4f37781de86a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -554,4 +554,73 @@ timer { , ; }; + + thermal-zones { + rfa-0-thermal { + thermal-sensors =3D <&tsens 11>; + + trips { + rfa-0-critical { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + rfa-1-thermal { + thermal-sensors =3D <&tsens 12>; + + trips { + rfa-1-critical { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + misc-thermal { + thermal-sensors =3D <&tsens 13>; + + trips { + misc-critical { + temperature =3D <125000>; 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charset="utf-8" IPQ5424 has tsens v2.3.3 peripheral. This patch adds the tsens node with nvmem cells for calibration data. Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Rename s9, s10, s11, s12, s13, s14, and s15 to tsens_sens9_off, tsens_se= ns10_off, tsens_sens11_off, tsens_sens12_off, tsens_sens13_off, tsens_sens14_off, = and tsens_sens15_off respectively. arch/arm64/boot/dts/qcom/ipq5424.dtsi | 87 +++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 5e219f900412..4f2e103d48a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -145,6 +145,93 @@ soc@0 { #size-cells =3D <2>; ranges =3D <0 0 0 0 0x10 0>; =20 + efuse@a4000 { + compatible =3D "qcom,ipq5424-qfprom", "qcom,qfprom"; + reg =3D <0 0x000a4000 0 0x741>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_sens9_off: s9@3dc { + reg =3D <0x3dc 0x1>; + bits =3D <4 4>; + }; + + tsens_sens10_off: s10@3dd { + reg =3D <0x3dd 0x1>; + bits =3D <0 4>; + }; + + tsens_sens11_off: s11@3dd { + reg =3D <0x3dd 0x1>; + bits =3D <4 4>; + }; + + tsens_sens12_off: s12@3de { + reg =3D <0x3de 0x1>; + bits =3D <0 4>; + }; + + tsens_sens13_off: s13@3de { + reg =3D <0x3de 0x1>; + bits =3D <4 4>; + }; + + tsens_sens14_off: s14@3e5 { + reg =3D <0x3e5 0x2>; + bits =3D <7 4>; + }; + + tsens_sens15_off: s15@3e6 { + reg =3D <0x3e6 0x1>; + bits =3D <3 4>; + }; + + tsens_mode: mode@419 { + reg =3D <0x419 0x1>; + bits =3D <0 3>; + }; + + tsens_base0: base0@419 { + reg =3D <0x419 0x2>; + bits =3D <3 10>; + }; + + tsens_base1: base1@41a { + reg =3D <0x41a 0x2>; + bits =3D <5 10>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,ipq5424-tsens"; + reg =3D <0 0x004a9000 0 0x1000>, + <0 0x004a8000 0 0x1000>; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens9_off>, + <&tsens_sens10_off>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names =3D "mode", + "base0", + "base1", + "tsens_sens9_off", + "tsens_sens10_off", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; 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charset="utf-8" Add thermal zone nodes for sensors present in IPQ5424. Signed-off-by: Manikanta Mylavarapu --- Changes in V8: - Add polling-delay-passive and configure with 100 for passive trip points. arch/arm64/boot/dts/qcom/ipq5424.dtsi | 114 ++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 4f2e103d48a4..fd9d22754107 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -389,4 +389,118 @@ timer { , ; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&tsens 14>; + + trips { + cpu-critical { + temperature =3D <120000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + + cpu-passive { + temperature =3D <110000>; + hysteresis =3D <9000>; + type =3D "passive"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&tsens 12>; + + trips { + cpu-critical { + temperature =3D <120000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + + cpu-passive { + temperature =3D <110000>; + hysteresis =3D <9000>; + type =3D "passive"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&tsens 11>; + + trips { + cpu-critical { + temperature =3D <120000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + + cpu-passive { + temperature =3D <110000>; + hysteresis =3D <9000>; + type =3D "passive"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&tsens 13>; + + trips { + cpu-critical { + temperature =3D <120000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + + cpu-passive { + temperature =3D <110000>; + hysteresis =3D <9000>; + type =3D "passive"; + }; + }; + }; + + wcss-tile2-thermal { + thermal-sensors =3D <&tsens 9>; + + trips { + wcss-tile2-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + wcss-tile3-thermal { + thermal-sensors =3D <&tsens 10>; + + trips { + wcss-tile3-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + top-glue-thermal { + thermal-sensors =3D <&tsens 15>; + + trips { + top-glue-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + }; }; --=20 2.34.1