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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:09:00.7225 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c802ee3-38b5-4af3-0ee2-08dd053bffd8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8906 Content-Type: text/plain; charset="utf-8" commit 9e9af8bbb5f9 ("perf/x86/rapl: Clean up cpumask and hotplug") removes the cpumask handling from rapl. Post that, we no longer need the get_rapl_pmu_cpumask() function. So remove it. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- arch/x86/events/rapl.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index a8defc813c36..f70c49ca0ef3 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -153,7 +153,7 @@ static u64 rapl_timer_ms; static struct perf_msr *rapl_msrs; =20 /* - * Helper functions to get the correct topology macros according to the + * Helper function to get the correct topology id according to the * RAPL PMU scope. */ static inline unsigned int get_rapl_pmu_idx(int cpu) @@ -162,12 +162,6 @@ static inline unsigned int get_rapl_pmu_idx(int cpu) topology_logical_die_id(cpu); } =20 -static inline const struct cpumask *get_rapl_pmu_cpumask(int cpu) -{ - return rapl_pmu_is_pkg_scope() ? topology_core_cpumask(cpu) : - topology_die_cpumask(cpu); -} - static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) { unsigned int rapl_pmu_idx =3D get_rapl_pmu_idx(cpu); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:09:17.9104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc20c54d-4162-4b35-333b-08dd053c0a0d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6623 Content-Type: text/plain; charset="utf-8" From: K Prateek Nayak On x86, topology_core_id() returns a unique core ID within the PKG domain. Looking at match_smt() suggests that a core ID just needs to be unique within a LLC domain. For use cases such as the core RAPL PMU, there exists a need for a unique core ID across the entire system with multiple PKG domains. Introduce topology_logical_core_id() to derive a unique core ID across the system. Signed-off-by: K Prateek Nayak Reviewed-by: Zhang Rui Tested-by: K Prateek Nayak Tested-by: Oleksandr Natalenko Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy --- Documentation/arch/x86/topology.rst | 4 ++++ arch/x86/include/asm/processor.h | 1 + arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_common.c | 1 + 5 files changed, 8 insertions(+) diff --git a/Documentation/arch/x86/topology.rst b/Documentation/arch/x86/t= opology.rst index 7352ab89a55a..c12837e61bda 100644 --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -135,6 +135,10 @@ Thread-related topology information in the kernel: The ID of the core to which a thread belongs. It is also printed in /p= roc/cpuinfo "core_id." =20 + - topology_logical_core_id(); + + The logical core ID to which a thread belongs. + =20 =20 System topology examples diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 4a686f0e5dbf..595859cbf7ff 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -98,6 +98,7 @@ struct cpuinfo_topology { // Logical ID mappings u32 logical_pkg_id; u32 logical_die_id; + u32 logical_core_id; =20 // AMD Node ID and Nodes per Package info u32 amd_node_id; diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index aef70336d624..672fccf9f845 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -137,6 +137,7 @@ extern const struct cpumask *cpu_clustergroup_mask(int = cpu); #define topology_logical_package_id(cpu) (cpu_data(cpu).topo.logical_pkg_i= d) #define topology_physical_package_id(cpu) (cpu_data(cpu).topo.pkg_id) #define topology_logical_die_id(cpu) (cpu_data(cpu).topo.logical_die_id) +#define topology_logical_core_id(cpu) (cpu_data(cpu).topo.logical_core_id) #define topology_die_id(cpu) (cpu_data(cpu).topo.die_id) #define topology_core_id(cpu) (cpu_data(cpu).topo.core_id) #define topology_ppin(cpu) (cpu_data(cpu).ppin) diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 3baf3e435834..b1eb6d7828db 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -24,6 +24,7 @@ static int cpu_debug_show(struct seq_file *m, void *p) seq_printf(m, "core_id: %u\n", c->topo.core_id); seq_printf(m, "logical_pkg_id: %u\n", c->topo.logical_pkg_id); seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); + seq_printf(m, "logical_core_id: %u\n", c->topo.logical_core_id); seq_printf(m, "llc_id: %u\n", c->topo.llc_id); seq_printf(m, "l2c_id: %u\n", c->topo.l2c_id); seq_printf(m, "amd_node_id: %u\n", c->topo.amd_node_id); diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/to= pology_common.c index 9a6069e7133c..23722aa21e2f 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -151,6 +151,7 @@ static void topo_set_ids(struct topo_scan *tscan, bool = early) if (!early) { c->topo.logical_pkg_id =3D topology_get_logical_id(apicid, TOPO_PKG_DOMA= IN); c->topo.logical_die_id =3D topology_get_logical_id(apicid, TOPO_DIE_DOMA= IN); + c->topo.logical_core_id =3D topology_get_logical_id(apicid, TOPO_CORE_DO= MAIN); } =20 /* Package relative core ID */ --=20 2.34.1 From nobody Fri Nov 22 21:59:42 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2050.outbound.protection.outlook.com [40.107.94.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07D59175D5D; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:09:34.9096 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53031988-080b-4b7b-d639-08dd053c1433 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7512 Content-Type: text/plain; charset="utf-8" Prepare for the addition of RAPL core energy counter support. Post which, one CPU might be mapped to more than one rapl_pmu (package/die one and a core one). So, remove the cpu_to_rapl_pmu() function. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- v7 changes: * Add comment to get_rapl_pmu_idx() * Change the rapl_pmu_idx variable in rapl_pmu_event_init() to=20 unsigned int --- arch/x86/events/rapl.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index f70c49ca0ef3..a3c063176513 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -157,22 +157,15 @@ static struct perf_msr *rapl_msrs; * RAPL PMU scope. */ static inline unsigned int get_rapl_pmu_idx(int cpu) -{ +{ /* + * Returns unsigned int, which converts the '-1' return value + * (for non-existent mappings in topology map) to UINT_MAX, so + * the error check in the caller is simplified. + */ return rapl_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : topology_logical_die_id(cpu); } =20 -static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) -{ - unsigned int rapl_pmu_idx =3D get_rapl_pmu_idx(cpu); - - /* - * The unsigned check also catches the '-1' return value for non - * existent mappings in the topology map. - */ - return rapl_pmu_idx < rapl_pmus->nr_rapl_pmu ? rapl_pmus->pmus[rapl_pmu_i= dx] : NULL; -} - static inline u64 rapl_read_counter(struct perf_event *event) { u64 raw; @@ -350,6 +343,7 @@ static int rapl_pmu_event_init(struct perf_event *event) u64 cfg =3D event->attr.config & RAPL_EVENT_MASK; int bit, ret =3D 0; struct rapl_pmu *pmu; + unsigned int rapl_pmu_idx; =20 /* only look at RAPL events */ if (event->attr.type !=3D rapl_pmus->pmu.type) @@ -376,8 +370,12 @@ static int rapl_pmu_event_init(struct perf_event *even= t) if (event->attr.sample_period) /* no sampling */ return -EINVAL; =20 + rapl_pmu_idx =3D get_rapl_pmu_idx(event->cpu); + if (rapl_pmu_idx >=3D rapl_pmus->nr_rapl_pmu) + return -EINVAL; + /* must be done before validate_group */ - pmu =3D cpu_to_rapl_pmu(event->cpu); + pmu =3D rapl_pmus->pmus[rapl_pmu_idx]; if (!pmu) return -EINVAL; event->pmu_private =3D pmu; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:09:51.6661 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81b563b9-b2b3-4cd8-5eca-08dd053c1e22 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4154 Content-Type: text/plain; charset="utf-8" Rename struct rapl_pmu variables from "pmu" to "rapl_pmu", to avoid any confusion between the variables of two different structs pmu and rapl_pmu. As rapl_pmu also contains a pointer to struct pmu, which leads to situations in code like pmu->pmu, which is needlessly confusing. Above scenario is replaced with much more readable rapl_pmu->pmu with this change. Also rename "pmus" member in rapl_pmus struct, for same reason. No functional change. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- arch/x86/events/rapl.c | 91 +++++++++++++++++++++--------------------- 1 file changed, 46 insertions(+), 45 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index a3c063176513..dc350292e1fc 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -129,7 +129,7 @@ struct rapl_pmu { struct rapl_pmus { struct pmu pmu; unsigned int nr_rapl_pmu; - struct rapl_pmu *pmus[] __counted_by(nr_rapl_pmu); + struct rapl_pmu *rapl_pmu[] __counted_by(nr_rapl_pmu); }; =20 enum rapl_unit_quirk { @@ -227,34 +227,34 @@ static void rapl_start_hrtimer(struct rapl_pmu *pmu) =20 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) { - struct rapl_pmu *pmu =3D container_of(hrtimer, struct rapl_pmu, hrtimer); + struct rapl_pmu *rapl_pmu =3D container_of(hrtimer, struct rapl_pmu, hrti= mer); struct perf_event *event; unsigned long flags; =20 - if (!pmu->n_active) + if (!rapl_pmu->n_active) return HRTIMER_NORESTART; =20 - raw_spin_lock_irqsave(&pmu->lock, flags); + raw_spin_lock_irqsave(&rapl_pmu->lock, flags); =20 - list_for_each_entry(event, &pmu->active_list, active_entry) + list_for_each_entry(event, &rapl_pmu->active_list, active_entry) rapl_event_update(event); =20 - raw_spin_unlock_irqrestore(&pmu->lock, flags); + raw_spin_unlock_irqrestore(&rapl_pmu->lock, flags); =20 - hrtimer_forward_now(hrtimer, pmu->timer_interval); + hrtimer_forward_now(hrtimer, rapl_pmu->timer_interval); =20 return HRTIMER_RESTART; } =20 -static void rapl_hrtimer_init(struct rapl_pmu *pmu) +static void rapl_hrtimer_init(struct rapl_pmu *rapl_pmu) { - struct hrtimer *hr =3D &pmu->hrtimer; + struct hrtimer *hr =3D &rapl_pmu->hrtimer; =20 hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL); hr->function =3D rapl_hrtimer_handle; } =20 -static void __rapl_pmu_event_start(struct rapl_pmu *pmu, +static void __rapl_pmu_event_start(struct rapl_pmu *rapl_pmu, struct perf_event *event) { if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) @@ -262,39 +262,39 @@ static void __rapl_pmu_event_start(struct rapl_pmu *p= mu, =20 event->hw.state =3D 0; =20 - list_add_tail(&event->active_entry, &pmu->active_list); + list_add_tail(&event->active_entry, &rapl_pmu->active_list); =20 local64_set(&event->hw.prev_count, rapl_read_counter(event)); =20 - pmu->n_active++; - if (pmu->n_active =3D=3D 1) - rapl_start_hrtimer(pmu); + rapl_pmu->n_active++; + if (rapl_pmu->n_active =3D=3D 1) + rapl_start_hrtimer(rapl_pmu); } =20 static void rapl_pmu_event_start(struct perf_event *event, int mode) { - struct rapl_pmu *pmu =3D event->pmu_private; + struct rapl_pmu *rapl_pmu =3D event->pmu_private; unsigned long flags; =20 - raw_spin_lock_irqsave(&pmu->lock, flags); - __rapl_pmu_event_start(pmu, event); - raw_spin_unlock_irqrestore(&pmu->lock, flags); + raw_spin_lock_irqsave(&rapl_pmu->lock, flags); + __rapl_pmu_event_start(rapl_pmu, event); + raw_spin_unlock_irqrestore(&rapl_pmu->lock, flags); } =20 static void rapl_pmu_event_stop(struct perf_event *event, int mode) { - struct rapl_pmu *pmu =3D event->pmu_private; + struct rapl_pmu *rapl_pmu =3D event->pmu_private; struct hw_perf_event *hwc =3D &event->hw; unsigned long flags; =20 - raw_spin_lock_irqsave(&pmu->lock, flags); + raw_spin_lock_irqsave(&rapl_pmu->lock, flags); =20 /* mark event as deactivated and stopped */ if (!(hwc->state & PERF_HES_STOPPED)) { - WARN_ON_ONCE(pmu->n_active <=3D 0); - pmu->n_active--; - if (pmu->n_active =3D=3D 0) - hrtimer_cancel(&pmu->hrtimer); + WARN_ON_ONCE(rapl_pmu->n_active <=3D 0); + rapl_pmu->n_active--; + if (rapl_pmu->n_active =3D=3D 0) + hrtimer_cancel(&rapl_pmu->hrtimer); =20 list_del(&event->active_entry); =20 @@ -312,23 +312,23 @@ static void rapl_pmu_event_stop(struct perf_event *ev= ent, int mode) hwc->state |=3D PERF_HES_UPTODATE; } =20 - raw_spin_unlock_irqrestore(&pmu->lock, flags); + raw_spin_unlock_irqrestore(&rapl_pmu->lock, flags); } =20 static int rapl_pmu_event_add(struct perf_event *event, int mode) { - struct rapl_pmu *pmu =3D event->pmu_private; + struct rapl_pmu *rapl_pmu =3D event->pmu_private; struct hw_perf_event *hwc =3D &event->hw; unsigned long flags; =20 - raw_spin_lock_irqsave(&pmu->lock, flags); + raw_spin_lock_irqsave(&rapl_pmu->lock, flags); =20 hwc->state =3D PERF_HES_UPTODATE | PERF_HES_STOPPED; =20 if (mode & PERF_EF_START) - __rapl_pmu_event_start(pmu, event); + __rapl_pmu_event_start(rapl_pmu, event); =20 - raw_spin_unlock_irqrestore(&pmu->lock, flags); + raw_spin_unlock_irqrestore(&rapl_pmu->lock, flags); =20 return 0; } @@ -342,7 +342,7 @@ static int rapl_pmu_event_init(struct perf_event *event) { u64 cfg =3D event->attr.config & RAPL_EVENT_MASK; int bit, ret =3D 0; - struct rapl_pmu *pmu; + struct rapl_pmu *rapl_pmu; unsigned int rapl_pmu_idx; =20 /* only look at RAPL events */ @@ -375,10 +375,11 @@ static int rapl_pmu_event_init(struct perf_event *eve= nt) return -EINVAL; =20 /* must be done before validate_group */ - pmu =3D rapl_pmus->pmus[rapl_pmu_idx]; - if (!pmu) + rapl_pmu =3D rapl_pmus->rapl_pmu[rapl_pmu_idx]; + if (!rapl_pmu) return -EINVAL; - event->pmu_private =3D pmu; + + event->pmu_private =3D rapl_pmu; event->hw.event_base =3D rapl_msrs[bit].msr; event->hw.config =3D cfg; event->hw.idx =3D bit; @@ -605,7 +606,7 @@ static void cleanup_rapl_pmus(void) int i; =20 for (i =3D 0; i < rapl_pmus->nr_rapl_pmu; i++) - kfree(rapl_pmus->pmus[i]); + kfree(rapl_pmus->rapl_pmu[i]); kfree(rapl_pmus); } =20 @@ -620,27 +621,27 @@ static const struct attribute_group *rapl_attr_update= [] =3D { =20 static int __init init_rapl_pmu(void) { - struct rapl_pmu *pmu; + struct rapl_pmu *rapl_pmu; int idx; =20 for (idx =3D 0; idx < rapl_pmus->nr_rapl_pmu; idx++) { - pmu =3D kzalloc(sizeof(*pmu), GFP_KERNEL); - if (!pmu) + rapl_pmu =3D kzalloc(sizeof(*rapl_pmu), GFP_KERNEL); + if (!rapl_pmu) goto free; =20 - raw_spin_lock_init(&pmu->lock); - INIT_LIST_HEAD(&pmu->active_list); - pmu->pmu =3D &rapl_pmus->pmu; - pmu->timer_interval =3D ms_to_ktime(rapl_timer_ms); - rapl_hrtimer_init(pmu); + raw_spin_lock_init(&rapl_pmu->lock); + INIT_LIST_HEAD(&rapl_pmu->active_list); + rapl_pmu->pmu =3D &rapl_pmus->pmu; + rapl_pmu->timer_interval =3D ms_to_ktime(rapl_timer_ms); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:10:11.3044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4f030d6-d1bb-4817-f141-08dd053c29d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7380 Content-Type: text/plain; charset="utf-8" Prepare for the addition of RAPL core energy counter support. As there will always be just one rapl_model variable on a system, make it global, to make it easier to access it from any function. No functional change. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Zhang Rui Tested-by: Zhang Rui Reviewed-by: Gautham R. Shenoy --- arch/x86/events/rapl.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index dc350292e1fc..0585e15caeab 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -151,6 +151,7 @@ static struct rapl_pmus *rapl_pmus; static unsigned int rapl_cntr_mask; static u64 rapl_timer_ms; static struct perf_msr *rapl_msrs; +static struct rapl_model *rapl_model; =20 /* * Helper function to get the correct topology id according to the @@ -541,18 +542,18 @@ static struct perf_msr amd_rapl_msrs[] =3D { [PERF_RAPL_PSYS] =3D { 0, &rapl_events_psys_group, NULL, false, 0 }, }; =20 -static int rapl_check_hw_unit(struct rapl_model *rm) +static int rapl_check_hw_unit(void) { u64 msr_rapl_power_unit_bits; int i; =20 /* protect rdmsrl() to handle virtualization */ - if (rdmsrl_safe(rm->msr_power_unit, &msr_rapl_power_unit_bits)) + if (rdmsrl_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits)) return -1; for (i =3D 0; i < NR_RAPL_DOMAINS; i++) rapl_hw_unit[i] =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; =20 - switch (rm->unit_quirk) { + switch (rapl_model->unit_quirk) { /* * DRAM domain on HSW server and KNL has fixed energy unit which can be * different than the unit from power unit MSR. See @@ -797,21 +798,20 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_model_match); static int __init rapl_pmu_init(void) { const struct x86_cpu_id *id; - struct rapl_model *rm; int ret; =20 id =3D x86_match_cpu(rapl_model_match); if (!id) return -ENODEV; =20 - rm =3D (struct rapl_model *) id->driver_data; + rapl_model =3D (struct rapl_model *) id->driver_data; =20 - rapl_msrs =3D rm->rapl_msrs; + rapl_msrs =3D rapl_model->rapl_msrs; =20 rapl_cntr_mask =3D perf_msr_probe(rapl_msrs, PERF_RAPL_MAX, - false, (void *) &rm->events); + false, (void *) &rapl_model->events); =20 - ret =3D rapl_check_hw_unit(rm); + ret =3D rapl_check_hw_unit(); if (ret) return ret; =20 --=20 2.34.1 From nobody Fri Nov 22 21:59:42 2024 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2062.outbound.protection.outlook.com [40.107.96.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B40E1862B8; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:10:25.7212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5cf7d47b-f312-44ea-261e-08dd053c3271 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5913 Content-Type: text/plain; charset="utf-8" Prepare for the addition of RAPL core energy counter support. Add arguments to the init and cleanup functions, which will help in initialization and cleaning up of two separate PMUs. No functional change. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- arch/x86/events/rapl.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 0585e15caeab..f353008b860b 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -602,7 +602,7 @@ static void __init rapl_advertise(void) } } =20 -static void cleanup_rapl_pmus(void) +static void cleanup_rapl_pmus(struct rapl_pmus *rapl_pmus) { int i; =20 @@ -620,7 +620,7 @@ static const struct attribute_group *rapl_attr_update[]= =3D { NULL, }; =20 -static int __init init_rapl_pmu(void) +static int __init init_rapl_pmu(struct rapl_pmus *rapl_pmus) { struct rapl_pmu *rapl_pmu; int idx; @@ -646,20 +646,20 @@ static int __init init_rapl_pmu(void) return -ENOMEM; } =20 -static int __init init_rapl_pmus(void) +static int __init init_rapl_pmus(struct rapl_pmus **rapl_pmus_ptr, int rap= l_pmu_scope) { int nr_rapl_pmu =3D topology_max_packages(); - int rapl_pmu_scope =3D PERF_PMU_SCOPE_PKG; + struct rapl_pmus *rapl_pmus; =20 - if (!rapl_pmu_is_pkg_scope()) { - nr_rapl_pmu *=3D topology_max_dies_per_package(); - rapl_pmu_scope =3D PERF_PMU_SCOPE_DIE; - } + if (rapl_pmu_scope =3D=3D PERF_PMU_SCOPE_DIE) + nr_rapl_pmu *=3D topology_max_dies_per_package(); =20 rapl_pmus =3D kzalloc(struct_size(rapl_pmus, rapl_pmu, nr_rapl_pmu), GFP_= KERNEL); if (!rapl_pmus) return -ENOMEM; =20 + *rapl_pmus_ptr =3D rapl_pmus; + rapl_pmus->nr_rapl_pmu =3D nr_rapl_pmu; rapl_pmus->pmu.attr_groups =3D rapl_attr_groups; rapl_pmus->pmu.attr_update =3D rapl_attr_update; @@ -674,7 +674,7 @@ static int __init init_rapl_pmus(void) rapl_pmus->pmu.module =3D THIS_MODULE; rapl_pmus->pmu.capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; =20 - return init_rapl_pmu(); + return init_rapl_pmu(rapl_pmus); } =20 static struct rapl_model model_snb =3D { @@ -798,8 +798,12 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_model_match); static int __init rapl_pmu_init(void) { const struct x86_cpu_id *id; + int rapl_pmu_scope =3D PERF_PMU_SCOPE_DIE; int ret; =20 + if (rapl_pmu_is_pkg_scope()) + rapl_pmu_scope =3D PERF_PMU_SCOPE_PKG; + id =3D x86_match_cpu(rapl_model_match); if (!id) return -ENODEV; @@ -815,7 +819,7 @@ static int __init rapl_pmu_init(void) if (ret) return ret; =20 - ret =3D init_rapl_pmus(); + ret =3D init_rapl_pmus(&rapl_pmus, rapl_pmu_scope); if (ret) return ret; =20 @@ -828,7 +832,7 @@ static int __init rapl_pmu_init(void) =20 out: pr_warn("Initialization failed (%d), disabled\n", ret); - cleanup_rapl_pmus(); + cleanup_rapl_pmus(rapl_pmus); return ret; } module_init(rapl_pmu_init); @@ -836,6 +840,6 @@ module_init(rapl_pmu_init); static void __exit intel_rapl_exit(void) { perf_pmu_unregister(&rapl_pmus->pmu); - cleanup_rapl_pmus(); + cleanup_rapl_pmus(rapl_pmus); } module_exit(intel_rapl_exit); --=20 2.34.1 From nobody Fri Nov 22 21:59:42 2024 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2066.outbound.protection.outlook.com [40.107.237.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8350185B77; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:10:44.1771 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ae948af-d4c2-490e-2354-08dd053c3d89 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9247 Content-Type: text/plain; charset="utf-8" Prepare for the addition of RAPL core energy counter support. Replace the generic names with *_pkg*, to later on differentiate between the scopes of the two different PMUs and their variables. No functional change. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- arch/x86/events/rapl.c | 120 ++++++++++++++++++++--------------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index f353008b860b..2398a8452709 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -70,18 +70,18 @@ MODULE_LICENSE("GPL"); /* * RAPL energy status counters */ -enum perf_rapl_events { +enum perf_rapl_pkg_events { PERF_RAPL_PP0 =3D 0, /* all cores */ PERF_RAPL_PKG, /* entire package */ PERF_RAPL_RAM, /* DRAM */ PERF_RAPL_PP1, /* gpu */ PERF_RAPL_PSYS, /* psys */ =20 - PERF_RAPL_MAX, - NR_RAPL_DOMAINS =3D PERF_RAPL_MAX, + PERF_RAPL_PKG_EVENTS_MAX, + NR_RAPL_PKG_DOMAINS =3D PERF_RAPL_PKG_EVENTS_MAX, }; =20 -static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = =3D { +static const char *const rapl_pkg_domain_names[NR_RAPL_PKG_DOMAINS] __init= const =3D { "pp0-core", "package", "dram", @@ -112,7 +112,7 @@ static struct perf_pmu_events_attr event_attr_##v =3D {= \ * considered as either pkg-scope or die-scope, and we are considering * them as die-scope. */ -#define rapl_pmu_is_pkg_scope() \ +#define rapl_pkg_pmu_is_pkg_scope() \ (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || \ boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) =20 @@ -139,16 +139,16 @@ enum rapl_unit_quirk { }; =20 struct rapl_model { - struct perf_msr *rapl_msrs; - unsigned long events; + struct perf_msr *rapl_pkg_msrs; + unsigned long pkg_events; unsigned int msr_power_unit; enum rapl_unit_quirk unit_quirk; }; =20 /* 1/2^hw_unit Joule */ -static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; -static struct rapl_pmus *rapl_pmus; -static unsigned int rapl_cntr_mask; +static int rapl_pkg_hw_unit[NR_RAPL_PKG_DOMAINS] __read_mostly; +static struct rapl_pmus *rapl_pmus_pkg; +static unsigned int rapl_pkg_cntr_mask; static u64 rapl_timer_ms; static struct perf_msr *rapl_msrs; static struct rapl_model *rapl_model; @@ -163,8 +163,8 @@ static inline unsigned int get_rapl_pmu_idx(int cpu) * (for non-existent mappings in topology map) to UINT_MAX, so * the error check in the caller is simplified. */ - return rapl_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : - topology_logical_die_id(cpu); + return rapl_pkg_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : + topology_logical_die_id(cpu); } =20 static inline u64 rapl_read_counter(struct perf_event *event) @@ -176,7 +176,7 @@ static inline u64 rapl_read_counter(struct perf_event *= event) =20 static inline u64 rapl_scale(u64 v, int cfg) { - if (cfg > NR_RAPL_DOMAINS) { + if (cfg > NR_RAPL_PKG_DOMAINS) { pr_warn("Invalid domain %d, failed to scale data\n", cfg); return v; } @@ -186,7 +186,7 @@ static inline u64 rapl_scale(u64 v, int cfg) * or use ldexp(count, -32). * Watts =3D Joules/Time delta */ - return v << (32 - rapl_hw_unit[cfg - 1]); + return v << (32 - rapl_pkg_hw_unit[cfg - 1]); } =20 static u64 rapl_event_update(struct perf_event *event) @@ -347,7 +347,7 @@ static int rapl_pmu_event_init(struct perf_event *event) unsigned int rapl_pmu_idx; =20 /* only look at RAPL events */ - if (event->attr.type !=3D rapl_pmus->pmu.type) + if (event->attr.type !=3D rapl_pmus_pkg->pmu.type) return -ENOENT; =20 /* check only supported bits are set */ @@ -357,14 +357,14 @@ static int rapl_pmu_event_init(struct perf_event *eve= nt) if (event->cpu < 0) return -EINVAL; =20 - if (!cfg || cfg >=3D NR_RAPL_DOMAINS + 1) + if (!cfg || cfg >=3D NR_RAPL_PKG_DOMAINS + 1) return -EINVAL; =20 - cfg =3D array_index_nospec((long)cfg, NR_RAPL_DOMAINS + 1); + cfg =3D array_index_nospec((long)cfg, NR_RAPL_PKG_DOMAINS + 1); bit =3D cfg - 1; =20 /* check event supported */ - if (!(rapl_cntr_mask & (1 << bit))) + if (!(rapl_pkg_cntr_mask & (1 << bit))) return -EINVAL; =20 /* unsupported modes and filters */ @@ -372,11 +372,11 @@ static int rapl_pmu_event_init(struct perf_event *eve= nt) return -EINVAL; =20 rapl_pmu_idx =3D get_rapl_pmu_idx(event->cpu); - if (rapl_pmu_idx >=3D rapl_pmus->nr_rapl_pmu) + if (rapl_pmu_idx >=3D rapl_pmus_pkg->nr_rapl_pmu) return -EINVAL; =20 /* must be done before validate_group */ - rapl_pmu =3D rapl_pmus->rapl_pmu[rapl_pmu_idx]; + rapl_pmu =3D rapl_pmus_pkg->rapl_pmu[rapl_pmu_idx]; if (!rapl_pmu) return -EINVAL; =20 @@ -530,11 +530,11 @@ static struct perf_msr intel_rapl_spr_msrs[] =3D { }; =20 /* - * Force to PERF_RAPL_MAX size due to: - * - perf_msr_probe(PERF_RAPL_MAX) + * Force to PERF_RAPL_PKG_EVENTS_MAX size due to: + * - perf_msr_probe(PERF_RAPL_PKG_EVENTS_MAX) * - want to use same event codes across both architectures */ -static struct perf_msr amd_rapl_msrs[] =3D { +static struct perf_msr amd_rapl_pkg_msrs[] =3D { [PERF_RAPL_PP0] =3D { 0, &rapl_events_cores_group, NULL, false, 0 }, [PERF_RAPL_PKG] =3D { MSR_AMD_PKG_ENERGY_STATUS, &rapl_events_pkg_group= , test_msr, false, RAPL_MSR_MASK }, [PERF_RAPL_RAM] =3D { 0, &rapl_events_ram_group, NULL, false, 0 }, @@ -550,8 +550,8 @@ static int rapl_check_hw_unit(void) /* protect rdmsrl() to handle virtualization */ if (rdmsrl_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits)) return -1; - for (i =3D 0; i < NR_RAPL_DOMAINS; i++) - rapl_hw_unit[i] =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; + for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) + rapl_pkg_hw_unit[i] =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; =20 switch (rapl_model->unit_quirk) { /* @@ -561,11 +561,11 @@ static int rapl_check_hw_unit(void) * of 2. Datasheet, September 2014, Reference Number: 330784-001 " */ case RAPL_UNIT_QUIRK_INTEL_HSW: - rapl_hw_unit[PERF_RAPL_RAM] =3D 16; + rapl_pkg_hw_unit[PERF_RAPL_RAM] =3D 16; break; /* SPR uses a fixed energy unit for Psys domain. */ case RAPL_UNIT_QUIRK_INTEL_SPR: - rapl_hw_unit[PERF_RAPL_PSYS] =3D 0; + rapl_pkg_hw_unit[PERF_RAPL_PSYS] =3D 0; break; default: break; @@ -580,9 +580,9 @@ static int rapl_check_hw_unit(void) * if hw unit is 32, then we use 2 ms 1/200/2 */ rapl_timer_ms =3D 2; - if (rapl_hw_unit[0] < 32) { + if (rapl_pkg_hw_unit[0] < 32) { rapl_timer_ms =3D (1000 / (2 * 100)); - rapl_timer_ms *=3D (1ULL << (32 - rapl_hw_unit[0] - 1)); + rapl_timer_ms *=3D (1ULL << (32 - rapl_pkg_hw_unit[0] - 1)); } return 0; } @@ -592,12 +592,12 @@ static void __init rapl_advertise(void) int i; =20 pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\= n", - hweight32(rapl_cntr_mask), rapl_timer_ms); + hweight32(rapl_pkg_cntr_mask), rapl_timer_ms); =20 - for (i =3D 0; i < NR_RAPL_DOMAINS; i++) { - if (rapl_cntr_mask & (1 << i)) { + for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) { + if (rapl_pkg_cntr_mask & (1 << i)) { pr_info("hw unit of domain %s 2^-%d Joules\n", - rapl_domain_names[i], rapl_hw_unit[i]); + rapl_pkg_domain_names[i], rapl_pkg_hw_unit[i]); } } } @@ -678,71 +678,71 @@ static int __init init_rapl_pmus(struct rapl_pmus **r= apl_pmus_ptr, int rapl_pmu_ } =20 static struct rapl_model model_snb =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_PP1), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_snbep =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_hsw =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM) | BIT(PERF_RAPL_PP1), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_hsx =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM), .unit_quirk =3D RAPL_UNIT_QUIRK_INTEL_HSW, .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_knl =3D { - .events =3D BIT(PERF_RAPL_PKG) | + .pkg_events =3D BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM), .unit_quirk =3D RAPL_UNIT_QUIRK_INTEL_HSW, .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_skl =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM) | BIT(PERF_RAPL_PP1) | BIT(PERF_RAPL_PSYS), .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_msrs, + .rapl_pkg_msrs =3D intel_rapl_msrs, }; =20 static struct rapl_model model_spr =3D { - .events =3D BIT(PERF_RAPL_PP0) | + .pkg_events =3D BIT(PERF_RAPL_PP0) | BIT(PERF_RAPL_PKG) | BIT(PERF_RAPL_RAM) | BIT(PERF_RAPL_PSYS), .unit_quirk =3D RAPL_UNIT_QUIRK_INTEL_SPR, .msr_power_unit =3D MSR_RAPL_POWER_UNIT, - .rapl_msrs =3D intel_rapl_spr_msrs, + .rapl_pkg_msrs =3D intel_rapl_spr_msrs, }; =20 static struct rapl_model model_amd_hygon =3D { - .events =3D BIT(PERF_RAPL_PKG), + .pkg_events =3D BIT(PERF_RAPL_PKG), .msr_power_unit =3D MSR_AMD_RAPL_POWER_UNIT, - .rapl_msrs =3D amd_rapl_msrs, + .rapl_pkg_msrs =3D amd_rapl_pkg_msrs, }; =20 static const struct x86_cpu_id rapl_model_match[] __initconst =3D { @@ -798,11 +798,11 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_model_match); static int __init rapl_pmu_init(void) { const struct x86_cpu_id *id; - int rapl_pmu_scope =3D PERF_PMU_SCOPE_DIE; + int rapl_pkg_pmu_scope =3D PERF_PMU_SCOPE_DIE; int ret; =20 - if (rapl_pmu_is_pkg_scope()) - rapl_pmu_scope =3D PERF_PMU_SCOPE_PKG; + if (rapl_pkg_pmu_is_pkg_scope()) + rapl_pkg_pmu_scope =3D PERF_PMU_SCOPE_PKG; =20 id =3D x86_match_cpu(rapl_model_match); if (!id) @@ -810,20 +810,20 @@ static int __init rapl_pmu_init(void) =20 rapl_model =3D (struct rapl_model *) id->driver_data; =20 - rapl_msrs =3D rapl_model->rapl_msrs; + rapl_msrs =3D rapl_model->rapl_pkg_msrs; =20 - rapl_cntr_mask =3D perf_msr_probe(rapl_msrs, PERF_RAPL_MAX, - false, (void *) &rapl_model->events); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:11:00.2647 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f262d2a0-bcdc-411a-fe4f-08dd053c4713 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB9045 Content-Type: text/plain; charset="utf-8" Prepare for the addition of RAPL core energy counter support. After making the rapl_model struct global, the rapl_msrs global variable isn't needed, so remove it. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- arch/x86/events/rapl.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 2398a8452709..46ad20b5e7c5 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -150,7 +150,6 @@ static int rapl_pkg_hw_unit[NR_RAPL_PKG_DOMAINS] __read= _mostly; static struct rapl_pmus *rapl_pmus_pkg; static unsigned int rapl_pkg_cntr_mask; static u64 rapl_timer_ms; -static struct perf_msr *rapl_msrs; static struct rapl_model *rapl_model; =20 /* @@ -381,7 +380,7 @@ static int rapl_pmu_event_init(struct perf_event *event) return -EINVAL; =20 event->pmu_private =3D rapl_pmu; - event->hw.event_base =3D rapl_msrs[bit].msr; + event->hw.event_base =3D rapl_model->rapl_pkg_msrs[bit].msr; event->hw.config =3D cfg; event->hw.idx =3D bit; =20 @@ -810,9 +809,7 @@ static int __init rapl_pmu_init(void) =20 rapl_model =3D (struct rapl_model *) id->driver_data; =20 - rapl_msrs =3D rapl_model->rapl_pkg_msrs; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:11:17.4450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba428281-7268-4d92-1e95-08dd053c514f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8057 Content-Type: text/plain; charset="utf-8" Prepare for the addition of RAPL core energy counter support. Move cntr_mask to rapl_pmus struct instead of adding a new global cntr_mask for the new RAPL power_core PMU. This will also ensure that the second "core_cntr_mask" is only created if needed (i.e. in case of AMD CPUs). Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy Reviewed-by: Zhang Rui Tested-by: Zhang Rui --- arch/x86/events/rapl.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 46ad20b5e7c5..6e51386ff91f 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -129,6 +129,7 @@ struct rapl_pmu { struct rapl_pmus { struct pmu pmu; unsigned int nr_rapl_pmu; + unsigned int cntr_mask; struct rapl_pmu *rapl_pmu[] __counted_by(nr_rapl_pmu); }; =20 @@ -148,7 +149,6 @@ struct rapl_model { /* 1/2^hw_unit Joule */ static int rapl_pkg_hw_unit[NR_RAPL_PKG_DOMAINS] __read_mostly; static struct rapl_pmus *rapl_pmus_pkg; -static unsigned int rapl_pkg_cntr_mask; static u64 rapl_timer_ms; static struct rapl_model *rapl_model; =20 @@ -363,7 +363,7 @@ static int rapl_pmu_event_init(struct perf_event *event) bit =3D cfg - 1; =20 /* check event supported */ - if (!(rapl_pkg_cntr_mask & (1 << bit))) + if (!(rapl_pmus_pkg->cntr_mask & (1 << bit))) return -EINVAL; =20 /* unsupported modes and filters */ @@ -591,10 +591,10 @@ static void __init rapl_advertise(void) int i; =20 pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\= n", - hweight32(rapl_pkg_cntr_mask), rapl_timer_ms); + hweight32(rapl_pmus_pkg->cntr_mask), rapl_timer_ms); =20 for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) { - if (rapl_pkg_cntr_mask & (1 << i)) { + if (rapl_pmus_pkg->cntr_mask & (1 << i)) { pr_info("hw unit of domain %s 2^-%d Joules\n", rapl_pkg_domain_names[i], rapl_pkg_hw_unit[i]); } @@ -809,9 +809,6 @@ static int __init rapl_pmu_init(void) =20 rapl_model =3D (struct rapl_model *) id->driver_data; =20 - rapl_pkg_cntr_mask =3D perf_msr_probe(rapl_model->rapl_pkg_msrs, PERF_RAP= L_PKG_EVENTS_MAX, - false, (void *) &rapl_model->pkg_events); - ret =3D rapl_check_hw_unit(); if (ret) return ret; @@ -820,6 +817,10 @@ static int __init rapl_pmu_init(void) if (ret) return ret; =20 + rapl_pmus_pkg->cntr_mask =3D perf_msr_probe(rapl_model->rapl_pkg_msrs, + PERF_RAPL_PKG_EVENTS_MAX, false, + (void *) &rapl_model->pkg_events); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2024 06:11:34.6245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc50fcfa-a7b8-47d0-8046-08dd053c5b8c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5706 Content-Type: text/plain; charset="utf-8" Add a new "power_core" PMU and "energy-core" event for monitoring energy consumption by each individual core. The existing energy-cores event aggregates the energy consumption of CPU cores at the package level. This new event aligns with the AMD's per-core energy counters. Tested the package level and core level PMU counters with workloads pinned to different CPUs. Results with workload pinned to CPU 4 in core 4 on an AMD Zen4 Genoa machine: $ sudo perf stat --per-core -e power_core/energy-core/ -- taskset -c 4 stre= ss-ng --matrix 1 --timeout 5s stress-ng: info: [21250] setting to a 5 second run per stressor stress-ng: info: [21250] dispatching hogs: 1 matrix stress-ng: info: [21250] successful run completed in 5.00s Performance counter stats for 'system wide': S0-D0-C0 1 0.00 Joules power_core/energy-core/ S0-D0-C1 1 0.00 Joules power_core/energy-core/ S0-D0-C2 1 0.00 Joules power_core/energy-core/ S0-D0-C3 1 0.00 Joules power_core/energy-core/ S0-D0-C4 1 8.43 Joules power_core/energy-core/ S0-D0-C5 1 0.00 Joules power_core/energy-core/ S0-D0-C6 1 0.00 Joules power_core/energy-core/ S0-D0-C7 1 0.00 Joules power_core/energy-core/ S0-D1-C8 1 0.00 Joules power_core/energy-core/ S0-D1-C9 1 0.00 Joules power_core/energy-core/ S0-D1-C10 1 0.00 Joules power_core/energy-core/ Signed-off-by: Dhananjay Ugwekar Reviewed-by: Gautham R. Shenoy --- arch/x86/events/rapl.c | 185 +++++++++++++++++++++++++++++++++-------- 1 file changed, 152 insertions(+), 33 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 6e51386ff91f..e9be1f31163d 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -39,6 +39,10 @@ * event: rapl_energy_psys * perf code: 0x5 * + * core counter: consumption of a single physical core + * event: rapl_energy_core (power_core PMU) + * perf code: 0x1 + * * We manage those counters as free running (read-only). They may be * use simultaneously by other tools, such as turbostat. * @@ -81,6 +85,10 @@ enum perf_rapl_pkg_events { NR_RAPL_PKG_DOMAINS =3D PERF_RAPL_PKG_EVENTS_MAX, }; =20 +#define PERF_RAPL_CORE 0 /* single core */ +#define PERF_RAPL_CORE_EVENTS_MAX 1 +#define NR_RAPL_CORE_DOMAINS PERF_RAPL_CORE_EVENTS_MAX + static const char *const rapl_pkg_domain_names[NR_RAPL_PKG_DOMAINS] __init= const =3D { "pp0-core", "package", @@ -89,6 +97,8 @@ static const char *const rapl_pkg_domain_names[NR_RAPL_PK= G_DOMAINS] __initconst "psys", }; =20 +static const char *const rapl_core_domain_name __initconst =3D "core"; + /* * event code: LSB 8 bits, passed in attr->config * any other bit is reserved @@ -141,14 +151,18 @@ enum rapl_unit_quirk { =20 struct rapl_model { struct perf_msr *rapl_pkg_msrs; + struct perf_msr *rapl_core_msrs; unsigned long pkg_events; + unsigned long core_events; unsigned int msr_power_unit; enum rapl_unit_quirk unit_quirk; }; =20 /* 1/2^hw_unit Joule */ static int rapl_pkg_hw_unit[NR_RAPL_PKG_DOMAINS] __read_mostly; +static int rapl_core_hw_unit __read_mostly; static struct rapl_pmus *rapl_pmus_pkg; +static struct rapl_pmus *rapl_pmus_core; static u64 rapl_timer_ms; static struct rapl_model *rapl_model; =20 @@ -156,14 +170,23 @@ static struct rapl_model *rapl_model; * Helper function to get the correct topology id according to the * RAPL PMU scope. */ -static inline unsigned int get_rapl_pmu_idx(int cpu) -{ /* +static inline unsigned int get_rapl_pmu_idx(int cpu, int scope) +{ + /* * Returns unsigned int, which converts the '-1' return value * (for non-existent mappings in topology map) to UINT_MAX, so * the error check in the caller is simplified. */ - return rapl_pkg_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) : - topology_logical_die_id(cpu); + switch (scope) { + case PERF_PMU_SCOPE_PKG: + return topology_logical_package_id(cpu); + case PERF_PMU_SCOPE_DIE: + return topology_logical_die_id(cpu); + case PERF_PMU_SCOPE_CORE: + return topology_logical_core_id(cpu); + default: + return -EINVAL; + } } =20 static inline u64 rapl_read_counter(struct perf_event *event) @@ -173,19 +196,20 @@ static inline u64 rapl_read_counter(struct perf_event= *event) return raw; } =20 -static inline u64 rapl_scale(u64 v, int cfg) +static inline u64 rapl_scale(u64 v, struct perf_event *event) { - if (cfg > NR_RAPL_PKG_DOMAINS) { - pr_warn("Invalid domain %d, failed to scale data\n", cfg); - return v; - } + int hw_unit =3D rapl_pkg_hw_unit[event->hw.config - 1]; + + if (event->pmu->scope =3D=3D PERF_PMU_SCOPE_CORE) + hw_unit =3D rapl_core_hw_unit; + /* * scale delta to smallest unit (1/2^32) * users must then scale back: count * 1/(1e9*2^32) to get Joules * or use ldexp(count, -32). * Watts =3D Joules/Time delta */ - return v << (32 - rapl_pkg_hw_unit[cfg - 1]); + return v << (32 - hw_unit); } =20 static u64 rapl_event_update(struct perf_event *event) @@ -212,7 +236,7 @@ static u64 rapl_event_update(struct perf_event *event) delta =3D (new_raw_count << shift) - (prev_raw_count << shift); delta >>=3D shift; =20 - sdelta =3D rapl_scale(delta, event->hw.config); + sdelta =3D rapl_scale(delta, event); =20 local64_add(sdelta, &event->count); =20 @@ -341,13 +365,14 @@ static void rapl_pmu_event_del(struct perf_event *eve= nt, int flags) static int rapl_pmu_event_init(struct perf_event *event) { u64 cfg =3D event->attr.config & RAPL_EVENT_MASK; - int bit, ret =3D 0; + int bit, rapl_pmus_scope, ret =3D 0; struct rapl_pmu *rapl_pmu; unsigned int rapl_pmu_idx; + struct rapl_pmus *rapl_pmus; =20 - /* only look at RAPL events */ - if (event->attr.type !=3D rapl_pmus_pkg->pmu.type) - return -ENOENT; + /* unsupported modes and filters */ + if (event->attr.sample_period) /* no sampling */ + return -EINVAL; =20 /* check only supported bits are set */ if (event->attr.config & ~RAPL_EVENT_MASK) @@ -356,31 +381,49 @@ static int rapl_pmu_event_init(struct perf_event *eve= nt) if (event->cpu < 0) return -EINVAL; =20 - if (!cfg || cfg >=3D NR_RAPL_PKG_DOMAINS + 1) + rapl_pmus =3D container_of(event->pmu, struct rapl_pmus, pmu); + if (!rapl_pmus) return -EINVAL; - - cfg =3D array_index_nospec((long)cfg, NR_RAPL_PKG_DOMAINS + 1); - bit =3D cfg - 1; - - /* check event supported */ - if (!(rapl_pmus_pkg->cntr_mask & (1 << bit))) + rapl_pmus_scope =3D rapl_pmus->pmu.scope; + + if (rapl_pmus_scope =3D=3D PERF_PMU_SCOPE_PKG || rapl_pmus_scope =3D=3D P= ERF_PMU_SCOPE_DIE) { + /* only look at RAPL package events */ + if (event->attr.type !=3D rapl_pmus_pkg->pmu.type) + return -ENOENT; + + cfg =3D array_index_nospec((long)cfg, NR_RAPL_PKG_DOMAINS + 1); + if (!cfg || cfg >=3D NR_RAPL_PKG_DOMAINS + 1) + return -EINVAL; + + bit =3D cfg - 1; + event->hw.event_base =3D rapl_model->rapl_pkg_msrs[bit].msr; + } else if (rapl_pmus_scope =3D=3D PERF_PMU_SCOPE_CORE) { + /* only look at RAPL core events */ + if (event->attr.type !=3D rapl_pmus_core->pmu.type) + return -ENOENT; + + cfg =3D array_index_nospec((long)cfg, NR_RAPL_CORE_DOMAINS + 1); + if (!cfg || cfg >=3D NR_RAPL_PKG_DOMAINS + 1) + return -EINVAL; + + bit =3D cfg - 1; + event->hw.event_base =3D rapl_model->rapl_core_msrs[bit].msr; + } else return -EINVAL; =20 - /* unsupported modes and filters */ - if (event->attr.sample_period) /* no sampling */ + /* check event supported */ + if (!(rapl_pmus->cntr_mask & (1 << bit))) return -EINVAL; =20 - rapl_pmu_idx =3D get_rapl_pmu_idx(event->cpu); - if (rapl_pmu_idx >=3D rapl_pmus_pkg->nr_rapl_pmu) + rapl_pmu_idx =3D get_rapl_pmu_idx(event->cpu, rapl_pmus_scope); + if (rapl_pmu_idx >=3D rapl_pmus->nr_rapl_pmu) return -EINVAL; - /* must be done before validate_group */ - rapl_pmu =3D rapl_pmus_pkg->rapl_pmu[rapl_pmu_idx]; + rapl_pmu =3D rapl_pmus->rapl_pmu[rapl_pmu_idx]; if (!rapl_pmu) return -EINVAL; =20 event->pmu_private =3D rapl_pmu; - event->hw.event_base =3D rapl_model->rapl_pkg_msrs[bit].msr; event->hw.config =3D cfg; event->hw.idx =3D bit; =20 @@ -397,12 +440,14 @@ RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event= =3D0x02"); RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=3D0x03"); RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=3D0x04"); RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=3D0x05"); +RAPL_EVENT_ATTR_STR(energy-core, rapl_core, "event=3D0x01"); =20 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_psys_unit, "Joules"); +RAPL_EVENT_ATTR_STR(energy-core.unit, rapl_core_unit, "Joules"); =20 /* * we compute in 0.23 nJ increments regardless of MSR @@ -412,6 +457,7 @@ RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scal= e, "2.3283064365386962890 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386= 962890625e-10"); RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386= 962890625e-10"); RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386= 962890625e-10"); +RAPL_EVENT_ATTR_STR(energy-core.scale, rapl_core_scale, "2.3283064365386= 962890625e-10"); =20 /* * There are no default events, but we need to create @@ -444,6 +490,12 @@ static const struct attribute_group *rapl_attr_groups[= ] =3D { NULL, }; =20 +static const struct attribute_group *rapl_core_attr_groups[] =3D { + &rapl_pmu_format_group, + &rapl_pmu_events_group, + NULL, +}; + static struct attribute *rapl_events_cores[] =3D { EVENT_PTR(rapl_cores), EVENT_PTR(rapl_cores_unit), @@ -504,6 +556,18 @@ static struct attribute_group rapl_events_psys_group = =3D { .attrs =3D rapl_events_psys, }; =20 +static struct attribute *rapl_events_core[] =3D { + EVENT_PTR(rapl_core), + EVENT_PTR(rapl_core_unit), + EVENT_PTR(rapl_core_scale), + NULL, +}; + +static struct attribute_group rapl_events_core_group =3D { + .name =3D "events", + .attrs =3D rapl_events_core, +}; + static bool test_msr(int idx, void *data) { return test_bit(idx, (unsigned long *) data); @@ -541,6 +605,11 @@ static struct perf_msr amd_rapl_pkg_msrs[] =3D { [PERF_RAPL_PSYS] =3D { 0, &rapl_events_psys_group, NULL, false, 0 }, }; =20 +static struct perf_msr amd_rapl_core_msrs[] =3D { + [PERF_RAPL_CORE] =3D { MSR_AMD_CORE_ENERGY_STATUS, &rapl_events_core_grou= p, + test_msr, false, RAPL_MSR_MASK }, +}; + static int rapl_check_hw_unit(void) { u64 msr_rapl_power_unit_bits; @@ -552,6 +621,8 @@ static int rapl_check_hw_unit(void) for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) rapl_pkg_hw_unit[i] =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; =20 + rapl_core_hw_unit =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; + switch (rapl_model->unit_quirk) { /* * DRAM domain on HSW server and KNL has fixed energy unit which can be @@ -570,7 +641,6 @@ static int rapl_check_hw_unit(void) break; } =20 - /* * Calculate the timer rate: * Use reference of 200W for scaling the timeout to avoid counter @@ -589,9 +659,13 @@ static int rapl_check_hw_unit(void) static void __init rapl_advertise(void) { int i; + int num_counters =3D hweight32(rapl_pmus_pkg->cntr_mask); + + if (rapl_pmus_core) + num_counters +=3D hweight32(rapl_pmus_core->cntr_mask); =20 pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\= n", - hweight32(rapl_pmus_pkg->cntr_mask), rapl_timer_ms); + num_counters, rapl_timer_ms); =20 for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) { if (rapl_pmus_pkg->cntr_mask & (1 << i)) { @@ -599,6 +673,10 @@ static void __init rapl_advertise(void) rapl_pkg_domain_names[i], rapl_pkg_hw_unit[i]); } } + + if (rapl_pmus_core && (rapl_pmus_core->cntr_mask & (1 << PERF_RAPL_CORE))) + pr_info("hw unit of domain %s 2^-%d Joules\n", + rapl_core_domain_name, rapl_core_hw_unit); } =20 static void cleanup_rapl_pmus(struct rapl_pmus *rapl_pmus) @@ -619,6 +697,10 @@ static const struct attribute_group *rapl_attr_update[= ] =3D { NULL, }; =20 +static const struct attribute_group *rapl_core_attr_update[] =3D { + &rapl_events_core_group, +}; + static int __init init_rapl_pmu(struct rapl_pmus *rapl_pmus) { struct rapl_pmu *rapl_pmu; @@ -645,13 +727,22 @@ static int __init init_rapl_pmu(struct rapl_pmus *rap= l_pmus) return -ENOMEM; } =20 -static int __init init_rapl_pmus(struct rapl_pmus **rapl_pmus_ptr, int rap= l_pmu_scope) +static int __init init_rapl_pmus(struct rapl_pmus **rapl_pmus_ptr, int rap= l_pmu_scope, + const struct attribute_group **rapl_attr_groups, + const struct attribute_group **rapl_attr_update) { int nr_rapl_pmu =3D topology_max_packages(); struct rapl_pmus *rapl_pmus; =20 + /* + * rapl_pmu_scope must be either PKG, DIE or CORE + */ if (rapl_pmu_scope =3D=3D PERF_PMU_SCOPE_DIE) nr_rapl_pmu *=3D topology_max_dies_per_package(); + else if (rapl_pmu_scope =3D=3D PERF_PMU_SCOPE_CORE) + nr_rapl_pmu *=3D topology_num_cores_per_package(); + else if (rapl_pmu_scope !=3D PERF_PMU_SCOPE_PKG) + return -EINVAL; =20 rapl_pmus =3D kzalloc(struct_size(rapl_pmus, rapl_pmu, nr_rapl_pmu), GFP_= KERNEL); if (!rapl_pmus) @@ -740,8 +831,10 @@ static struct rapl_model model_spr =3D { =20 static struct rapl_model model_amd_hygon =3D { .pkg_events =3D BIT(PERF_RAPL_PKG), + .core_events =3D BIT(PERF_RAPL_CORE), .msr_power_unit =3D MSR_AMD_RAPL_POWER_UNIT, .rapl_pkg_msrs =3D amd_rapl_pkg_msrs, + .rapl_core_msrs =3D amd_rapl_core_msrs, }; =20 static const struct x86_cpu_id rapl_model_match[] __initconst =3D { @@ -813,7 +906,8 @@ static int __init rapl_pmu_init(void) if (ret) return ret; =20 - ret =3D init_rapl_pmus(&rapl_pmus_pkg, rapl_pkg_pmu_scope); + ret =3D init_rapl_pmus(&rapl_pmus_pkg, rapl_pkg_pmu_scope, rapl_attr_grou= ps, + rapl_attr_update); if (ret) return ret; =20 @@ -825,6 +919,27 @@ static int __init rapl_pmu_init(void) if (ret) goto out; =20 + if (rapl_model->core_events) { + ret =3D init_rapl_pmus(&rapl_pmus_core, PERF_PMU_SCOPE_CORE, + rapl_core_attr_groups, + rapl_core_attr_update); + if (ret) { + pr_warn("power-core PMU initialization failed (%d)\n", ret); + goto core_init_failed; + } + + rapl_pmus_core->cntr_mask =3D perf_msr_probe(rapl_model->rapl_core_msrs, + PERF_RAPL_CORE_EVENTS_MAX, false, + (void *) &rapl_model->core_events); + + ret =3D perf_pmu_register(&rapl_pmus_core->pmu, "power_core", -1); + if (ret) { + pr_warn("power-core PMU registration failed (%d)\n", ret); + cleanup_rapl_pmus(rapl_pmus_core); + } + } + +core_init_failed: rapl_advertise(); return 0; =20 @@ -837,6 +952,10 @@ module_init(rapl_pmu_init); =20 static void __exit intel_rapl_exit(void) { + if (rapl_pmus_core) { + perf_pmu_unregister(&rapl_pmus_core->pmu); + cleanup_rapl_pmus(rapl_pmus_core); + } perf_pmu_unregister(&rapl_pmus_pkg->pmu); cleanup_rapl_pmus(rapl_pmus_pkg); } --=20 2.34.1