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a=ed25519-sha256; t=1731666627; l=1812; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=VbDv3VmH4BfqeU0tgRfXeULFVj1/pBCdJ7CHRcqO1uU=; b=e4MCwvIySteGarsyItU3a5dgpd2BB6gxVhbyhGZUaA05k19I2TjrD3UuOS72f2P4J1dAi4R7M PEwhx7ZJxT/CUEA9QeXcGKkdAZtREowYDpXFa1S36rgj3BVGdGmjha9 X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: paOokC8OoKEq3K1kz5m3ylI5LsOxnP1b X-Proofpoint-GUID: paOokC8OoKEq3K1kz5m3ylI5LsOxnP1b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 mlxlogscore=935 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150089 If the vendor drivers can detect the Link up event using mechanisms such as Link up IRQ and can the driver can enumerate downstream devices instead of waiting here, then waiting for Link up during probe is not needed here, which optimizes the boot time. So skip waiting for link to be up if the driver supports 'linkup_irq'. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..c8208a6c03d1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -530,8 +530,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) goto err_remove_edma; } =20 - /* Ignore errors, the link may come up later */ - dw_pcie_wait_for_link(pci); + /* + * Note: The link up delay is skipped only when a link up IRQ is present. + * This flag should not be used to bypass the link up delay for arbitrary + * reasons. + */ + if (!pp->use_linkup_irq) + /* Ignore errors, the link may come up later */ + dw_pcie_wait_for_link(pci); =20 bridge->sysdata =3D pp; =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..1d0ec47e1986 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -379,6 +379,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + bool use_linkup_irq; }; =20 struct dw_pcie_ep_ops { --=20 2.34.1 From nobody Fri Nov 22 21:29:35 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E87761B6CFC; Fri, 15 Nov 2024 10:30:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731666651; cv=none; b=Vk4ww96HNZ0e0ZKXeFMAXHUtFgbzZFkfKcG9a4nhKDJxZeEWvx1Ydeynz3BK8CmichIAQRFHssvMI5yRovB6yTDoIdzUJyeqwhM/TK6FHMhAhsFJSvUDJrgCsiSWOcso7Whc0I9res37mVY1s82wHP1jhgI4FaCTvvIm2oj7DLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731666651; c=relaxed/simple; bh=1g9ovhFlUsWtAx757genx6afRDjob3rmWUH2d/1UyGA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; 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So, set use_linkup_irq flag if global IRQ is present and In order to set the use_linkup_irq flag before calling dw_pcie_host_init() API, which waits for link to be up, move platform_get_irq_byname_optional() API above dw_pcie_host_init(). Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index ef44a82be058..c39d1c55b50e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1692,6 +1692,10 @@ static int qcom_pcie_probe(struct platform_device *p= dev) =20 platform_set_drvdata(pdev, pcie); =20 + irq =3D platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) + pp->use_linkup_irq =3D true; + ret =3D dw_pcie_host_init(pp); if (ret) { dev_err(dev, "cannot initialize host\n"); @@ -1705,7 +1709,6 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) goto err_host_deinit; } =20 - irq =3D platform_get_irq_byname_optional(pdev, "global"); if (irq > 0) { ret =3D devm_request_threaded_irq(&pdev->dev, irq, NULL, qcom_pcie_global_irq_thread, --=20 2.34.1 From nobody Fri Nov 22 21:29:35 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12AFC1B85D1; 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Fri, 15 Nov 2024 10:30:46 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AFAUjsI026286 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Nov 2024 10:30:45 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 02:30:41 -0800 From: Krishna chaitanya chundru Date: Fri, 15 Nov 2024 16:00:23 +0530 Subject: [PATCH v4 3/3] PCI: qcom: Update ICC and OPP values during link up event Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241115-remove_wait1-v4-3-7e3412756e3d@quicinc.com> References: <20241115-remove_wait1-v4-0-7e3412756e3d@quicinc.com> In-Reply-To: <20241115-remove_wait1-v4-0-7e3412756e3d@quicinc.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Konrad Dybcio CC: , , , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , , , , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731666627; l=1234; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=SMJJgYPH0VoGR55VneQNmLBv8TSMazn2Q6TLDzZHqrU=; b=9intVnxYhFLrDZboWXaLPVdNry23wIwyis3ZH/sI8B8nwj3bvkQJAmkSnV44VxTkBr+a+dX4r ByXyDLe4gyrDt5kHHhKt1oZdWY7nGS1V0YVL5Bbd4PtUg9nKqmBoorK X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mj43ACRTjM06U-6ORqlC0OB-d6GzWrZV X-Proofpoint-ORIG-GUID: mj43ACRTjM06U-6ORqlC0OB-d6GzWrZV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=963 bulkscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150089 As the wait for linkup is removed if there is a global IRQ support, there is no guarantee that the correct icc and opp votes are updated as part of probe. And also global IRQ is being used as hotplug event in case link hasn't come up as part probe, link up IRQ is the correct place to update the ICC and OPP votes. So, as part of the PCIe link up event, update ICC and OPP values. Fixes: 4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event= in 'global_irq' interrupt") Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index c39d1c55b50e..39f5c782e2c3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1558,6 +1558,8 @@ static irqreturn_t qcom_pcie_global_irq_thread(int ir= q, void *data) pci_lock_rescan_remove(); pci_rescan_bus(pp->bridge->bus); pci_unlock_rescan_remove(); + + qcom_pcie_icc_opp_update(pcie); } else { dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", status); --=20 2.34.1