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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71a780ea62esm748978a34.5.2024.11.15.12.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 12:18:59 -0800 (PST) From: David Lechner Date: Fri, 15 Nov 2024 14:18:46 -0600 Subject: [PATCH v5 07/16] spi: dt-bindings: axi-spi-engine: add SPI offload properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241115-dlech-mainline-spi-engine-offload-2-v5-7-bea815bd5ea5@baylibre.com> References: <20241115-dlech-mainline-spi-engine-offload-2-v5-0-bea815bd5ea5@baylibre.com> In-Reply-To: <20241115-dlech-mainline-spi-engine-offload-2-v5-0-bea815bd5ea5@baylibre.com> To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, David Lechner X-Mailer: b4 0.14.1 The AXI SPI Engine has support for hardware offloading capabilities. This includes a connection to a DMA controller for streaming RX data and a trigger input for starting execution of the SPI message programmed in the offload. Each SPI Engine may have up to 1 offload. The spec actually says that it could support up to 32, so we are using an index number in the dma-names (e.g. offload0-rx) to allow for this possibility in the future. Signed-off-by: David Lechner --- v5 changes: * Also document offload0-tx DMA names since the hardware can support that now. * Limit the number of offloads to 1 for now since it would require significant hardware changes to actually support more than that. v4 changes: * Dropped #spi-offload-cells property. * Changed subject line. v3 changes: * Added #spi-offload-cells property. * Added properties for triggers and RX data stream connected to DMA. v2 changes: * This is basically a new patch. It partially replaces "dt-bindings: iio: offload: add binding for PWM/DMA triggered buffer". * The controller no longer has an offloads object node and the spi-offloads property is now a standard SPI peripheral property. --- .../bindings/spi/adi,axi-spi-engine.yaml | 24 ++++++++++++++++++= ++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml = b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index d48faa42d025..d703b47eb498 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -41,6 +41,26 @@ properties: - const: s_axi_aclk - const: spi_clk =20 + trigger-sources: + description: + An array of trigger source phandles for offload instances. The index= in + the array corresponds to the offload instance number. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + dmas: + description: + DMA channels connected to the input or output stream interface of an + offload instance. + minItems: 1 + maxItems: 2 + + dma-names: + items: + pattern: "^offload0-[tr]x$" + minItems: 1 + maxItems: 2 + required: - compatible - reg @@ -59,6 +79,10 @@ examples: clocks =3D <&clkc 15>, <&clkc 15>; clock-names =3D "s_axi_aclk", "spi_clk"; =20 + trigger-sources =3D <&trigger_clock>; + dmas =3D <&dma 0>; + dma-names =3D "offload0-rx"; + #address-cells =3D <1>; #size-cells =3D <0>; =20 --=20 2.43.0