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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:28 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 14/22] iio: accel: adxl345: read FIFO entries Date: Thu, 14 Nov 2024 23:09:54 +0000 Message-Id: <20241114231002.98595-15-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a function to read the elements of the adxl345 FIFO. This will flush the FIFO, and brings it into a ready state. The read out is used to read the elemnts and to reset the fifo again. The cleanup equally needs a read on the INT_SOURCE register. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index dbd07308a7..57bca112ea 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -140,6 +140,8 @@ struct adxl34x_state { const struct adxl345_chip_info *info; struct regmap *regmap; struct adxl34x_platform_data data; /* watermark, fifo_mode, etc */ + + __le16 fifo_buf[3 * ADXL34x_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); u8 int_map; bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; @@ -321,6 +323,27 @@ static const struct attribute_group adxl345_attrs_grou= p =3D { .attrs =3D adxl345_attrs, }; =20 +/** + * Read number of FIFO entries into *fifo_entries + */ +static int adxl345_get_fifo_entries(struct adxl34x_state *st, int *fifo_en= tries) +{ + unsigned int regval =3D 0; + int ret; + + ret =3D regmap_read(st->regmap, ADXL345_REG_FIFO_STATUS, ®val); + if (ret) { + pr_warn("%s(): Failed to read FIFO_STATUS register\n", __func__); + *fifo_entries =3D 0; + return ret; + } + + *fifo_entries =3D 0x3f & regval; + pr_debug("%s(): fifo_entries %d\n", __func__, *fifo_entries); + + return 0; +} + static const struct iio_buffer_setup_ops adxl345_buffer_ops =3D { }; =20 @@ -362,6 +385,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, voi= d *p) struct iio_dev *indio_dev =3D ((struct iio_poll_func *) p)->indio_dev; struct adxl34x_state *st =3D iio_priv(indio_dev); u8 int_stat; + int fifo_entries; int ret; =20 ret =3D adxl345_get_status(st, &int_stat); @@ -379,9 +403,11 @@ static irqreturn_t adxl345_trigger_handler(int irq, vo= id *p) goto done; } =20 - if (int_stat & (ADXL345_INT_DATA_READY | ADXL345_INT_WATERMARK)) + if (int_stat & (ADXL345_INT_DATA_READY | ADXL345_INT_WATERMARK)) { pr_debug("%s(): WATERMARK or DATA_READY event detected\n", __func__); - + if (adxl345_get_fifo_entries(st, &fifo_entries) < 0) + goto done; + } goto done; done: =20 --=20 2.39.2