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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:14 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 01/22] iio: accel: adxl345: fix comment on probe Date: Thu, 14 Nov 2024 23:09:41 +0000 Message-Id: <20241114231002.98595-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix comment on the probe function. Add covered sensors and fix typo. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 006ce66c0a..d121caf839 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -170,7 +170,7 @@ static void adxl345_powerdown(void *regmap) =20 /** * adxl345_core_probe() - probe and setup for the adxl345 accelerometer, - * also covers the adlx375 accelerometer + * also covers the adxl375 and adxl346 accelerometer * @dev: Driver model representation of the device * @regmap: Regmap instance for the device * @setup: Setup routine to be executed right before the standard device --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 987DE1B21B9; Thu, 14 Nov 2024 23:10:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625820; cv=none; b=B7cYfr1XjEeg78CubQ/nTdMm1wUuV0YPjva8Lu2fzDyha2TMLcvaMP8LaqD2z59MDlckQs/+kWbjzkHE8eEH3jUKxjttQlW+ks+OSaG8UiisexyIdAi3kQgoVLAnjnO8WSxewJQoO+5RSpAP5kivHV/OIfaPBOaOKVIUEitEgtw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625820; c=relaxed/simple; bh=vXMd3bUouv/WV7BNNEBeLPEuXmjltJJ2I4sZLLnoAXA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QllKxwauv5dk5bc6nnAw63xXpbXwYw8Plzrr2iuC3YBAgq8cDAl/tyUkW1/BCy8f4Bt540flQHb0+ZAA6GCP6WYfHphOSc2KqHEG1g0pJo1NxpSJ9MZmO0pvBbT6uDF5c2lLwa/INpi2yulB6Pb0Pv/w1re1zQdWTilzOY9IVYY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=C1mj8GUo; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="C1mj8GUo" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-37d432f9f5aso60006f8f.3; Thu, 14 Nov 2024 15:10:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731625817; x=1732230617; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dL7aJCXSASL5a/Feg30aFqhCV24wGmaLRDtir+JmL5k=; b=C1mj8GUo7JyutNGnrjSuIJ2MF51ZyqTO57Bh12dWad/HSexezhdybxCV5XqIN0ohCi Yh4T6qOHLOhYFOVE5HucOLztxF/AT4kdiIGX/eI36u6MvdYv7Y2+FyPb+Dbp1b7AabPF nJjE4PoLoADYlf/qimwAxPkSfhRbCUkgOcmot23+5jQyGAVpTDaD+rM8e9bXxdcnxebl ddWkhVtNsIB/fB29Mp8Agy8i5+FzTepy/TzvRPvhApeL6xT/TktZYva8ldov2erl4OZz +caFcUUW2mcnzP+9ZEtGRFh48bXaUR/WW1ZMivUmCedsN/Adwumb9qUMfKws2gPQGYY5 16HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731625817; x=1732230617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dL7aJCXSASL5a/Feg30aFqhCV24wGmaLRDtir+JmL5k=; b=mtSiXy5Jr6FaWExnaXJJojDmQL+B3sq8Jiex480ONcyPa5oV1lk84j0zXh4rSz5NjH u/4RCDXygBYrwK5mydRjJT+9IRv8Sf3lE4JAc6Oa1ipCd0Zal8c2wGHT4lmjVCOegzBB xyTgEfU2tDdaT753Dub5p6gvL3EtFWKUZH0wLixEJ6fE5TtOW8E9cRxQlC2offaK5zUJ ZI0YceVubzK71wIE0peIQHibEmfQW9XDtPwbs7M/HmPcP2QLPG85IW7PxXPMJ7K3qiEf OGzWnmbt19unR/bwBu3dWwZ9Dt4MG+dtuji0BGyX2HPnWmTnWtFhbrAVttBupGn1g4NO Q/Rg== X-Forwarded-Encrypted: i=1; AJvYcCW41hHOmdclPYtnynIpOFXJV78W2B/pGXNXpviWjRlSAX/pf6UUZ7Hmk0Zf9TEcAYfpz7KKK2XCWbyAU2JU@vger.kernel.org, AJvYcCXo2zeScRGDgOQOlVQPcgDnyWYLqP1lPzwLUOoc60wvINHkKslHAe8+8O/bdG956R1G07Yim8CDoOM=@vger.kernel.org X-Gm-Message-State: AOJu0YxnJXoXoz/Ltw3i1u/nU4S+dua5dAj+Z+k4QiG+q5tdn8/nGc1I 0GfaWqyuyEss0Pm8wxYPEFf7O1H642hEnr2EkMEKCiAgFOOUWEHn X-Google-Smtp-Source: AGHT+IEOUNbTCQ4D3xhfcr9oaq9a76+9sXJvK1TxKNmF8DAb7EydMz88hAAyjJcRsEJHg0tLv2gHDA== X-Received: by 2002:a05:600c:3589:b0:42c:c59a:ac21 with SMTP id 5b1f17b1804b1-432df7229eamr1715315e9.2.1731625816737; Thu, 14 Nov 2024 15:10:16 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:15 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 02/22] iio: accel: adxl345: rename variable data to st Date: Thu, 14 Nov 2024 23:09:42 +0000 Message-Id: <20241114231002.98595-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the locally used variable data to st. The st refers to "state", representing the internal state of the driver object. Further it prepares the usage of an internal data pointer needed for the implementation of the sensor features. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 42 ++++++++++++++++---------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index d121caf839..3fb7a7b1b7 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -43,7 +43,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { - struct adxl345_data *data =3D iio_priv(indio_dev); + struct adxl345_data *st =3D iio_priv(indio_dev); __le16 accel; long long samp_freq_nhz; unsigned int regval; @@ -56,7 +56,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte */ - ret =3D regmap_bulk_read(data->regmap, + ret =3D regmap_bulk_read(st->regmap, ADXL345_REG_DATA_AXIS(chan->address), &accel, sizeof(accel)); if (ret < 0) @@ -66,10 +66,10 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val =3D 0; - *val2 =3D data->info->uscale; + *val2 =3D st->info->uscale; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_CALIBBIAS: - ret =3D regmap_read(data->regmap, + ret =3D regmap_read(st->regmap, ADXL345_REG_OFS_AXIS(chan->address), ®val); if (ret < 0) return ret; @@ -81,7 +81,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, =20 return IIO_VAL_INT; case IIO_CHAN_INFO_SAMP_FREQ: - ret =3D regmap_read(data->regmap, ADXL345_REG_BW_RATE, ®val); + ret =3D regmap_read(st->regmap, ADXL345_REG_BW_RATE, ®val); if (ret < 0) return ret; =20 @@ -99,7 +99,7 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { - struct adxl345_data *data =3D iio_priv(indio_dev); + struct adxl345_data *st =3D iio_priv(indio_dev); s64 n; =20 switch (mask) { @@ -108,14 +108,14 @@ static int adxl345_write_raw(struct iio_dev *indio_de= v, * 8-bit resolution at +/- 2g, that is 4x accel data scale * factor */ - return regmap_write(data->regmap, + return regmap_write(st->regmap, ADXL345_REG_OFS_AXIS(chan->address), val / 4); case IIO_CHAN_INFO_SAMP_FREQ: n =3D div_s64(val * NANOHZ_PER_HZ + val2, ADXL345_BASE_RATE_NANO_HZ); =20 - return regmap_update_bits(data->regmap, ADXL345_REG_BW_RATE, + return regmap_update_bits(st->regmap, ADXL345_REG_BW_RATE, ADXL345_BW_RATE, clamp_val(ilog2(n), 0, ADXL345_BW_RATE)); @@ -181,7 +181,7 @@ static void adxl345_powerdown(void *regmap) int adxl345_core_probe(struct device *dev, struct regmap *regmap, int (*setup)(struct device*, struct regmap*)) { - struct adxl345_data *data; + struct adxl345_data *st; struct iio_dev *indio_dev; u32 regval; unsigned int data_format_mask =3D (ADXL345_DATA_FORMAT_RANGE | @@ -190,17 +190,17 @@ int adxl345_core_probe(struct device *dev, struct reg= map *regmap, ADXL345_DATA_FORMAT_SELF_TEST); int ret; =20 - indio_dev =3D devm_iio_device_alloc(dev, sizeof(*data)); + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); if (!indio_dev) return -ENOMEM; =20 - data =3D iio_priv(indio_dev); - data->regmap =3D regmap; - data->info =3D device_get_match_data(dev); - if (!data->info) + st =3D iio_priv(indio_dev); + st->regmap =3D regmap; + st->info =3D device_get_match_data(dev); + if (!st->info) return -ENODEV; =20 - indio_dev->name =3D data->info->name; + indio_dev->name =3D st->info->name; indio_dev->info =3D &adxl345_info; indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->channels =3D adxl345_channels; @@ -208,12 +208,12 @@ int adxl345_core_probe(struct device *dev, struct reg= map *regmap, =20 if (setup) { /* Perform optional initial bus specific configuration */ - ret =3D setup(dev, data->regmap); + ret =3D setup(dev, st->regmap); if (ret) return ret; =20 /* Enable full-resolution mode */ - ret =3D regmap_update_bits(data->regmap, ADXL345_REG_DATA_FORMAT, + ret =3D regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT, data_format_mask, ADXL345_DATA_FORMAT_FULL_RES); if (ret) @@ -222,14 +222,14 @@ int adxl345_core_probe(struct device *dev, struct reg= map *regmap, =20 } else { /* Enable full-resolution mode (init all data_format bits) */ - ret =3D regmap_write(data->regmap, ADXL345_REG_DATA_FORMAT, + ret =3D regmap_write(st->regmap, ADXL345_REG_DATA_FORMAT, ADXL345_DATA_FORMAT_FULL_RES); if (ret) return dev_err_probe(dev, ret, "Failed to set data range\n"); } =20 - ret =3D regmap_read(data->regmap, ADXL345_REG_DEVID, ®val); + ret =3D regmap_read(st->regmap, ADXL345_REG_DEVID, ®val); if (ret < 0) return dev_err_probe(dev, ret, "Error reading device ID\n"); =20 @@ -238,11 +238,11 @@ int adxl345_core_probe(struct device *dev, struct reg= map *regmap, regval, ADXL345_DEVID); =20 /* Enable measurement mode */ - ret =3D adxl345_powerup(data->regmap); + ret =3D adxl345_powerup(st->regmap); if (ret < 0) return dev_err_probe(dev, ret, "Failed to enable measurement mode\n"); =20 - ret =3D devm_add_action_or_reset(dev, adxl345_powerdown, data->regmap); + ret =3D devm_add_action_or_reset(dev, adxl345_powerdown, st->regmap); if (ret < 0) return ret; =20 --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C9F11B3930; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:17 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 03/22] iio: accel: adxl345: rename struct adxl34x_state Date: Thu, 14 Nov 2024 23:09:43 +0000 Message-Id: <20241114231002.98595-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the struct "adxl345_data" to "adxl34x_state". First, the data structure is supposed to be extended to represent state rather than only hold sensor data. The data will be a separate member pointer. Second, the driver not only covers the adxl345 accelerometer, it also supports the adxl345, adxl346 and adxl375. Thus "adxl34x_" is a choice for a common prefix. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 3fb7a7b1b7..30896555a4 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -17,7 +17,7 @@ =20 #include "adxl345.h" =20 -struct adxl345_data { +struct adxl34x_state { const struct adxl345_chip_info *info; struct regmap *regmap; }; @@ -43,7 +43,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { - struct adxl345_data *st =3D iio_priv(indio_dev); + struct adxl34x_state *st =3D iio_priv(indio_dev); __le16 accel; long long samp_freq_nhz; unsigned int regval; @@ -99,7 +99,7 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { - struct adxl345_data *st =3D iio_priv(indio_dev); + struct adxl34x_state *st =3D iio_priv(indio_dev); s64 n; =20 switch (mask) { @@ -181,7 +181,7 @@ static void adxl345_powerdown(void *regmap) int adxl345_core_probe(struct device *dev, struct regmap *regmap, int (*setup)(struct device*, struct regmap*)) { - struct adxl345_data *st; + struct adxl34x_state *st; struct iio_dev *indio_dev; u32 regval; unsigned int data_format_mask =3D (ADXL345_DATA_FORMAT_RANGE | --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BA831B3933; Thu, 14 Nov 2024 23:10:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625821; cv=none; b=eRLMbj09nMeQDoqxyB4qWRCu5Aa5zSqw+N4GNq62S2e8hTDyejqt1RxolCDV6epnwPQ7MkxVh7XoFn0EGlKIE+/eouAu46llkb7jJ+RKbgZ/wmbOdbQGkSzEe5veLgIktdqHXHx2a9yB+E0qpAeeypPUlzHYeh2lyBtp3/6SiNY= ARC-Message-Signature: i=1; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:18 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 04/22] iio: accel: adxl345: rename to adxl34x_channels Date: Thu, 14 Nov 2024 23:09:44 +0000 Message-Id: <20241114231002.98595-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the "adxl345_channels" to "adxl34x_channels". The driver supports several Analog accelerometers equally, e.g. adxl346 and adxl375. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 30896555a4..2b62e79248 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -33,7 +33,7 @@ struct adxl34x_state { BIT(IIO_CHAN_INFO_SAMP_FREQ), \ } =20 -static const struct iio_chan_spec adxl345_channels[] =3D { +static const struct iio_chan_spec adxl34x_channels[] =3D { ADXL345_CHANNEL(0, X), ADXL345_CHANNEL(1, Y), ADXL345_CHANNEL(2, Z), @@ -203,8 +203,8 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, indio_dev->name =3D st->info->name; indio_dev->info =3D &adxl345_info; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->channels =3D adxl345_channels; - indio_dev->num_channels =3D ARRAY_SIZE(adxl345_channels); + indio_dev->channels =3D adxl34x_channels; + indio_dev->num_channels =3D ARRAY_SIZE(adxl34x_channels); =20 if (setup) { /* Perform optional initial bus specific configuration */ --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66F3A1B3949; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:19 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 05/22] iio: accel: adxl345: measure right-justified Date: Thu, 14 Nov 2024 23:09:45 +0000 Message-Id: <20241114231002.98595-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make measurements right-justified, since it is the default for the driver and sensor. By not setting the ADXL345_DATA_FORMAT_JUSTIFY bit, the data becomes right-judstified. This was the original setting, there is no reason to change it to left-justified, where right-justified simplifies working on the registers. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 2b62e79248..926e397678 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -184,8 +184,13 @@ int adxl345_core_probe(struct device *dev, struct regm= ap *regmap, struct adxl34x_state *st; struct iio_dev *indio_dev; u32 regval; + + /* NB: ADXL345_DATA_FORMAT_JUSTIFY or 0: + * do right-justified: 0, then adjust resolution according to 10-bit + * through 13-bit in channel - this is the default behavior, and can + * be modified here by oring ADXL345_DATA_FORMAT_JUSTIFY + */ unsigned int data_format_mask =3D (ADXL345_DATA_FORMAT_RANGE | - ADXL345_DATA_FORMAT_JUSTIFY | ADXL345_DATA_FORMAT_FULL_RES | ADXL345_DATA_FORMAT_SELF_TEST); int ret; --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3568D1B4F08; Thu, 14 Nov 2024 23:10:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625824; cv=none; b=F/MWeTHnYgNXCwqTcN9ExUqN0UaPkxZhQrYk/0nJmXn6VESrGlhiTnepWm/Lhm4DeVoYo+vAtnJOv9niodcjeR1AMCvxKiS66ufRY4sdlSBXyD+x26ep8ZBGlG/SsCPXWhR4mkXGRT3reDRMbzxgcOyQBJkIuRSWFTX7u/A1ooA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625824; c=relaxed/simple; bh=gHYu12Rw5/dkV3YGL2sO3N01Roy+URU34yCpf9G7WpU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eKKJnc1LSM4sDzSeVo1P7jv39cTR5mcJCdG/l3m7wkXJPjXpE8eSw1kFJtwvKm24tCYF83OFnZvx5xHQmjL+oOlNfeTueGWySp/qt/HxsDdzkSmmSDxHl2k2avjSCJT5MuV4/s2yitLiVpX+BeryJzStjmSmcBS8LunN/2wIvgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lTK8mM01; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lTK8mM01" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-432d796a57eso1407575e9.1; Thu, 14 Nov 2024 15:10:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731625820; x=1732230620; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O5DVuhpbt65Tb2WFhtaXDExhTn0sEn63wQnWqfaY7lM=; b=lTK8mM01kc1cYTwGpDNtfsMB1D5Vio/Qn/URQmchASlXafybKrdYUNs6Pds67MUmsO iTTNe7Br2HUTGxHMGLVVirYM6u3wNNkOwfYa2m6I4FpASO3cTcVY5WbVaQt2JihaDrdm KQgi1CHmB8HyZKcXMh1sv6xgR+CYuj0HRZtkCufCZTO++hqf7WESm5N+oUxgxHBlaPYT jjU7juN+y0HmU0v9Y6YGSi27q1IdBUqQ+4V1JO6rnfeJp+IbhUw0rBXXaZp/NJUk+K54 DTxUPC8P9H6D66vIPW+d3B7/6ygl6SXZY6N/x9PW8D3QuD6n/JMjmoM0hGVI0pv+4kBN HYWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731625820; x=1732230620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O5DVuhpbt65Tb2WFhtaXDExhTn0sEn63wQnWqfaY7lM=; b=U8aYR/cVy7oD5pJ37I8y2Kehy/pPyOmgZ2tUvKJYFgKHoBft5C2Lg8bWO1VcJqxJGS qC5922AvfkAL3n7nvazTGupOh5/7t5qhc9ieUYI8/P+1XeCsg26XhOdLOvaamJFD+WE6 jLwqPerVvECeB0jY5I1mvs/psJCR7E5xq/BFTKYADoS7gzoNOGuOVfaMtzZsgSoUjXHP LlSIOZ/QWlv6buxdUo5YhS0w5QjJTm3mcNhqF9o7mTy4LXY4ki38iGcLOOZoltrDoAM+ BK2bjGzMNV4T6X9NUQikoUnKirtqgJPRFm2Re818ovu2PN3k/jyHT3HrOJDmMAe65aWc WnHw== X-Forwarded-Encrypted: i=1; AJvYcCUfsNLduakWt4V9aPmzpknjFihFXEubuMbkBU0HRL/ZZSVzvf8JjdkpOTX8DFDMtt39oSik15obQjlS4NKn@vger.kernel.org, AJvYcCXhFBmvTkkXp+V/Vjpb0meRMKu+8ubZdW0/28+/auRAB1fuZ+DXVoQuuNP//4OVyoOA481gNBbDE78=@vger.kernel.org X-Gm-Message-State: AOJu0Yye+UM7XGbHYXwMTr0W8NagOMhZV7uZpm4XpZUPag90iKhSTmop 7bru9MqvWXo68ELXW3LHagc/H3b4WXPn4KTgQ+tz/xfIt3yNLVBPswZBSg2J X-Google-Smtp-Source: AGHT+IGnLpyW7H9Y1VJWXggAltSHjuIV49gVf56bMpwC75H0RQx3h7POr/4wUCoo2fWL/AswOiZ8hA== X-Received: by 2002:a05:600c:5250:b0:42c:c0d8:bf34 with SMTP id 5b1f17b1804b1-432df679bfdmr1778515e9.0.1731625820340; Thu, 14 Nov 2024 15:10:20 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:20 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 06/22] iio: accel: adxl345: add function to switch measuring Date: Thu, 14 Nov 2024 23:09:46 +0000 Message-Id: <20241114231002.98595-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the powerup / powerdown functions by a generic function to put the sensor in STANDBY, or MEASURE mode. This is needed for several features of the accelerometer. It allows to change e.g. FIFO settings. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 51 ++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 926e397678..bcec3a8e05 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -138,6 +138,37 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *i= ndio_dev, } } =20 +/** + * For lowest power operation, standby mode can be used. In standby mode, + * current consumption is supposed to be reduced to 0.1uA (typical). In th= is + * mode no measurements are made. Placing the device into standby mode + * preserves the contents of FIFO. + * + * Unloading the driver puts the device in standby mode (measuring off). + * + * @st: The device data. + * @en: Enable measurements, else standby mode. + */ +static int adxl345_set_measure_en(struct adxl34x_state *st, bool en) +{ + unsigned int val =3D 0; + int ret; + + val =3D (en) ? ADXL345_POWER_CTL_MEASURE : ADXL345_POWER_CTL_STANDBY; + ret =3D regmap_write(st->regmap, ADXL345_REG_POWER_CTL, val); + if (ret) + return -EINVAL; + + return 0; +} + +static void adxl345_powerdown(void *ptr) +{ + struct adxl34x_state *st =3D ptr; + + adxl345_set_measure_en(st, false); +} + static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 20= 0 400 800 1600 3200" ); @@ -158,16 +189,6 @@ static const struct iio_info adxl345_info =3D { .write_raw_get_fmt =3D adxl345_write_raw_get_fmt, }; =20 -static int adxl345_powerup(void *regmap) -{ - return regmap_write(regmap, ADXL345_REG_POWER_CTL, ADXL345_POWER_CTL_MEAS= URE); -} - -static void adxl345_powerdown(void *regmap) -{ - regmap_write(regmap, ADXL345_REG_POWER_CTL, ADXL345_POWER_CTL_STANDBY); -} - /** * adxl345_core_probe() - probe and setup for the adxl345 accelerometer, * also covers the adxl375 and adxl346 accelerometer @@ -242,14 +263,12 @@ int adxl345_core_probe(struct device *dev, struct reg= map *regmap, return dev_err_probe(dev, -ENODEV, "Invalid device ID: %x, expected %x\n= ", regval, ADXL345_DEVID); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:20 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 07/22] iio: accel: adxl345: initialize IRQ number Date: Thu, 14 Nov 2024 23:09:47 +0000 Message-Id: <20241114231002.98595-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the possibility to claim an interrupt and init the state structure with interrupt number and interrupt line to use. The adxl345 can use two different interrupt lines, mainly to signal FIFO watermark events, single or double tap, activity, etc. Hence, having the interrupt line available is crucial to implement such features. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 1 + drivers/iio/accel/adxl345_core.c | 6 ++++++ drivers/iio/accel/adxl345_i2c.c | 2 +- drivers/iio/accel/adxl345_spi.c | 8 ++++++-- 4 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index 3d5c8719db..cf4132715c 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -62,6 +62,7 @@ struct adxl345_chip_info { }; =20 int adxl345_core_probe(struct device *dev, struct regmap *regmap, + int irq, int (*setup)(struct device*, struct regmap*)); =20 #endif /* _ADXL345_H_ */ diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index bcec3a8e05..57bc530cc3 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include #include @@ -18,6 +19,7 @@ #include "adxl345.h" =20 struct adxl34x_state { + int irq; const struct adxl345_chip_info *info; struct regmap *regmap; }; @@ -194,12 +196,14 @@ static const struct iio_info adxl345_info =3D { * also covers the adxl375 and adxl346 accelerometer * @dev: Driver model representation of the device * @regmap: Regmap instance for the device + * @irq: Interrupt handling for async usage * @setup: Setup routine to be executed right before the standard device * setup * * Return: 0 on success, negative errno on error */ int adxl345_core_probe(struct device *dev, struct regmap *regmap, + int irq, int (*setup)(struct device*, struct regmap*)) { struct adxl34x_state *st; @@ -222,6 +226,8 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, =20 st =3D iio_priv(indio_dev); st->regmap =3D regmap; + + st->irq =3D irq; st->info =3D device_get_match_data(dev); if (!st->info) return -ENODEV; diff --git a/drivers/iio/accel/adxl345_i2c.c b/drivers/iio/accel/adxl345_i2= c.c index 4065b8f7c8..604b706c29 100644 --- a/drivers/iio/accel/adxl345_i2c.c +++ b/drivers/iio/accel/adxl345_i2c.c @@ -27,7 +27,7 @@ static int adxl345_i2c_probe(struct i2c_client *client) if (IS_ERR(regmap)) return dev_err_probe(&client->dev, PTR_ERR(regmap), "Error initializing = regmap\n"); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:22 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 08/22] iio: accel: adxl345: initialize FIFO delay value for SPI Date: Thu, 14 Nov 2024 23:09:48 +0000 Message-Id: <20241114231002.98595-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the possibility to delay FIFO access when SPI is used. According to the datasheet this is needed for the adxl345. When initialization happens over SPI the need for delay is to be signalized, and the delay will be used. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 2 +- drivers/iio/accel/adxl345_core.c | 6 +++++- drivers/iio/accel/adxl345_i2c.c | 2 +- drivers/iio/accel/adxl345_spi.c | 3 +++ 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index cf4132715c..4ba493f636 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -62,7 +62,7 @@ struct adxl345_chip_info { }; =20 int adxl345_core_probe(struct device *dev, struct regmap *regmap, - int irq, + int irq, bool fifo_delay_default, int (*setup)(struct device*, struct regmap*)); =20 #endif /* _ADXL345_H_ */ diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 57bc530cc3..ef3b7d9fb4 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -22,6 +22,7 @@ struct adxl34x_state { int irq; const struct adxl345_chip_info *info; struct regmap *regmap; + bool fifo_delay; /* delay: delay is needed for SPI */ }; =20 #define ADXL345_CHANNEL(index, axis) { \ @@ -197,13 +198,14 @@ static const struct iio_info adxl345_info =3D { * @dev: Driver model representation of the device * @regmap: Regmap instance for the device * @irq: Interrupt handling for async usage + * @fifo_delay_default: Using FIFO with SPI needs delay * @setup: Setup routine to be executed right before the standard device * setup * * Return: 0 on success, negative errno on error */ int adxl345_core_probe(struct device *dev, struct regmap *regmap, - int irq, + int irq, bool fifo_delay_default, int (*setup)(struct device*, struct regmap*)) { struct adxl34x_state *st; @@ -232,6 +234,8 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, if (!st->info) return -ENODEV; =20 + st->fifo_delay =3D fifo_delay_default; + indio_dev->name =3D st->info->name; indio_dev->info =3D &adxl345_info; indio_dev->modes =3D INDIO_DIRECT_MODE; diff --git a/drivers/iio/accel/adxl345_i2c.c b/drivers/iio/accel/adxl345_i2= c.c index 604b706c29..fa1b7e7026 100644 --- a/drivers/iio/accel/adxl345_i2c.c +++ b/drivers/iio/accel/adxl345_i2c.c @@ -27,7 +27,7 @@ static int adxl345_i2c_probe(struct i2c_client *client) if (IS_ERR(regmap)) return dev_err_probe(&client->dev, PTR_ERR(regmap), "Error initializing = regmap\n"); =20 - return adxl345_core_probe(&client->dev, regmap, client->irq, NULL); + return adxl345_core_probe(&client->dev, regmap, client->irq, false, NULL); } =20 static const struct adxl345_chip_info adxl345_i2c_info =3D { diff --git a/drivers/iio/accel/adxl345_spi.c b/drivers/iio/accel/adxl345_sp= i.c index 39e7d71e1d..75940d9c1c 100644 --- a/drivers/iio/accel/adxl345_spi.c +++ b/drivers/iio/accel/adxl345_spi.c @@ -12,6 +12,7 @@ #include "adxl345.h" =20 #define ADXL345_MAX_SPI_FREQ_HZ 5000000 +#define ADXL345_MAX_FREQ_NO_FIFO_DELAY 1500000 =20 static const struct regmap_config adxl345_spi_regmap_config =3D { .reg_bits =3D 8, @@ -41,10 +42,12 @@ static int adxl345_spi_probe(struct spi_device *spi) if (spi->mode & SPI_3WIRE) return adxl345_core_probe(&spi->dev, regmap, spi->irq, + spi->max_speed_hz > ADXL345_MAX_FREQ_NO_FIFO_DELAY, adxl345_spi_setup); else return adxl345_core_probe(&spi->dev, regmap, spi->irq, + spi->max_speed_hz > ADXL345_MAX_FREQ_NO_FIFO_DELAY, NULL); } =20 --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 118B81B85C0; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:22 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 09/22] iio: accel: adxl345: unexpose private defines Date: Thu, 14 Nov 2024 23:09:49 +0000 Message-Id: <20241114231002.98595-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the implementation of features like FIFO-usage, watermark, single tap, double tap, freefall, etc. most of the constants do not need to be exposed in the header file, but are rather of private nature. Reduce namespace pollution by moving them to the core source file. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 33 +--------- drivers/iio/accel/adxl345_core.c | 108 +++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 31 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index 4ba493f636..c9d2a82fa6 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -8,38 +8,9 @@ #ifndef _ADXL345_H_ #define _ADXL345_H_ =20 -#define ADXL345_REG_DEVID 0x00 -#define ADXL345_REG_OFSX 0x1E -#define ADXL345_REG_OFSY 0x1F -#define ADXL345_REG_OFSZ 0x20 -#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) -#define ADXL345_REG_BW_RATE 0x2C -#define ADXL345_REG_POWER_CTL 0x2D -#define ADXL345_REG_DATA_FORMAT 0x31 -#define ADXL345_REG_DATAX0 0x32 -#define ADXL345_REG_DATAY0 0x34 -#define ADXL345_REG_DATAZ0 0x36 -#define ADXL345_REG_DATA_AXIS(index) \ - (ADXL345_REG_DATAX0 + (index) * sizeof(__le16)) - -#define ADXL345_BW_RATE GENMASK(3, 0) -#define ADXL345_BASE_RATE_NANO_HZ 97656250LL - -#define ADXL345_POWER_CTL_MEASURE BIT(3) -#define ADXL345_POWER_CTL_STANDBY 0x00 - -#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */ -#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */ -#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */ +/* Regs and bits needed to be declared globally */ +#define ADXL345_REG_DATA_FORMAT 0x31 /* r/w Data format control */ #define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) /* 3-wire SPI mode */ -#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) /* Enable a self test */ - -#define ADXL345_DATA_FORMAT_2G 0 -#define ADXL345_DATA_FORMAT_4G 1 -#define ADXL345_DATA_FORMAT_8G 2 -#define ADXL345_DATA_FORMAT_16G 3 - -#define ADXL345_DEVID 0xE5 =20 /* * In full-resolution mode, scale factor is maintained at ~4 mg/LSB diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index ef3b7d9fb4..aac49b3d03 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -18,6 +18,114 @@ =20 #include "adxl345.h" =20 +/* ADXL345 register map */ +#define ADXL345_REG_DEVID 0x00 /* r Device ID */ +#define ADXL345_REG_THRESH_TAP 0x1D /* r/w Tap Threshold */ +#define ADXL345_REG_OFSX 0x1E /* r/w X-axis offset */ +#define ADXL345_REG_OFSY 0x1F /* r/w Y-axis offset */ +#define ADXL345_REG_OFSZ 0x20 /* r/w Z-axis offset */ +#define ADXL345_REG_DUR 0x21 /* r/w Tap duration */ +#define ADXL345_REG_LATENT 0x22 /* r/w Tap latency */ +#define ADXL345_REG_WINDOW 0x23 /* r/w Tap window */ +#define ADXL345_REG_THRESH_ACT 0x24 /* r/w Activity threshold */ +#define ADXL345_REG_THRESH_INACT 0x25 /* r/w Inactivity threshold */ +#define ADXL345_REG_TIME_INACT 0x26 /* r/w Inactivity time */ +#define ADXL345_REG_ACT_INACT_CTRL 0x27 /* r/w Axis enable control for */ + /* activity and inactivity */ + /* detection */ +#define ADXL345_REG_THRESH_FF 0x28 /* r/w Free-fall threshold */ +#define ADXL345_REG_TIME_FF 0x29 /* r/w Free-fall time */ +#define ADXL345_REG_TAP_AXIS 0x2A /* r/w Axis control for */ + /* single tap or double tap */ +#define ADXL345_REG_ACT_TAP_STATUS 0x2B /* r Source of single tap or */ + /* double tap */ +#define ADXL345_REG_BW_RATE 0x2C /* r/w Data rate and power */ + /* mode control */ +#define ADXL345_REG_POWER_CTL 0x2D /* r/w Power-saving features */ +#define ADXL345_REG_INT_ENABLE 0x2E /* r/w Interrupt enable control */ +#define ADXL345_REG_INT_MAP 0x2F /* r/w Interrupt mapping */ + /* control */ +#define ADXL345_REG_INT_SOURCE 0x30 /* r Source of interrupts */ +/* NB: ADXL345_REG_DATA_FORMAT 0x31 r/w Data format control, + * (defined in header) + */ + +#define ADXL345_REG_XYZ_BASE 0x32 /* r Base address to read out */ + /* X-, Y- and Z-axis data 0 */ + /* and 1 */ +#define ADXL345_REG_DATA_AXIS(index) \ + (ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16)) +/* NB: having DATAX0 and DATAX1 makes 2x sizeof(__le16) */ + +#define ADXL345_REG_FIFO_CTL 0x38 /* r/w FIFO control */ +#define ADXL345_REG_FIFO_STATUS 0x39 /* r FIFO status */ + +/* DEVID(s) */ +#define ADXL345_DEVID 0xE5 + +/* FIFO */ +#define ADXL345_FIFO_CTL_SAMLPES(x) (0x1f & (x)) +#define ADXL345_FIFO_CTL_TRIGGER(x) (0x20 & ((x) << 5)) /* set 1: INT2, 0:= INT1 */ +#define ADXL345_FIFO_CTL_MODE(x) (0xc0 & ((x) << 6)) + +/* INT_ENABLE, INT_MAP, INT_SOURCE bits */ +#define ADXL345_INT_DATA_READY BIT(7) +#define ADXL345_INT_SINGLE_TAP BIT(6) +#define ADXL345_INT_DOUBLE_TAP BIT(5) +#define ADXL345_INT_ACTIVITY BIT(4) +#define ADXL345_INT_INACTIVITY BIT(3) +#define ADXL345_INT_FREE_FALL BIT(2) +#define ADXL345_INT_WATERMARK BIT(1) +#define ADXL345_INT_OVERRUN BIT(0) + +#define ADXL34X_S_TAP_MSK ADXL345_INT_SINGLE_TAP +#define ADXL34X_D_TAP_MSK ADXL345_INT_DOUBLE_TAP + +/* INT1 or INT2 */ +#define ADXL345_INT1 0 +#define ADXL345_INT2 1 + +/* BW_RATE bits - Bandwidth and output data rate. The default value is + * 0x0A, which translates to a 100 Hz output data rate + */ +#define ADXL345_BW_RATE GENMASK(3, 0) +#define ADXL345_BW_LOW_POWER BIT(4) +#define ADXL345_BASE_RATE_NANO_HZ 97656250LL + +/* POWER_CTL bits */ +#define ADXL345_POWER_CTL_STANDBY 0x00 + +/* NB: + * BIT(0), BIT(1) for explicit wakeup (not implemented) + * BIT(2) for explicit sleep (not implemented) + */ +#define ADXL345_POWER_CTL_MEASURE BIT(3) +#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4) +#define ADXL345_POWER_CTL_LINK BIT(5) + +/* DATA_FORMAT bits */ +#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */ +#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* 1: left-justified (MSB) mode= , 0: right-just'd */ +#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */ +/* NB: BIT(6): 3-wire SPI mode (defined in header) */ + +#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) /* Enable a self test */ +#define ADXL345_DATA_FORMAT_2G 0 +#define ADXL345_DATA_FORMAT_4G 1 +#define ADXL345_DATA_FORMAT_8G 2 +#define ADXL345_DATA_FORMAT_16G 3 + +#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) + +/* The ADXL345 include a 32 sample FIFO + * + * FIFO stores a maximum of 32 entries, which equates to a maximum of 33 + * entries available at any given time because an additional entry is avai= lable + * at the output filter of the device. + * (see datasheet FIFO_STATUS description on "Entries Bits") + */ +#define ADXL34x_FIFO_SIZE 33 + struct adxl34x_state { int irq; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:23 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 10/22] iio: accel: adxl345: set interrupt line to INT1 Date: Thu, 14 Nov 2024 23:09:50 +0000 Message-Id: <20241114231002.98595-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The adxl345 sensor uses one of two interrupt lines, INT1 or INT2. The interrupt lines are used to signal feature events such as watermark reached, single tap, double tap, activity, etc. Only one interrupt line is used and must be configured. The adxl345 default is to use INT1 and in many installations only INT1 is even connected. Therefore configure INT1 as the sensor's default interrupt line. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index aac49b3d03..949847fad2 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -131,6 +131,7 @@ struct adxl34x_state { const struct adxl345_chip_info *info; struct regmap *regmap; bool fifo_delay; /* delay: delay is needed for SPI */ + u8 intio; }; =20 #define ADXL345_CHANNEL(index, axis) { \ @@ -343,6 +344,7 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, return -ENODEV; =20 st->fifo_delay =3D fifo_delay_default; + st->intio =3D ADXL345_INT1; =20 indio_dev->name =3D st->info->name; indio_dev->info =3D &adxl345_info; --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B9491BC9EE; Thu, 14 Nov 2024 23:10:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625830; cv=none; b=nwUIcpNS8uaZVjztbRp/FcyUxtzwsMvoOQwbNmqhPHc+m5rH9ggjglhsyS6IETd59PQGd7Ala+q7gZu9sD7i99RG6PtJuErT6EJwBEjEDiRbF5GPBfV/xrnAreck/KHY3tyaDvRhx1CBAK4XKtg6U1zjLbAgeITKbZVjk+b8fK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625830; c=relaxed/simple; bh=ev2Wu/gXNSjSOij9PQO/6WznPrulhD2PnlcIqOoQrTU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eTE1jz3iQ0k7NXX8zNVKamnW/RQo7WMhyoSGsKri4PJdGofIK2VbnBsX0rAyeuTMTRzoE8CTGbDm6KPXbDq0T8DUx5vWw2be/0lKCWHJl+2Vz52L/ZOPouidV8JHVygKmi+2dE0aeUFclQHXOHO5AIYmGEOlc+chR+QbVfey++s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fyLyteaL; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fyLyteaL" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-43160c5bad8so625735e9.3; Thu, 14 Nov 2024 15:10:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731625826; x=1732230626; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MIqKzIejoyfItsKpIgyA1dC0uX/NO9YX2lqUdNJFK/Y=; b=fyLyteaLJ9juT/+PmM06MrY9QsWdG1vLWHLSiJomtb5EaV6aH+qiQqisrUKBN7Winr tohCe7Y13igiokE4rOvoIJHmTGdD02gIQDVslpSMZmETdRtiDoajfVKK+af7PZ+73q7Q XGzOYCB51zdBhBYD9c9qaBjdMc5xW8QqJ/HypxbWPQVqYja0Xjnt0ABdbeeC/ufthQ6I 2+CTzcf/ofLQe+tMWSC1txmh23IGgq6P/0Trux2f/l7WOz1tStXERXN5TSm5g3SzuaZE Uar/meJAAF/TqqL3sNJLGq2gSggJ7qgya7YQqw6L3Q2o7pk7yrehLH1tCr6Y/MuUbtcI oYew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731625826; x=1732230626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MIqKzIejoyfItsKpIgyA1dC0uX/NO9YX2lqUdNJFK/Y=; b=hPk4AJfiMA8Nr6uryZbheWtEBZGWDmWYwAamQVkMgKeuDE9yjrcNtbodknS+zcEk+G dxaKT1FlHCq1qNQ5gaBn1mjbdu22/qZ7fVZl57XY52jEgOKifosujbX/h5nn/ZuSACVI QrJgvgxy/16GPdT5EG204s4Jw6H5MIVYUJfmzYfkCeqiqtjRgGJPOfT51u32tkebfgWh kM+hu+Dx6JzPDtxXvjRq4/I8B8eahePWJaZPVKz7ixlLjq+YTaifNJHrKQaH4LyKJ1hu OZzbk63Av7/Z1XuyO8+t4ngXOeepYMiODGnOy4HgWcqgi+G0wbG88VNJTavpOZmMxttp ti7w== X-Forwarded-Encrypted: i=1; AJvYcCU/yN0bEq13gx12PF5lCkDrfZrIxxR4Tw0sai+vxL+Os+dKwAVq8X5zilJ0TfAtdaMy0Kvo0nOepyXafbu8@vger.kernel.org, AJvYcCXZiIS9iOnc6IBJDOHlF2ceUQ2IZM6PuCiOJwKZVVc1YMGV3QWcaqnVMxIX21E3tGZJAoEApCOKFIM=@vger.kernel.org X-Gm-Message-State: AOJu0Ywr/x8rnPJQNEM6Cwu5JgaUz/0TVuEIaQQweDGtuM9Zlg9igXah ZZBj2/LvcLMvSWe1CmWEwr6aoG/mqL2E+mytRZAJc1xXsRUrcD82 X-Google-Smtp-Source: AGHT+IEyRmOqna4BTj63MSyNIFOcJGxI/aFIyTftVp+alwqZ6kJ7NbhPXKooO/CAyfDaLlfkwOz1Ew== X-Received: by 2002:a05:600c:1991:b0:42c:ba83:3efa with SMTP id 5b1f17b1804b1-432df6841femr1834715e9.0.1731625825488; Thu, 14 Nov 2024 15:10:25 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:25 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 11/22] iio: accel: adxl345: import adxl345 general data Date: Thu, 14 Nov 2024 23:09:51 +0000 Message-Id: <20241114231002.98595-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use struct adxl34x_platform_data from the included public header of the input driver for ADXL34x with the following argumentation for this approach: - The iio driver for the ADXL34x covers features also implemented in the older input driver. The iio driver will implement the same features but can also benefit from including the common header and struct adxl34x_platform_data. Once complete, the input driver could be faded out. - The fields in the input driver are identical to the fields the IIO implementation will need. Including the header over reimplementing, avoids a duplication of almost identical headers in IIO and iio. - The header for the input driver is public. It provides a public interface for adxl34x related implementation and is not private to the input system. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 949847fad2..57ecf33d60 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -16,6 +16,8 @@ #include #include =20 +#include + #include "adxl345.h" =20 /* ADXL345 register map */ @@ -126,10 +128,15 @@ */ #define ADXL34x_FIFO_SIZE 33 =20 +static const struct adxl34x_platform_data adxl345_default_init =3D { + .tap_axis_control =3D ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, +}; + struct adxl34x_state { int irq; const struct adxl345_chip_info *info; struct regmap *regmap; + struct adxl34x_platform_data data; /* watermark, fifo_mode, etc */ bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; }; @@ -329,6 +336,7 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, unsigned int data_format_mask =3D (ADXL345_DATA_FORMAT_RANGE | ADXL345_DATA_FORMAT_FULL_RES | ADXL345_DATA_FORMAT_SELF_TEST); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:26 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 12/22] iio: accel: adxl345: elaborate iio channel definition Date: Thu, 14 Nov 2024 23:09:52 +0000 Message-Id: <20241114231002.98595-13-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make the channel definition ready to allow for feature implementation for this accelerometer sensor. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 36 +++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 57ecf33d60..7e607534df 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -141,21 +141,33 @@ struct adxl34x_state { u8 intio; }; =20 -#define ADXL345_CHANNEL(index, axis) { \ - .type =3D IIO_ACCEL, \ - .modified =3D 1, \ - .channel2 =3D IIO_MOD_##axis, \ - .address =3D index, \ - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ - BIT(IIO_CHAN_INFO_CALIBBIAS), \ - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_SAMP_FREQ), \ +#define ADXL34x_CHANNEL(index, reg, axis) { \ + .type =3D IIO_ACCEL, \ + .address =3D (reg), \ + .modified =3D 1, \ + .channel2 =3D IIO_MOD_##axis, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index =3D (index), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D 13, \ + .storagebits =3D 16, \ + .shift =3D 0, \ + .endianness =3D IIO_LE, \ + }, \ } =20 +enum adxl34x_chans { + chan_x, chan_y, chan_z, +}; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:27 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 13/22] iio: accel: adxl345: add trigger handler Date: Thu, 14 Nov 2024 23:09:53 +0000 Message-Id: <20241114231002.98595-14-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add basic setup to the interrupt handler function and prepare probe for using and not using the FIFO on the adxl345. Interrupt handler and basic structure integration is needed to evaluate interrupt source register. This is crucial for implementing further features of the sensor. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 106 ++++++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 2 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 7e607534df..dbd07308a7 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -15,6 +15,9 @@ =20 #include #include +#include +#include +#include =20 #include =20 @@ -137,6 +140,7 @@ struct adxl34x_state { const struct adxl345_chip_info *info; struct regmap *regmap; struct adxl34x_platform_data data; /* watermark, fifo_mode, etc */ + u8 int_map; bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; }; @@ -300,6 +304,10 @@ static void adxl345_powerdown(void *ptr) adxl345_set_measure_en(st, false); } =20 +static const struct iio_dev_attr *adxl345_fifo_attributes[] =3D { + NULL, +}; + static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 20= 0 400 800 1600 3200" ); @@ -313,6 +321,76 @@ static const struct attribute_group adxl345_attrs_grou= p =3D { .attrs =3D adxl345_attrs, }; =20 +static const struct iio_buffer_setup_ops adxl345_buffer_ops =3D { +}; + +static int adxl345_get_status(struct adxl34x_state *st, u8 *int_stat) +{ + int ret; + unsigned int regval; + + *int_stat =3D 0; + ret =3D regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); + if (ret) { + pr_warn("%s(): Failed to read INT_SOURCE register\n", __func__); + return -EINVAL; + } + + *int_stat =3D 0xff & regval; + pr_debug("%s(): int_stat 0x%02X (INT_SOURCE)\n", __func__, *int_stat); + + return 0; +} + +/** + * Interrupt handler used for several features of the ADXL345. + * - DATA_READY / FIFO watermark + * - single tap / double tap + * - activity / inactivity + * - freefall detection + * - overrun + * + * @irq: The interrupt number. Having an interrupt imples FIFO_STREAM mode= was + * enabled. Since this is given there will no be further test for being in + * FIFO_BYPASS mode. FIFO_TRIGGER and FIFO_FIFO mode (being similar to + * FIFO_STREAM mode) are not separately implemented so far. Both should be + * work smoothly with the same way of interrupt handling. + * @p: The iio poll function instance, used to derive the device and data. + */ +static irqreturn_t adxl345_trigger_handler(int irq, void *p) +{ + struct iio_dev *indio_dev =3D ((struct iio_poll_func *) p)->indio_dev; + struct adxl34x_state *st =3D iio_priv(indio_dev); + u8 int_stat; + int ret; + + ret =3D adxl345_get_status(st, &int_stat); + if (ret < 0) + goto done; + + /* Ignore already read event by reissued too fast */ + if (int_stat =3D=3D 0x0) + goto done; + + /* evaluation */ + + if (int_stat & ADXL345_INT_OVERRUN) { + pr_debug("%s(): OVERRUN event detected\n", __func__); + goto done; + } + + if (int_stat & (ADXL345_INT_DATA_READY | ADXL345_INT_WATERMARK)) + pr_debug("%s(): WATERMARK or DATA_READY event detected\n", __func__); + + goto done; +done: + + if (indio_dev) + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + static const struct iio_info adxl345_info =3D { .attrs =3D &adxl345_attrs_group, .read_raw =3D adxl345_read_raw, @@ -349,6 +427,7 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, ADXL345_DATA_FORMAT_FULL_RES | ADXL345_DATA_FORMAT_SELF_TEST); const struct adxl34x_platform_data *data; + u8 fifo_ctl; int ret; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); @@ -417,9 +496,32 @@ int adxl345_core_probe(struct device *dev, struct regm= ap *regmap, if (ret < 0) return dev_err_probe(dev, ret, "Failed to add action or reset\n"); =20 - /* Enable measurement mode */ - adxl345_set_measure_en(st, true); + /* Basic common initialization of the driver is done now */ + + if (st->irq) { /* Initialization to prepare for FIFO_STREAM mode */ + ret =3D devm_iio_triggered_buffer_setup_ext(dev, indio_dev, + NULL, + adxl345_trigger_handler, + IIO_BUFFER_DIRECTION_IN, + &adxl345_buffer_ops, + adxl345_fifo_attributes); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup triggered buffer\n"); + + } else { /* Initialization to prepare for FIFO_BYPASS mode (fallback) */ =20 + /* The following defaults to 0x00, anyway */ + fifo_ctl =3D 0x00 | ADXL345_FIFO_CTL_MODE(ADXL_FIFO_BYPASS); + + dev_dbg(dev, "fifo_ctl 0x%02X [0x00]\n", fifo_ctl); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:28 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 14/22] iio: accel: adxl345: read FIFO entries Date: Thu, 14 Nov 2024 23:09:54 +0000 Message-Id: <20241114231002.98595-15-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a function to read the elements of the adxl345 FIFO. This will flush the FIFO, and brings it into a ready state. The read out is used to read the elemnts and to reset the fifo again. The cleanup equally needs a read on the INT_SOURCE register. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index dbd07308a7..57bca112ea 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -140,6 +140,8 @@ struct adxl34x_state { const struct adxl345_chip_info *info; struct regmap *regmap; struct adxl34x_platform_data data; /* watermark, fifo_mode, etc */ + + __le16 fifo_buf[3 * ADXL34x_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); u8 int_map; bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; @@ -321,6 +323,27 @@ static const struct attribute_group adxl345_attrs_grou= p =3D { .attrs =3D adxl345_attrs, }; =20 +/** + * Read number of FIFO entries into *fifo_entries + */ +static int adxl345_get_fifo_entries(struct adxl34x_state *st, int *fifo_en= tries) +{ + unsigned int regval =3D 0; + int ret; + + ret =3D regmap_read(st->regmap, ADXL345_REG_FIFO_STATUS, ®val); + if (ret) { + pr_warn("%s(): Failed to read FIFO_STATUS register\n", __func__); + *fifo_entries =3D 0; + return ret; + } + + *fifo_entries =3D 0x3f & regval; + pr_debug("%s(): fifo_entries %d\n", __func__, *fifo_entries); + + return 0; +} + static const struct iio_buffer_setup_ops adxl345_buffer_ops =3D { }; =20 @@ -362,6 +385,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, voi= d *p) struct iio_dev *indio_dev =3D ((struct iio_poll_func *) p)->indio_dev; struct adxl34x_state *st =3D iio_priv(indio_dev); u8 int_stat; + int fifo_entries; int ret; =20 ret =3D adxl345_get_status(st, &int_stat); @@ -379,9 +403,11 @@ static irqreturn_t adxl345_trigger_handler(int irq, vo= id *p) goto done; } =20 - if (int_stat & (ADXL345_INT_DATA_READY | ADXL345_INT_WATERMARK)) + if (int_stat & (ADXL345_INT_DATA_READY | ADXL345_INT_WATERMARK)) { pr_debug("%s(): WATERMARK or DATA_READY event detected\n", __func__); - + if (adxl345_get_fifo_entries(st, &fifo_entries) < 0) + goto done; + } goto done; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:30 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 15/22] iio: accel: adxl345: reset the FIFO on error Date: Thu, 14 Nov 2024 23:09:55 +0000 Message-Id: <20241114231002.98595-16-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a function to empty the FIFO and reset the INT_SOURCE register. Reading out is used to reset the fifo again. For cleanup also a read on the INT_SOURCE register is needed to allow the adxl345 to issue interrupts again. Without clearing the fields no further interrupts will happen. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 70 ++++++++++++++++++++++++++++---- 1 file changed, 62 insertions(+), 8 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 57bca112ea..ece28825fb 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -344,6 +344,56 @@ static int adxl345_get_fifo_entries(struct adxl34x_sta= te *st, int *fifo_entries) return 0; } =20 +/** + * Read fifo_entries number of elements into *st + * + * It is recommended that a multiple-byte read of all registers be + * performed to prevent a change in data between reads of sequential + * registers. + * That is to read out the data registers X0, X1, Y0, Y1, Z0, Z1 at once. + * + * @st: The instance of the state object of this sensor. + * @fifo_entries: The number of lines in the FIFO referred to as fifo_entr= y, + * a fifo_entry has 3 elements for X, Y and Z direction of 2 bytes each. + */ +static int adxl345_read_fifo_elements(struct adxl34x_state *st, int fifo_e= ntries) +{ + size_t count, ndirs =3D 3; + int i, ret; + + count =3D 2 * ndirs; /* 2 byte per direction */ + for (i =3D 0; i < fifo_entries; i++) { + ret =3D regmap_noinc_read(st->regmap, ADXL345_REG_XYZ_BASE, + st->fifo_buf + (i * count / 2), count); + if (ret) { + pr_warn("%s(): regmap_noinc_read() failed\n", __func__); + return -EFAULT; + } + } + + return 0; +} + +/** + * Empty the fifo. This is needed also in case of overflow or error handli= ng. + * Read out all remaining elements and reset the fifo_entries counter. + * + * @st: The instance to the state object of the sensor. + */ +void adxl345_empty_fifo(struct adxl34x_state *st) +{ + int regval; + int fifo_entries; + + /* In case the HW is not "clean" just read out remaining elements */ + adxl345_get_fifo_entries(st, &fifo_entries); + if (fifo_entries > 0) + adxl345_read_fifo_elements(st, fifo_entries); + + /* Reset the INT_SOURCE register by reading the register */ + regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); +} + static const struct iio_buffer_setup_ops adxl345_buffer_ops =3D { }; =20 @@ -390,30 +440,34 @@ static irqreturn_t adxl345_trigger_handler(int irq, v= oid *p) =20 ret =3D adxl345_get_status(st, &int_stat); if (ret < 0) - goto done; + goto err; =20 /* Ignore already read event by reissued too fast */ if (int_stat =3D=3D 0x0) - goto done; + goto err; =20 /* evaluation */ =20 if (int_stat & ADXL345_INT_OVERRUN) { pr_debug("%s(): OVERRUN event detected\n", __func__); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:32 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 16/22] iio: accel: adxl345: register trigger ops Date: Thu, 14 Nov 2024 23:09:56 +0000 Message-Id: <20241114231002.98595-17-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add trigger options to the sensor driver. Reacting to the sensor events communicated by IRQ, the FIFO handling and the trigger will be core events for further feature implementation. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index ece28825fb..b917b02245 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -15,6 +15,9 @@ =20 #include #include +#include +#include +#include #include #include #include @@ -140,11 +143,13 @@ struct adxl34x_state { const struct adxl345_chip_info *info; struct regmap *regmap; struct adxl34x_platform_data data; /* watermark, fifo_mode, etc */ + struct iio_trigger *trig_dready; =20 __le16 fifo_buf[3 * ADXL34x_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); u8 int_map; bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; + bool watermark_en; }; =20 #define ADXL34x_CHANNEL(index, reg, axis) { \ @@ -415,6 +420,35 @@ static int adxl345_get_status(struct adxl34x_state *st= , u8 *int_stat) return 0; } =20 +/* data ready trigger */ + +static int adxl345_trig_dready(struct iio_trigger *trig, bool state) +{ + struct iio_dev *indio_dev =3D iio_trigger_get_drvdata(trig); + struct adxl34x_state *st =3D iio_priv(indio_dev); + + st->int_map =3D 0x00; + if (state) { + /* Setting also ADXL345_INT_DATA_READY results in just a single + * generated interrupt, and no continuously re-generation. NB that the + * INT_DATA_READY as well as the INT_OVERRUN are managed automatically, + * setting their bits here is not needed. + */ + if (st->watermark_en) + st->int_map |=3D ADXL345_INT_WATERMARK; + + pr_debug("%s(): preparing st->int_map 0x%02X\n", + __func__, st->int_map); + } + + return 0; +} + +static const struct iio_trigger_ops adxl34x_trig_dready_ops =3D { + .validate_device =3D &iio_trigger_validate_own_device, + .set_trigger_state =3D adxl345_trig_dready, +}; + /** * Interrupt handler used for several features of the ADXL345. * - DATA_READY / FIFO watermark --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C0511C2323; Thu, 14 Nov 2024 23:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625839; cv=none; b=gQo7UkeCkimNjI05VUnikrugZoytHfmj5ENtZmsirq1BzFG2qVcogLiKdebNOmzf1ff8dmmJ7ii78N6xEKYrVlKqilOhd4Tv7q09km62Eny+eET+UAqA6dCxB6D3V+HL2u8Nvaq0BzTFQjwfZySkkSwWc54zoyvlmuPXYmGODQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625839; c=relaxed/simple; bh=qR/sCQci0olPDHNGyPvQt4E28w+O0k5TA3wmzOJrj0M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XRixYMxmmZegQ2u++gsHrpaVm2Wra/C206zTOh91DWBpeQtcaXgL1/8bijA7HaXHJ1ARwnepbRoGNqkp/8iDNgPxDcUGkitxJ8iiL8LJ/uJF5fKmHsTcdhXyZdhEc7shjwXPiFizjPKHYlpm7IKFWaTWcGp3FP4f/4qWtFq7Ujc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZTCHNLJl; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZTCHNLJl" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4315dfa3e0bso1419205e9.0; Thu, 14 Nov 2024 15:10:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731625836; x=1732230636; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I1YfXIBJlmygh5jtMiNQIlnvrPVWfGPBojvJxihEMvs=; b=ZTCHNLJlvFHqqghHnCXhuAqGXDStLQvUd0Q6oOvxDj4wKi5JIg3iYZ4zQjhv4gK73V wskTE3SOlTJOfcj5u+HLwcD9WVQbbnDtGufxtD8DvbftU9J/ChDeE2CLmwcThXuL/iVx /kyk7HhJhV8LLEn2ijb2mzimhjlvHjTvqBTnCMaQY10Oj//XUal03mWxNeAq8KraynET cz/BpIljIMgYST8vpSOa40jVghW/qpcfG/82Hj3RiG+8Di9bucIQh/99dPq7+rmTKW/3 i+B+AfZAQNgbtV/ynhUpyLOx+A0+3XiIe2hGTgv1vB+h6tStZAg7sTG3vcLILCTmW0hP MW0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731625836; x=1732230636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I1YfXIBJlmygh5jtMiNQIlnvrPVWfGPBojvJxihEMvs=; b=NHcp3Ho7hGjBTc2Zycvatb/7KzXkIZszTQ2ZOSxUADw+MDlkCMkMEbxUPQbVi06V+I wQnsG3MC0IGGNka7SlbrRPMk12KDApwq3QdB8SxcHvZozVZoyLn5tCv3GEFSIhSejtnJ 2zDyKQU0Dr7bkTV8kHlCf5ITj2w4qV7ieBWgVVzJridcw2emYn9IMkRphbGDUVY3uSzf Mu9MH92RF9pmAvUFzwdyFVmzZ421ukS9T7wcyCd6TeNy7lQVBNrZqCKuhTVmmzYpkrMF jQyDoro9EtExXY7vFSLYAfuk/jvOj2vDIxHDfEXWe51Q785+8TJFqZ3VC7dMI3XZi4+W xXZg== X-Forwarded-Encrypted: i=1; AJvYcCXDGDVM2t7kBP0bVuh/CGk+9M2TtunI9JtlJ1DVMhxY10+srKPKCoqKHzu6pCJjv0zndDN8349+elE1vK1y@vger.kernel.org, AJvYcCXNOa3uXCY4fyamBwFdUeHcf+3iy9IwiFnbbLq+8+k4bbFNCz0yGo/6gclySAxaBiiECk0fn4iqj/A=@vger.kernel.org X-Gm-Message-State: AOJu0Yze7c720rtXyzJvRy86dbopApBT+2GQOTlD4ANPPkvPigwcHo+Q D0SGKTDm1AADswROesoSsVmrbzfl2RrUMFnvHThHjmsH44H57asz X-Google-Smtp-Source: AGHT+IHelWCwPBw7LJw1a+gm+mce0LetN3EoVahQMD1vsZynmcWULUKrOhwig+e5HzuxGMqijhSOKA== X-Received: by 2002:a05:600c:3ca8:b0:431:5316:6752 with SMTP id 5b1f17b1804b1-432df71e06fmr1712075e9.2.1731625835730; Thu, 14 Nov 2024 15:10:35 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:34 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 17/22] iio: accel: adxl345: push FIFO data to iio Date: Thu, 14 Nov 2024 23:09:57 +0000 Message-Id: <20241114231002.98595-18-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add FIFO and hwfifo handling. Add some functions to deal with FIFO entries and configuration. This feature will be needed for e.g. watermark setting. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index b917b02245..f686037df3 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -420,6 +420,41 @@ static int adxl345_get_status(struct adxl34x_state *st= , u8 *int_stat) return 0; } =20 +static int adxl345_push_fifo_data(struct iio_dev *indio_dev, + u8 status, + int fifo_entries) +{ + struct adxl34x_state *st =3D iio_priv(indio_dev); + int ndirs =3D 3; /* 3 directions */ + int i, ret; + + if (fifo_entries <=3D 0) + return true; + + ret =3D adxl345_read_fifo_elements(st, fifo_entries); + if (ret) + return false; + + for (i =3D 0; i < ndirs * fifo_entries; i +=3D ndirs) { + /* To ensure that the FIFO has completely popped, there must be at least= 5 + * us between the end of reading the data registers, signified by the + * transition to register 0x38 from 0x37 or the CS pin going high, and t= he + * start of new reads of the FIFO or reading the FIFO_STATUS register. F= or + * SPI operation at 1.5 MHz or lower, the register addressing portion of= the + * transmission is sufficient delay to ensure the FIFO has completely + * popped. It is necessary for SPI operation greater than 1.5 MHz to + * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 = us + * at 5 MHz operation. + */ + if (st->fifo_delay && (fifo_entries > 1)) + udelay(3); + + iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); + } + + return true; +} + /* data ready trigger */ =20 static int adxl345_trig_dready(struct iio_trigger *trig, bool state) @@ -492,6 +527,9 @@ static irqreturn_t adxl345_trigger_handler(int irq, voi= d *p) if (adxl345_get_fifo_entries(st, &fifo_entries) < 0) goto err; =20 + if (adxl345_push_fifo_data(indio_dev, int_stat, fifo_entries) < 0) + goto err; + iio_trigger_notify_done(indio_dev->trig); } =20 --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 148C21C243C; Thu, 14 Nov 2024 23:10:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625840; cv=none; b=eiuRf5K56SjT8llZvaIVcegpBXw/1Xxya98FBPdSNG7V+2Al0J8UvilSVGzrefrrVtJI2wAAiUC4mBAdHem0LkaWBlnquabn8TZHxmWvIG/Y8C0OqFWEVYrO6aYfy4Qzge3xN3ciISw7NbuCQJ7r5BcAK/QuhH+ZhFphQ2SOr30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625840; c=relaxed/simple; bh=GtWePVG860SxLDAycMC+2V4CVWFP6S+iiM4qVAUho3U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N1FaGCi+uAhXZLQqjy+eyepOPCcpZEcsLmugLrxC9weSMXYZEDge3VDnI8hTqhvfAf3bBul7L5xsqpvaYUA0kMDugG7vyWFTgMqNX4IsMhtIL+vxl//c0qalU6LTripc672N+BzRMogzyqUzpSmnlodcTxV9lz48QSRhF+R+6ls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=m08286w5; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="m08286w5" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-37d5231f71cso161242f8f.2; Thu, 14 Nov 2024 15:10:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731625837; x=1732230637; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oP5cXLy2LL0l0G0KnSB+0lFPN9e6gBigDfbVNZI3xWY=; b=m08286w5ArmrWCDg1NBy+o+Q269+JDzt7B8rUXqFjexip+HIrsD/STMMfWNLwoqQ0u 0GN7kESDfHKIl9R9a3lywiqKY4lTbvM9MDH0n87/hhu/CDjD+lRlk+VvI69iD0meI7dy 2kHM7yteyTyXD7ZrLqIekyaRcgdVzVVnu7OSWcBM34vId2SsBlL5VGELTZ7YxNCTllAx YXVAA/ZTd3JES7d4kHnE4C0cbvfTmhcQs1Xx+GBXYgBcWu4goo9muaRRJe7TJFnSbj8f x0kbfEshJBEaZ1qb+zEvg2qVSRsZxtrEBYNkbLM8iOfq1n2ahn1tisSUj1XlfG+P/Rme GnNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731625837; x=1732230637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oP5cXLy2LL0l0G0KnSB+0lFPN9e6gBigDfbVNZI3xWY=; b=uSkT9ewubvwEZ1qmceCieQvdD/O7NVDMP8uJWBNNSaMzJglcOKR8YRivQi+8OGl/lQ 9lhZxO2vpU66kPXT7QTccMc571wHE+xbtuXLKCzAI3+IIZwsPnvXyztLS8lYdZ1kk/K3 ggjcR98fNQ+b0c7pVPR1fDbnE45LdqNBJtErq8McvEsyw9HPYnbTEtHSKcWJhBNso9o9 9yALQ5P+uv8MYn4XC1P0OMTXp2UK/6Y3RqRnGaPvzL6Gopjhb9N0tSl54VA68HhZ/vXK M6Tz8zm+NUHXQGGnDDRuV7JrbH/m1KBHFxZ/CExFDCp7J1Ek9tVhEPNgMyZ2JL3JZQjj qiOg== X-Forwarded-Encrypted: i=1; AJvYcCXAcUQSdQyx/AyDyyThC+Djelrtbkc4XDtuPhVTmt8zsLcVum5emzW/+AExPcABfLBepM7YhsR981SVVfLU@vger.kernel.org, AJvYcCXkz/gU4tlRUYREO0xYmMi7sETbtVBynPW2ZO10sL4eKxNvyRzdbkSPEbTO6D7bCvBa7SmSfdYhCos=@vger.kernel.org X-Gm-Message-State: AOJu0YxwXE1UL4HPu2dvac6klNLavOvnZN7P7BGAQs/yUk+kkJ+UKomG uWjcSnw4ZWWi9Myg2v6efCxtcCJ9vLeU8DeAJ1ZeXnQNAd4eMvgj X-Google-Smtp-Source: AGHT+IEid8nFGtPXGMNkKaJAjMqJogkHklne/CWbhxjp5u/iP30k9r+qlyzowRLjhI5qX8E5y5EoXg== X-Received: by 2002:a05:600c:1c1f:b0:430:52ec:1e2a with SMTP id 5b1f17b1804b1-432df790752mr1681865e9.7.1731625837305; Thu, 14 Nov 2024 15:10:37 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:36 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 18/22] iio: accel: adxl345: start measure at buffer en/disable Date: Thu, 14 Nov 2024 23:09:58 +0000 Message-Id: <20241114231002.98595-19-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add and initialize the buffer options to use the FIFO and watermark feature of the adxl345 sensor. In this way measure enable will happen in at enabling the buffer. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 105 +++++++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index f686037df3..a5b2efa69e 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -181,6 +181,28 @@ static const struct iio_chan_spec adxl34x_channels[] = =3D { ADXL34x_CHANNEL(2, chan_z, Z), }; =20 +static int adxl345_set_interrupts(struct adxl34x_state *st) +{ + int ret; + unsigned int int_enable =3D st->int_map; + unsigned int int_map; + + /* Any bits set to 0 in the INT map register send their respective + * interrupts to the INT1 pin, whereas bits set to 1 send their respective + * interrupts to the INT2 pin. The intio shall convert this accordingly. + */ + int_map =3D 0xFF & (st->intio ? st->int_map : ~st->int_map); + pr_debug("%s(): Setting INT_MAP 0x%02X\n", __func__, int_map); + + ret =3D regmap_write(st->regmap, ADXL345_REG_INT_MAP, int_map); + if (ret) + return ret; + + pr_debug("%s(): Setting INT_ENABLE 0x%02X\n", __func__, int_enable); + ret =3D regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, int_enable); + return ret; +} + static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -328,6 +350,41 @@ static const struct attribute_group adxl345_attrs_grou= p =3D { .attrs =3D adxl345_attrs, }; =20 +static int adxl345_set_fifo(struct adxl34x_state *st) +{ + struct adxl34x_platform_data *data =3D &st->data; + u8 fifo_ctl; + int ret; + + /* FIFO should be configured while in standby mode */ + adxl345_set_measure_en(st, false); + + /* The watermark bit is set when the number of samples in FIFO + * equals the value stored in the samples bits (register + * FIFO_CTL). The watermark bit is cleared automatically when + * FIFO is read, and the content returns to a value below the + * value stored in the samples bits. + */ + fifo_ctl =3D 0x00 | + ADXL345_FIFO_CTL_SAMLPES(data->watermark) | + ADXL345_FIFO_CTL_TRIGGER(st->intio) | + ADXL345_FIFO_CTL_MODE(data->fifo_mode); + + pr_debug("%s(): fifo_ctl 0x%02X\n", __func__, fifo_ctl); + + /* The watermark bit is set when the number of samples in FIFO + * equals the value stored in the samples bits (register + * FIFO_CTL). The watermark bit is cleared automatically when + * FIFO is read, and the content returns to a value below the + * value stored in the samples bits. + */ + ret =3D regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, fifo_ctl); + if (ret < 0) + return ret; + + return adxl345_set_measure_en(st, true); +} + /** * Read number of FIFO entries into *fifo_entries */ @@ -399,7 +456,50 @@ void adxl345_empty_fifo(struct adxl34x_state *st) regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); } =20 +static int adxl345_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adxl34x_state *st =3D iio_priv(indio_dev); + struct adxl34x_platform_data *data =3D &st->data; + int ret; + + ret =3D adxl345_set_interrupts(st); + if (ret) + return -EINVAL; + + /* Default to FIFO mode: STREAM, since it covers the general usage + * and does not bypass the FIFO + */ + data->fifo_mode =3D ADXL_FIFO_STREAM; + adxl345_set_fifo(st); + + return 0; +} + +static int adxl345_buffer_predisable(struct iio_dev *indio_dev) +{ + struct adxl34x_state *st =3D iio_priv(indio_dev); + struct adxl34x_platform_data *data =3D &st->data; + int ret; + + /* Turn off interrupts */ + st->int_map =3D 0x00; + + ret =3D adxl345_set_interrupts(st); + if (ret) { + pr_warn("%s(): Failed to disable INTs\n", __func__); + return -EINVAL; + } + + /* Set FIFO mode: BYPASS, according to the situation */ + data->fifo_mode =3D ADXL_FIFO_BYPASS; + adxl345_set_fifo(st); + + return 0; +} + static const struct iio_buffer_setup_ops adxl345_buffer_ops =3D { + .postenable =3D adxl345_buffer_postenable, + .predisable =3D adxl345_buffer_predisable, }; =20 static int adxl345_get_status(struct adxl34x_state *st, u8 *int_stat) @@ -609,7 +709,7 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, =20 indio_dev->name =3D st->info->name; indio_dev->info =3D &adxl345_info; - indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->modes =3D INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; indio_dev->channels =3D adxl34x_channels; indio_dev->num_channels =3D ARRAY_SIZE(adxl34x_channels); =20 @@ -669,9 +769,6 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, ret =3D regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, fifo_ctl); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:37 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 19/22] iio: accel: adxl345: prepare FIFO watermark handling Date: Thu, 14 Nov 2024 23:09:59 +0000 Message-Id: <20241114231002.98595-20-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the feature of the adxl345 and related sensors to manage a FIFO in stream mode by a watermark level. Provide means to set the watermark through the IIO api and sysfs interface. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index a5b2efa69e..c99b8176f0 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -288,6 +288,26 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, return -EINVAL; } =20 +static int adxl345_set_watermark(struct iio_dev *indio_dev, unsigned int v= alue) +{ + struct adxl34x_state *st =3D iio_priv(indio_dev); + struct adxl34x_platform_data *data =3D &st->data; + unsigned int fifo_mask =3D 0x1F; + int ret; + + if (value > ADXL34x_FIFO_SIZE) + value =3D ADXL34x_FIFO_SIZE; + pr_debug("%s(): set watermark to 0x%02x\n", __func__, value); + + ret =3D regmap_update_bits(st->regmap, ADXL345_REG_FIFO_CTL, + fifo_mask, value); + if (ret) + return ret; + + data->watermark =3D value; + return 0; +} + static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long mask) @@ -333,7 +353,76 @@ static void adxl345_powerdown(void *ptr) adxl345_set_measure_en(st, false); } =20 +/* fifo */ + +static ssize_t adxl345_get_fifo_enabled(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct adxl34x_state *st =3D iio_priv(indio_dev); + struct adxl34x_platform_data *data =3D &st->data; + + return sysfs_emit(buf, "%d\n", data->fifo_mode); +} + +static ssize_t adxl345_get_fifo_watermark(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct adxl34x_state *st =3D iio_priv(indio_dev); + struct adxl34x_platform_data *data =3D &st->data; + + return sprintf(buf, "%d\n", data->watermark); +} + +static ssize_t watermark_en_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct adxl34x_state *st =3D iio_priv(indio_dev); + + return sysfs_emit(buf, "%d\n", st->watermark_en); +} + +static ssize_t watermark_en_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct adxl34x_state *st =3D iio_priv(indio_dev); + bool val; + + if (kstrtobool(buf, &val)) + return -EINVAL; + st->watermark_en =3D val; + return len; +} + +/* + * NB: The buffer/hwfifo_watermark is a read-only entry to display the + * currently set hardware FIFO watermark. First set a value to buffer0/len= gth. + * This allows to configure buffer0/watermark. After enabling buffer0/enab= le + * the hwfifo_watermark shall show the configured FIFO watermark value. + * + * ref: Documentation/ABI/testing/sysfs-bus-iio + */ +IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1"); +IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max, + __stringify(ADXL34x_FIFO_SIZE)); +static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, + adxl345_get_fifo_watermark, NULL, 0); +static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, + adxl345_get_fifo_enabled, NULL, 0); + +static IIO_DEVICE_ATTR_RW(watermark_en, 0); + static const struct iio_dev_attr *adxl345_fifo_attributes[] =3D { + &iio_dev_attr_hwfifo_watermark_min, + &iio_dev_attr_hwfifo_watermark_max, + &iio_dev_attr_hwfifo_watermark, + &iio_dev_attr_hwfifo_enabled, NULL, }; =20 @@ -343,6 +432,7 @@ static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( =20 static struct attribute *adxl345_attrs[] =3D { &iio_const_attr_sampling_frequency_available.dev_attr.attr, + &iio_dev_attr_watermark_en.dev_attr.attr, NULL }; =20 @@ -648,6 +738,7 @@ static const struct iio_info adxl345_info =3D { .read_raw =3D adxl345_read_raw, .write_raw =3D adxl345_write_raw, .write_raw_get_fmt =3D adxl345_write_raw_get_fmt, + .hwfifo_set_watermark =3D adxl345_set_watermark, }; =20 /** @@ -705,6 +796,9 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, /* some reasonable pre-initialization */ st->data.act_axis_control =3D 0xFF; =20 + /* default is all features turned off */ + st->watermark_en =3D 0; + st->intio =3D ADXL345_INT1; =20 indio_dev->name =3D st->info->name; --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D74521C3F0E; Thu, 14 Nov 2024 23:10:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625844; cv=none; b=PNdGgUPR1pjGj0PWwTHv4n9M2XHhVOBuhAB+Z35fLGag3UkUTsPU3YeH134bo8NE/Fojid36maIydPiPtBlebVlPvLvbiTlvQ5dIFrtoPHUey1PIf9IUiKb2H+/9JuiqOLB6suep9jwPB0JFUMgD2cNqSdf6RduW7QggnIhqUwQ= ARC-Message-Signature: i=1; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:40 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 20/22] iio: accel: adxl345: use FIFO with watermark IRQ Date: Thu, 14 Nov 2024 23:10:00 +0000 Message-Id: <20241114231002.98595-21-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the watermark feature of the adxl345 sensor. The feature uses a FIFO to be configured by the IIO fifo sysfs handles. The sensor configures the FIFO to streaming mode for measurements, or bypass for configuration. The sensor issues an interrupt on the configured line to signal several signals (data available, overrun or watermark reached). The setup allows for extension of further features based on the interrupt handler and the FIFO setup. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index c99b8176f0..ab39fd8eb5 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -854,6 +854,45 @@ int adxl345_core_probe(struct device *dev, struct regm= ap *regmap, if (ret) return dev_err_probe(dev, ret, "Failed to setup triggered buffer\n"); =20 + dev_dbg(dev, "IRQ: allocating data ready trigger\n"); + st->trig_dready =3D devm_iio_trigger_alloc(dev, + "%s-dev%d-dready", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig_dready) + return dev_err_probe(dev, -ENOMEM, + "Failed to setup triggered buffer\n"); + dev_dbg(dev, "IRQ: allocating data ready trigger ok\n"); + + st->trig_dready->ops =3D &adxl34x_trig_dready_ops; + dev_dbg(dev, "IRQ: Setting data ready trigger ops ok\n"); + + iio_trigger_set_drvdata(st->trig_dready, indio_dev); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:42 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 21/22] iio: accel: adxl345: sync FIFO reading with sensor Date: Thu, 14 Nov 2024 23:10:01 +0000 Message-Id: <20241114231002.98595-22-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pause the measurement while reading fifo values. Initially an interrupt is triggered if watermark of the FIFO is reached, or in case of OVERRUN. The sensor stays mute until FIFO is cleared and interrupts are read. Situations now can arise when the watermark is configured to a lower value. While reading the values, new values arrive such that a permanent OVERRUN state of the FIFO is reached, i.e. either the FIFO never gets emptied entirely because of permanently new arriving measurements. No more interrupts will be issued and the setup results in OVERRUN. To avoid such situation, stop measuring while solving an OVERRUN condition and generally reading FIFO entries. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index ab39fd8eb5..8025dfeb84 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -714,6 +714,11 @@ static irqreturn_t adxl345_trigger_handler(int irq, vo= id *p) =20 if (int_stat & (ADXL345_INT_DATA_READY | ADXL345_INT_WATERMARK)) { pr_debug("%s(): WATERMARK or DATA_READY event detected\n", __func__); + + /* Pause measuring, at low watermarks this would easily brick the + * sensor in permanent OVERRUN state + */ + adxl345_set_measure_en(st, false); if (adxl345_get_fifo_entries(st, &fifo_entries) < 0) goto err; =20 @@ -721,12 +726,15 @@ static irqreturn_t adxl345_trigger_handler(int irq, v= oid *p) goto err; =20 iio_trigger_notify_done(indio_dev->trig); + adxl345_set_measure_en(st, true); } =20 goto done; err: iio_trigger_notify_done(indio_dev->trig); + adxl345_set_measure_en(st, false); adxl345_empty_fifo(st); + adxl345_set_measure_en(st, true); return IRQ_NONE; =20 done: --=20 2.39.2 From nobody Sat Nov 23 02:12:47 2024 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D4571C4A1A; Thu, 14 Nov 2024 23:10:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625848; cv=none; b=pkzjs0+6NvigDITStLYJQQEiyRPuU51nMiwurxmaPoAoKbsvgtMdcIpqFGyQeDzuJEp/58WURV3B84ZoKDnFLDW49KFF6dQyjp52sisqC/2Ed94VZbyEeMlc65xP+E7iagt1Eu5XZk9akefLxVmDUvNL8sUSep5TXassmonNyjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731625848; c=relaxed/simple; bh=XVBaT7tI4WC3TxeQZRnASdggvZWpWUDYexXxWgAysew=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=O2zoMDbLPiYaXyIAon9AlaW0+9t+6qe69PoSqKqSbOikrm1HXEPTdtqXPL54WRhuifjMmgPJX1PllP3E5JioXvzN2YhVJnnKK0fMRzjt20SF4o20Kr9HQuZhQqetsJii2si3JL7Lt5Os1KWmcSSRmw+BnC+kAf7HA32eW9SJEdQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Ejp+WL1A; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ejp+WL1A" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3821ae348e3so97513f8f.1; Thu, 14 Nov 2024 15:10:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731625844; x=1732230644; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=76W9ZF4PZtMV17rjIpg8P7SpS5XYC97O8Bnuf6JYvP4=; b=Ejp+WL1AMtpsEjGWpN5jMhfwB/CDkjfAnrl0XP/qSKza0UnpTWjEVrmaY5jW2RnNuT T4XBjdfWD69QYWkC2ibUPnnxO0SKQGyYMsR/G9IvkaHY7v9SYem5ncCdK06QMZa+ZV46 OzCtHLfclvfsz2pEKW87r083u3uDC5hQNhhxi7zqTS3H5iXoO7cx2aGqAvujLijycNkD AcTRMBWsrLgXq0UJo/NtSnaYCVvYpeifTgOdApnkNUZMwcDv7aeAOosBI8dHAUdmFpMh tAbDjFLJyx5qnyOv1EcopFusHPlGb6w/zT+JQfomoaE47Q7tU/ov17P1/tfs7AciLLw8 hbwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731625844; x=1732230644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=76W9ZF4PZtMV17rjIpg8P7SpS5XYC97O8Bnuf6JYvP4=; b=L/gAxQZnGSwqpTPjuj/c7gpdsZ7iiaQykff95s0slyceDNHsEs8tlLrJJ+jIJlAaAc 8qpuInpSdk8FrkcXFqUiRNv2boN1vA22F7RA+UO5/oQVgXY0lbL8k5VUhBIH69BdTzBE YnRxzCXqprT7+Rq24muA37eIyTN1Mm9+D8iC9URKDr7TCLpFbaMEtbl0mOana535G8RN wgh+FD01PmIlJOYxtM3D2RJGdzM+P3Wro1iay24wZfzd/B0pbJTrwBuG76qPhlgEcAwG 0oO/kcr/R1z6S5BKMZelc/e3UTZaF9remMigpoN80HaqZfl4hyeHCL5YPbM4+snkgkJ2 LkjA== X-Forwarded-Encrypted: i=1; AJvYcCVdeTc1Pq8Wor/2cCteo0kwgiprYbE/M1ZzfIJ9oCtmyWR9X1LYG9PaL331DcQZ7UolARvtDwZw7V4=@vger.kernel.org, AJvYcCX9TdDh9cv6ejHE2vltnQXEdyci2mduMws0NyOhZg8mw35ivfpjYjsyEB8naxApY0qSpLa/CKzoh/jBnVi+@vger.kernel.org X-Gm-Message-State: AOJu0YxlBwGI4kFIg5tq0a1DbCTrp744/NL8bL1/2vjnv7jDtJ68xj34 2e1NOADHfahjelwevKIJEeY6N/nvOyc0WYsrH4yI61e/LsEGluJwGklS53Uq X-Google-Smtp-Source: AGHT+IEXex+1ImFX1NZKJrs9laoUabfJkQRS5OoHyNocpuHjQladGWpksvee4OXA8i0s3JZQ6az7LQ== X-Received: by 2002:a05:600c:a44:b0:42c:b870:c52e with SMTP id 5b1f17b1804b1-432df722ad4mr1689025e9.1.1731625844422; Thu, 14 Nov 2024 15:10:44 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab789fasm36464265e9.18.2024.11.14.15.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 15:10:44 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: l.rubusch@gmx.ch, Lothar Rubusch Subject: [PATCH 22/22] iio: accel: adxl345: add debug printout Date: Thu, 14 Nov 2024 23:10:02 +0000 Message-Id: <20241114231002.98595-23-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241114231002.98595-1-l.rubusch@gmail.com> References: <20241114231002.98595-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add debug prints to allow to debug the sensor based on dynamic debug. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 95 ++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 8025dfeb84..e416a50dd0 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -26,6 +26,9 @@ =20 #include "adxl345.h" =20 +/* debugging registers */ +#define DEBUG_ADXL345 0 + /* ADXL345 register map */ #define ADXL345_REG_DEVID 0x00 /* r Device ID */ #define ADXL345_REG_THRESH_TAP 0x1D /* r/w Tap Threshold */ @@ -181,6 +184,78 @@ static const struct iio_chan_spec adxl34x_channels[] = =3D { ADXL34x_CHANNEL(2, chan_z, Z), }; =20 +/* + * Debugging + */ + +__maybe_unused +static void adxl345_debug_registers(const char *func, struct adxl34x_state= *st) +{ +#if DEBUG_ADXL345 =3D=3D 1 + struct regmap *regmap =3D st->regmap; + unsigned int regval =3D 0; + + regmap_read(regmap, ADXL345_REG_THRESH_TAP, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_THRESH_TAP\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_DUR, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_DUR\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_LATENT, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_LATENT\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_WINDOW, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_WINDOW\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_ACT_TAP_STATUS, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_ACT_TAP_STATUS\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_POWER_CTL, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_POWER_CTL\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_INT_ENABLE, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_INT_ENABLE\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_INT_MAP, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_INT_MAP\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_INT_SOURCE, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_INT_SOURCE\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_FIFO_CTL, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_FIFO_CTL\n", + func, 0xff & regval); + + regmap_read(regmap, ADXL345_REG_FIFO_STATUS, ®val); + pr_debug("%s(): DEBUG - 0x%02X\t- ADXL345_REG_FIFO_STATUS\n", + func, 0xff & regval); +# endif +} + +__maybe_unused +static void adxl345_debug_fifo(const char *func, s16 *fifo_buf, int entrie= s_line) +{ +#if DEBUG_ADXL345 =3D=3D 1 + s16 xval, yval, zval; + + xval =3D fifo_buf[0 + entries_line]; + yval =3D fifo_buf[1 + entries_line]; + zval =3D fifo_buf[2 + entries_line]; + + pr_debug("%s(): FIFO[%d] - x=3D%d, y=3D%d, z=3D%d\n", + func, entries_line/3, xval, yval, zval); +#endif +} + static int adxl345_set_interrupts(struct adxl34x_state *st) { int ret; @@ -513,6 +588,8 @@ static int adxl345_read_fifo_elements(struct adxl34x_st= ate *st, int fifo_entries size_t count, ndirs =3D 3; int i, ret; =20 + pr_debug("%s(): fifo_entries =3D %d\n", __func__, fifo_entries); + count =3D 2 * ndirs; /* 2 byte per direction */ for (i =3D 0; i < fifo_entries; i++) { ret =3D regmap_noinc_read(st->regmap, ADXL345_REG_XYZ_BASE, @@ -522,6 +599,7 @@ static int adxl345_read_fifo_elements(struct adxl34x_st= ate *st, int fifo_entries return -EFAULT; } } + adxl345_debug_registers(__func__, st); =20 return 0; } @@ -639,6 +717,7 @@ static int adxl345_push_fifo_data(struct iio_dev *indio= _dev, if (st->fifo_delay && (fifo_entries > 1)) udelay(3); =20 + adxl345_debug_fifo(__func__, st->fifo_buf, i); iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); } =20 @@ -666,6 +745,7 @@ static int adxl345_trig_dready(struct iio_trigger *trig= , bool state) __func__, st->int_map); } =20 + adxl345_debug_registers(__func__, st); return 0; } =20 @@ -697,6 +777,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, voi= d *p) int fifo_entries; int ret; =20 + pr_debug("%s(): IRQ caught!\n", __func__); ret =3D adxl345_get_status(st, &int_stat); if (ret < 0) goto err; @@ -731,6 +812,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, voi= d *p) =20 goto done; err: + pr_debug("%s(): error termination\n", __func__); iio_trigger_notify_done(indio_dev->trig); adxl345_set_measure_en(st, false); adxl345_empty_fifo(st); @@ -738,6 +820,7 @@ static irqreturn_t adxl345_trigger_handler(int irq, voi= d *p) return IRQ_NONE; =20 done: + pr_debug("%s(): regular termination\n", __func__); return IRQ_HANDLED; } =20 @@ -788,6 +871,9 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, st =3D iio_priv(indio_dev); st->regmap =3D regmap; =20 + dev_dbg(dev, "irq '%d'\n", irq); + if (!irq) /* fall back to bypass mode w/o IRQ */ + dev_dbg(dev, "no IRQ, FIFO mode will stay in BYPASS_MODE\n"); st->irq =3D irq; st->info =3D device_get_match_data(dev); if (!st->info) @@ -815,7 +901,11 @@ int adxl345_core_probe(struct device *dev, struct regm= ap *regmap, indio_dev->channels =3D adxl34x_channels; indio_dev->num_channels =3D ARRAY_SIZE(adxl34x_channels); =20 + dev_dbg(dev, "setting up indio_dev ok\n"); + if (setup) { + dev_dbg(dev, "setup() was provided\n"); + /* Perform optional initial bus specific configuration */ ret =3D setup(dev, st->regmap); if (ret) @@ -830,6 +920,8 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, "Failed to set data range\n"); =20 } else { + dev_dbg(dev, "No setup() provided\n"); + /* Enable full-resolution mode (init all data_format bits) */ ret =3D regmap_write(st->regmap, ADXL345_REG_DATA_FORMAT, ADXL345_DATA_FORMAT_FULL_RES); @@ -838,6 +930,7 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, "Failed to set data range\n"); } =20 + dev_dbg(dev, "Retrieving DEVID\n"); ret =3D regmap_read(st->regmap, ADXL345_REG_DEVID, ®val); if (ret < 0) return dev_err_probe(dev, ret, "Error reading device ID\n"); @@ -845,7 +938,9 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, if (regval !=3D ADXL345_DEVID) return dev_err_probe(dev, -ENODEV, "Invalid device ID: %x, expected %x\n= ", regval, ADXL345_DEVID); + dev_dbg(dev, "Retrieving DEVID ok\n"); =20 + dev_dbg(dev, "Registering power down function\n"); ret =3D devm_add_action_or_reset(dev, adxl345_powerdown, st); if (ret < 0) return dev_err_probe(dev, ret, "Failed to add action or reset\n"); --=20 2.39.2