From nobody Sat Nov 23 05:20:02 2024 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC92918C33C for ; Thu, 14 Nov 2024 16:18:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601137; cv=none; b=CrhwNWUR5erXrUHpsFq1dL9z16F+S+iMXk78WoyQPm2k4UPbmaaefWzmSFy0IFuwhNadTToaYAmE/qenjSoW91jhgH+j9IU4O+RQ05mkXXfXWRhN2AzewMGheCPwAzoeWeggnzkQtJUEXEgQ7l48pXfYF5gNbik5AX67adf1nZs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601137; c=relaxed/simple; bh=Eb4pr4WluxpATHyk/B5wEDuQM3N608Zzf1YYtlCp/dw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WQwkYnjmy+KfbgSxZKj8ewDOjnMtu0v6Nx8S2yxmi6nDQ8boCUZIDYgO01B6xp0BYj33lSt4MoECfhdgnc9ujQSBvofvzbPx0NRLKGmqanzaQhjD6soxVQFw6fiSUMkXCpGGpWApBLL+uoRjtE+VIKk+LbiX1GHw9fn8NsEWG4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=FN9smk4z; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="FN9smk4z" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-539e59dadebso912884e87.0 for ; Thu, 14 Nov 2024 08:18:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601134; x=1732205934; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ro7v641M+HDwWifuZZcr9Q07sHhkgURxU5TLhKMU2Mo=; b=FN9smk4zEni5TTrZlNz/bPZesL1r0schg0VCtLsT1Ss0GKqYVMWxVIGZ9GDk/0oW6z +3pubecEYYIEauGVHH6c0p0d90Ri0lpSqstQ2dCTPAiKDRzRW1vLw5KijY1Ax8SP2XBQ qLp7rvt5OZhY8wpXRKOlNYGXMBdPoWokQ15lTpPt18RSbSXQeTGUMXtm9pu1ED+NNEqD EeNtDVRFBHnSs3AZbePAugFxVaYKqk+hePSCqG1ov1PwuqNcQuIl0UyflcLvf3GVzDT3 LbP68PDi9bEpbDLcbfipe5GipoIt2cIVM9memB2NPIJHhHrtGWwcsrsKTytqqhCr5iQB ccHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601134; x=1732205934; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ro7v641M+HDwWifuZZcr9Q07sHhkgURxU5TLhKMU2Mo=; b=OYobp7gZ7bixydA0pLCYwXtmGL6vRGzNOblLfy5zNQEXbhmiww++J+tVwijqM5re2D zZ5Z0oAa6t9Kwlf6Ysx+0pb/waHpMQKZSNVSzEkGPxrN6FvAdhKTjs5vH9lmVyKEKZPN vsC4VXktWalMJKcOkAC7KyyuCtvWwcuU4KJPZzabfAyKCeXQ9f1G56KQi3Fn8v6/9qqm x5sebSRBgDGubWslv/MjYoZkXGoEcxlAyvcc6qBlUuJUflkS1OqrdxBFtI6H6FT++mJf ZFBKLw9P4LxyLhxUau5BpQ4D1Qme2nL5YwY/x2p5V++i8v224HRYyzp8H92cyrqWrq1w SB5Q== X-Forwarded-Encrypted: i=1; AJvYcCWbsnDiOKXH7dJWvA4ZDNxTxTUEpG/tB1N3RSLVnSdGJAenC26Yj3TnESBsZZy1tm4HL3OwgZx19y9H0t4=@vger.kernel.org X-Gm-Message-State: AOJu0Yx4BMcuj5J+mPozCI0ss/cdTm9/s46iJJzjND/QXD8nJsuak04M dOM1MNkY9r9/xJ5/WI3nf2u25kfKWLPA4rrXi8J439VqkU4dVhAgZwFzwrgBRi8= X-Google-Smtp-Source: AGHT+IErvh7GZ5g5xv9y/mHNwbC72YxK/U2el7s2R5QBHLBxBaMXMwoD7jtczGtgvCVqx0SU+SjOAw== X-Received: by 2002:a05:6512:baa:b0:53d:a34d:9faa with SMTP id 2adb3069b0e04-53da34da11emr2749757e87.45.1731601133876; Thu, 14 Nov 2024 08:18:53 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da265e16sm28762605e9.12.2024.11.14.08.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:53 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 05/15] iommu/riscv: use data structure instead of individual values Date: Thu, 14 Nov 2024 17:18:50 +0100 Message-ID: <20241114161845.502027-22-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zong Li The parameter will be increased when we need to set up more bit fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 3fe4ceba8dd3..9d7945dc3c24 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1001,7 +1001,7 @@ static void riscv_iommu_iotlb_inval(struct riscv_iomm= u_domain *domain, * interim translation faults. */ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, - struct device *dev, u64 fsc, u64 ta) + struct device *dev, struct riscv_iommu_dc *new_dc) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); struct riscv_iommu_dc *dc; @@ -1035,10 +1035,10 @@ static void riscv_iommu_iodir_update(struct riscv_i= ommu_device *iommu, for (i =3D 0; i < fwspec->num_ids; i++) { dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); tc =3D READ_ONCE(dc->tc); - tc |=3D ta & RISCV_IOMMU_DC_TC_V; + tc |=3D new_dc->ta & RISCV_IOMMU_DC_TC_V; =20 - WRITE_ONCE(dc->fsc, fsc); - WRITE_ONCE(dc->ta, ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->fsc, new_dc->fsc); + WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1315,20 +1315,20 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); - u64 fsc, ta; + struct riscv_iommu_dc dc =3D {0}; =20 if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) return -ENODEV; =20 - fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); - ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | - RISCV_IOMMU_PC_TA_V; + dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); + dc.ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | + RISCV_IOMMU_PC_TA_V; =20 if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; =20 - riscv_iommu_iodir_update(iommu, dev, fsc, ta); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; =20 @@ -1419,9 +1419,12 @@ static int riscv_iommu_attach_blocking_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_dc dc =3D {0}; + + dc.fsc =3D RISCV_IOMMU_FSC_BARE; =20 /* Make device context invalid, translation requests will fault w/ #258 */ - riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 @@ -1440,8 +1443,12 @@ static int riscv_iommu_attach_identity_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_dc dc =3D {0}; + + dc.fsc =3D RISCV_IOMMU_FSC_BARE; + dc.ta =3D RISCV_IOMMU_PC_TA_V; =20 - riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, RISCV_IOMMU_PC= _TA_V); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 --=20 2.47.0