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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da2800absm28573255e9.25.2024.11.14.08.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:47 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 01/15] irqchip/riscv-imsic: Use hierarchy to reach irq_set_affinity Date: Thu, 14 Nov 2024 17:18:46 +0100 Message-ID: <20241114161845.502027-18-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to support IRQ domains which reside between the leaf domains and IMSIC, put the IMSIC implementation of irq_set_affinity into its chip. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index c708780e8760..5d7c30ad8855 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -96,9 +96,8 @@ static int imsic_irq_set_affinity(struct irq_data *d, con= st struct cpumask *mask bool force) { struct imsic_vector *old_vec, *new_vec; - struct irq_data *pd =3D d->parent_data; =20 - old_vec =3D irq_data_get_irq_chip_data(pd); + old_vec =3D irq_data_get_irq_chip_data(d); if (WARN_ON(!old_vec)) return -ENOENT; =20 @@ -116,13 +115,13 @@ static int imsic_irq_set_affinity(struct irq_data *d,= const struct cpumask *mask return -ENOSPC; =20 /* Point device to the new vector */ - imsic_msi_update_msg(d, new_vec); + imsic_msi_update_msg(irq_get_irq_data(d->irq), new_vec); =20 /* Update irq descriptors with the new vector */ - pd->chip_data =3D new_vec; + d->chip_data =3D new_vec; =20 - /* Update effective affinity of parent irq data */ - irq_data_update_effective_affinity(pd, cpumask_of(new_vec->cpu)); + /* Update effective affinity */ + irq_data_update_effective_affinity(d, cpumask_of(new_vec->cpu)); =20 /* Move state of the old vector to the new vector */ imsic_vector_move(old_vec, new_vec); @@ -135,6 +134,9 @@ static struct irq_chip imsic_irq_base_chip =3D { .name =3D "IMSIC", .irq_mask =3D imsic_irq_mask, .irq_unmask =3D imsic_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity =3D imsic_irq_set_affinity, +#endif .irq_retrigger =3D imsic_irq_retrigger, .irq_compose_msi_msg =3D imsic_irq_compose_msg, .flags =3D IRQCHIP_SKIP_SET_WAKE | @@ -245,7 +247,7 @@ static bool imsic_init_dev_msi_info(struct device *dev, if (WARN_ON_ONCE(domain !=3D real_parent)) return false; #ifdef CONFIG_SMP - info->chip->irq_set_affinity =3D imsic_irq_set_affinity; + info->chip->irq_set_affinity =3D irq_chip_set_affinity_parent; #endif break; default: --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 634CC8F62 for ; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da265c45sm28633555e9.11.2024.11.14.08.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:49 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 02/15] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP Date: Thu, 14 Nov 2024 17:18:47 +0100 Message-ID: <20241114161845.502027-19-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide a domain bus token for the upcoming support for the RISC-V IOMMU interrupt remapping domain, which needs to be distinguished from NEXUS domains. The new token name is generic, as the only information that needs to be conveyed is that the IRQ domain will remap MSIs, i.e. there's nothing RISC-V specific to convey. Signed-off-by: Andrew Jones --- include/linux/irqdomain_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h index 36653e2ee1c9..676eca8147ae 100644 --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -27,6 +27,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_AMDVI, DOMAIN_BUS_DEVICE_MSI, DOMAIN_BUS_WIRED_TO_MSI, + DOMAIN_BUS_MSI_REMAP, }; =20 #endif /* _LINUX_IRQDOMAIN_DEFS_H */ --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 171E9185B48 for ; Thu, 14 Nov 2024 16:18:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601134; cv=none; b=qL5HC0Hhy1iz2Hu2cP95RNWVm6JxSiQJrit1Od1qrWuli3GrumbopXz1cmAlKNUaKdvegC3hRYM8PyhUhXHTc1R8aIFmGHUReAwhlmME4EzImt40ORepXHojzhqRfrhHpSyNfCIa5E0IqSWKhqWFvrR+gjT8O+jWvx189KjSRok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601134; c=relaxed/simple; bh=NzQJBoC/AMGjdcz5fUxYJHaJ2T5WgutxrlJ2H2gtLTs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CPCPvBvIN0G0afEH1qNCQV1jfmPHlNBzKaKlJKrYHnD6qXgOtDg+ljwi5FhCXpOLH4LcqIyEtstAehIb/nhtIUdkPVGe4BPhmLtWS9y31sfs9y3ihtqQ6kCv1Xx7f9aChqZHYvaKKk9kE+/xkOAaWvQYw/vuakQLXB/Qnit5qUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=h5B7kqKt; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="h5B7kqKt" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-539f1292a9bso877128e87.2 for ; Thu, 14 Nov 2024 08:18:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601131; x=1732205931; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EgkdpOYsLIOn0iKAKl5fgt6eXL8Mzl+XIucJ8fWc9TA=; b=h5B7kqKtNlz0keBSJ6L9z3uNVroLZMvCO7rHbNBSELLix0MPQeWidHSSHgtozh1Qxw rQPbbka2ZCerR68GE6loC6UUBnuJgjWC2dipbRo1u+d/+IbwTKwgPmK0C5patPP99VO7 Jrx2i/dCcEN1+Lx9ZJyT+zXgmHNCmGIkdvqLS5U6PvnrW6/IVPYrPNhPMzSjMsaV1jHB lpfIsgIl/7trYNUNxGhyFshmWivhzB7PQl7jvxvzp1JJPBrOd1VbOORPLl3Bi1X0ENjm EujcdBFGfqLe9w3q1AO508CZz3eVRaW7WMhf3RtuTPUodQMDt0Rk3kQ/DQ+DseJVBTN5 RdFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601131; x=1732205931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EgkdpOYsLIOn0iKAKl5fgt6eXL8Mzl+XIucJ8fWc9TA=; b=gNPD6XXof362hMIKdnS6zYp7PRAxn0QCVpG3d1Q6PE1biMnHDv5lW+lspbvUbE9zlm 7dxCTpZZvM40Rin3tD9cutLDSQoYnKjajQGUJj8T96MM7B+S3cgbrBP2Bzm5xALwbkrc MTM9z72bZkAi/0q4MR3jMiV4oyC2YxX00kH/SAiaqmukMM2nJSCPkaEPgC5lJZB5lPbq uekREv6KG+eTbwDLLUa/SsUUuBekbkNo5Dh9lBI6x6ELfBHyyCNfJn8u8O4RgR9a8GEL PCNLpGklnxuSgGT5VAdMo8qtWMbLHWOOc7/jSwayGI4SSlYMua4NxEHqhaMN09Om7t1R 5NbA== X-Forwarded-Encrypted: i=1; AJvYcCUFJ/ZfIhVID7icCAqXIKlFYkiDFe5aUvMivwzLZUyvfNenG4cn1/LV/zxP3XgyLGBI8yMx6Sb/K4HtbFI=@vger.kernel.org X-Gm-Message-State: AOJu0YzerytfxRbdmbkO5m33S+aqaw/1hlF7JW2eKyvl1qENrln+eBML BdyMfuAHgyHxFsQ9LGVZUjpkiuCmfhxNLu1vhwYTkBR/RpYe5XrB0lHv/29hrxQ= X-Google-Smtp-Source: AGHT+IFd0CnkIMN5l0Pz4D+G0QBgRZi3KYTDXcb5xA9gQJqvW8wTertCqu9+xj4IWnW1G55hIkNGVw== X-Received: by 2002:a05:6512:3ca5:b0:539:f607:1d2b with SMTP id 2adb3069b0e04-53d862b45e5mr14144215e87.7.1731601131046; Thu, 14 Nov 2024 08:18:51 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac1f409sm24906005e9.37.2024.11.14.08.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:50 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 03/15] irqchip/riscv-imsic: Add support for DOMAIN_BUS_MSI_REMAP Date: Thu, 14 Nov 2024 17:18:48 +0100 Message-ID: <20241114161845.502027-20-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike a child of an MSI NEXUS domain, a child of an MSI_REMAP domain will not invoke init_dev_msi_info() with 'domain' equal to 'msi_parent_domain'. This is because the MSI_REMAP domain implements init_dev_msi_info() with msi_parent_init_dev_msi_info(), which makes 'domain' point to the NEXUS (IMSIC) domain, while keeping 'msi_parent_domain' pointing to itself. The rest of the IMSIC init_dev_msi_info() implementation works for MSI_REMAP domains, though, so there's nothing to do to add support except accept the token. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 5d7c30ad8855..6a7d7fefda6a 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -246,6 +246,8 @@ static bool imsic_init_dev_msi_info(struct device *dev, case DOMAIN_BUS_NEXUS: if (WARN_ON_ONCE(domain !=3D real_parent)) return false; + fallthrough; + case DOMAIN_BUS_MSI_REMAP: #ifdef CONFIG_SMP info->chip->irq_set_affinity =3D irq_chip_set_affinity_parent; #endif --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CCF618A92A for ; Thu, 14 Nov 2024 16:18:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601136; cv=none; b=Rimbu6Kshd9Y5lfutidn69v+c936jg5FC3x9Z/vInpuuYVb5ydvp3b+IQkUJShvscpYnZo/A3bLgTK7rR/SUCLzBn97I0RtjKsvNe9rkt9kIZBv/6WsARvwY7JMUpL0K4y5mP4A+oOPwsZFvZdXWzvox7HFnbRgfQPAnKspkEF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601136; c=relaxed/simple; bh=0mPWdQkW2KKBDaAhQDqapvf02Htw+fq40OqWkKngxqU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CsJNGTvVXyufk4bJbcBZVM+E7UbLMArkJSC/StRDTCG/kR/GKAoa2tCHqDmAOTeoaiDDNc/KbKoX+4OT0et6K/ELysBWFgMP9LH/10jBy20nCuK13Zm4dhrzr5IcXVgxbcLrd9FrUHWvber7koFBZI1FsJ4soHtpiGDvutPD2Ro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=oHbOPHBU; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="oHbOPHBU" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-431695fa98bso6928265e9.3 for ; Thu, 14 Nov 2024 08:18:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601132; x=1732205932; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o3RScEb/zQMeNBIY0PtZD1/ZjJQ2IegD9nNkwkqM6gc=; b=oHbOPHBUelHfY0VEbF0nTmwmxbT5sLJwpWWYtzvmb48Fx+muiDlYOrzYqK+2RW7F5c gCRJK3btEmsj1XrAz7nO9vE+d1I+Taeglw3B3cErFh7V6pMpzrF0QwMgJ92XZmUtIEcQ Yue6uT096Iyc58nVKpJ+Jpoe22VG1VokY0zMrcNia0AcLC8hv0CNOEwmgp+nBt+ZrMC9 z1msiUAqTSxt62HmbtiQ3rVAtDIBtAr2dJYL0tUUoaDGLKRcwHovCSZ9WagjA7zAR3bS 61pPNa8NoyHD3IyJYH1h/gmUUpGuJHaLOjxED+467qRemMjtl8cCjCnOSuRFqOPQu27K hfcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601132; x=1732205932; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o3RScEb/zQMeNBIY0PtZD1/ZjJQ2IegD9nNkwkqM6gc=; b=D8+ZWXUQcHaoF1M0zlMTNIT7V4AG/Z5W1O/hpacxsLE3QWLeW6aqRgZMb36lq4SM9A 1TuaQj24L5Pfnu6zHyLmMjEUNtFO1ng/wnm8rdUHcPn4S2O0SCAeBclQAquuk8lkvG3q 5oTBwVqKAX0306cJckoSNHm/nwm9ef8PTHFtv7U8B6Jn5cCQPchXW5tawyfCqxm90x// njOHVedHCFlrhV0ChslhQgkkJsSiaceO/KIaETkZpaOnZAgcL7gWa8MfzrcPsz6Ydnv+ 8nVjiWNf8USxVlWJliq1WgV6bgOUiMYey9rcVteNDcBCS7AfxeyIQddlsJk9QPsB0NEH 2hdA== X-Forwarded-Encrypted: i=1; AJvYcCUUJte4vepWRoBeTQ4ZJRGjCyxZlI4Y0eBNr+LXL/NqBHjbfWUd92CoVMy4tHunpf6nF/azW/g6CJ4gsyE=@vger.kernel.org X-Gm-Message-State: AOJu0Yxik+AlItxlNtn6zJogfDklXYMYeCsgOWSoggmxo1WJeJLuqxEY 7NI6Fy6VnljRAO8LwcA2cBzEMVJppyold9ejiOVtWYTQjPm659qEUPjEh0qtXe4= X-Google-Smtp-Source: AGHT+IETarykQuvm6+z3/CASGfAXpcrdoszeWN3rsEIL+bc92gQplNjgpnYXoIwCDFze+tOTvORF1Q== X-Received: by 2002:a05:600c:3c8f:b0:431:4e25:fe42 with SMTP id 5b1f17b1804b1-432b751e28fmr192523985e9.32.1731601132365; Thu, 14 Nov 2024 08:18:52 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab72184sm24967935e9.2.2024.11.14.08.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:51 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 04/15] iommu/riscv: report iommu capabilities Date: Thu, 14 Nov 2024 17:18:49 +0100 Message-ID: <20241114161845.502027-21-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Report RISC-V IOMMU capabilities required by VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 8a05def774bd..3fe4ceba8dd3 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1462,6 +1462,17 @@ static struct iommu_group *riscv_iommu_device_group(= struct device *dev) return generic_device_group(dev); } =20 +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + case IOMMU_CAP_DEFERRED_FLUSH: + return true; + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandl= e_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1526,6 +1537,7 @@ static void riscv_iommu_release_device(struct device = *dev) static const struct iommu_ops riscv_iommu_ops =3D { .pgsize_bitmap =3D SZ_4K, .of_xlate =3D riscv_iommu_of_xlate, + .capable =3D riscv_iommu_capable, .identity_domain =3D &riscv_iommu_identity_domain, .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC92918C33C for ; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da265e16sm28762605e9.12.2024.11.14.08.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:53 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 05/15] iommu/riscv: use data structure instead of individual values Date: Thu, 14 Nov 2024 17:18:50 +0100 Message-ID: <20241114161845.502027-22-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zong Li The parameter will be increased when we need to set up more bit fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 3fe4ceba8dd3..9d7945dc3c24 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1001,7 +1001,7 @@ static void riscv_iommu_iotlb_inval(struct riscv_iomm= u_domain *domain, * interim translation faults. */ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, - struct device *dev, u64 fsc, u64 ta) + struct device *dev, struct riscv_iommu_dc *new_dc) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); struct riscv_iommu_dc *dc; @@ -1035,10 +1035,10 @@ static void riscv_iommu_iodir_update(struct riscv_i= ommu_device *iommu, for (i =3D 0; i < fwspec->num_ids; i++) { dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); tc =3D READ_ONCE(dc->tc); - tc |=3D ta & RISCV_IOMMU_DC_TC_V; + tc |=3D new_dc->ta & RISCV_IOMMU_DC_TC_V; =20 - WRITE_ONCE(dc->fsc, fsc); - WRITE_ONCE(dc->ta, ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->fsc, new_dc->fsc); + WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1315,20 +1315,20 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); - u64 fsc, ta; + struct riscv_iommu_dc dc =3D {0}; =20 if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) return -ENODEV; =20 - fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); - ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | - RISCV_IOMMU_PC_TA_V; + dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); + dc.ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | + RISCV_IOMMU_PC_TA_V; =20 if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; =20 - riscv_iommu_iodir_update(iommu, dev, fsc, ta); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; =20 @@ -1419,9 +1419,12 @@ static int riscv_iommu_attach_blocking_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_dc dc =3D {0}; + + dc.fsc =3D RISCV_IOMMU_FSC_BARE; =20 /* Make device context invalid, translation requests will fault w/ #258 */ - riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 @@ -1440,8 +1443,12 @@ static int riscv_iommu_attach_identity_domain(struct= iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da27fc8esm29713515e9.21.2024.11.14.08.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:54 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 06/15] iommu/riscv: support GSCID and GVMA invalidation command Date: Thu, 14 Nov 2024 17:18:51 +0100 Message-ID: <20241114161845.502027-23-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zong Li This patch adds a ID Allocator for GSCID and a wrap for setting up GSCID in IOTLB invalidation command. Set up iohgatp to enable second stage table and flush stage-2 table if the GSCID is set. The GSCID of domain should be freed when release domain. GSCID will be allocated for parent domain in nested IOMMU process. Signed-off-by: Zong Li Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-bits.h | 7 +++++++ drivers/iommu/riscv/iommu.c | 32 ++++++++++++++++++++++++++------ 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-b= its.h index 98daf0e1a306..d72b982cf9bf 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -715,6 +715,13 @@ static inline void riscv_iommu_cmd_inval_vma(struct ri= scv_iommu_command *cmd) cmd->dword1 =3D 0; } =20 +static inline void riscv_iommu_cmd_inval_gvma(struct riscv_iommu_command *= cmd) +{ + cmd->dword0 =3D FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINV= AL_OPCODE) | + FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVM= A); + cmd->dword1 =3D 0; +} + static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_comma= nd *cmd, u64 addr) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 9d7945dc3c24..ef38a1bb3eca 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -45,6 +45,10 @@ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) =20 +/* IOMMU GSCID allocation namespace. */ +static DEFINE_IDA(riscv_iommu_gscids); +#define RISCV_IOMMU_MAX_GSCID (BIT(16) - 1) + /* Device resource-managed allocations */ struct riscv_iommu_devres { void *addr; @@ -801,6 +805,7 @@ struct riscv_iommu_domain { struct list_head bonds; spinlock_t lock; /* protect bonds list updates. */ int pscid; + int gscid; bool amo_enabled; int numa_node; unsigned int pgd_mode; @@ -954,15 +959,20 @@ static void riscv_iommu_iotlb_inval(struct riscv_iomm= u_domain *domain, =20 /* * IOTLB invalidation request can be safely omitted if already sent - * to the IOMMU for the same PSCID, and with domain->bonds list + * to the IOMMU for the same PSCID/GSCID, and with domain->bonds list * arranged based on the device's IOMMU, it's sufficient to check * last device the invalidation was sent to. */ if (iommu =3D=3D prev) continue; =20 - riscv_iommu_cmd_inval_vma(&cmd); - riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); + if (domain->gscid) { + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, domain->gscid); + } else { + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); + } if (len && len < RISCV_IOMMU_IOTLB_INVAL_LIMIT) { for (iova =3D start; iova < end; iova +=3D PAGE_SIZE) { riscv_iommu_cmd_inval_set_addr(&cmd, iova); @@ -1039,6 +1049,7 @@ static void riscv_iommu_iodir_update(struct riscv_iom= mu_device *iommu, =20 WRITE_ONCE(dc->fsc, new_dc->fsc); WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->iohgatp, new_dc->iohgatp); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1287,8 +1298,10 @@ static void riscv_iommu_free_paging_domain(struct io= mmu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 - if ((int)domain->pscid > 0) + if (domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); + if (domain->gscid > 0) + ida_free(&riscv_iommu_gscids, domain->gscid); =20 riscv_iommu_pte_free(domain, _io_pte_entry(pfn, _PAGE_TABLE), NULL); kfree(domain); @@ -1320,8 +1333,15 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) return -ENODEV; =20 - dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); + if (domain->gscid) { + dc.iohgatp =3D FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, domain->pgd_mode)= | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, virt_to_pfn(domain->pgd_roo= t)); + } else { + dc.fsc =3D FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); + } + dc.ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; =20 --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FB1B19597F for ; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac1f94asm25135835e9.39.2024.11.14.08.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:59 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 07/15] iommu/riscv: Move definitions to iommu.h Date: Thu, 14 Nov 2024 17:18:52 +0100 Message-ID: <20241114161845.502027-24-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to add the interrupt remapping support in a separate file, share definitions through the header, as well as making some functions public. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-bits.h | 4 ++ drivers/iommu/riscv/iommu.c | 71 ++++---------------------------- drivers/iommu/riscv/iommu.h | 54 ++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 62 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-b= its.h index d72b982cf9bf..d3d98dbed709 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -36,6 +36,10 @@ #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0) #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60) =20 +/* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=3D> PPN[53:10] */ +#define riscv_iommu_phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << = 10)) +#define riscv_iommu_ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << = 12)) + /* 5.3 IOMMU Capabilities (64bits) */ #define RISCV_IOMMU_REG_CAPABILITIES 0x0000 #define RISCV_IOMMU_CAPABILITIES_VERSION GENMASK_ULL(7, 0) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index ef38a1bb3eca..6e8ea3d22ff5 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -24,23 +24,10 @@ #include "iommu-bits.h" #include "iommu.h" =20 -/* Timeouts in [us] */ -#define RISCV_IOMMU_QCSR_TIMEOUT 150000 -#define RISCV_IOMMU_QUEUE_TIMEOUT 150000 -#define RISCV_IOMMU_DDTP_TIMEOUT 10000000 -#define RISCV_IOMMU_IOTINVAL_TIMEOUT 90000000 - /* Number of entries per CMD/FLT queue, should be <=3D INT_MAX */ #define RISCV_IOMMU_DEF_CQ_COUNT 8192 #define RISCV_IOMMU_DEF_FQ_COUNT 4096 =20 -/* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=3D> PPN[53:10] */ -#define phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << 10)) -#define ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << 12)) - -#define dev_to_iommu(dev) \ - iommu_get_iommu_dev(dev, struct riscv_iommu_device, iommu) - /* IOMMU PSCID allocation namespace. */ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) @@ -177,7 +164,7 @@ static int riscv_iommu_queue_alloc(struct riscv_iommu_d= evice *iommu, if (!queue->base) return -ENOMEM; =20 - qb =3D phys_to_ppn(queue->phys) | + qb =3D riscv_iommu_phys_to_ppn(queue->phys) | FIELD_PREP(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, logsz); =20 /* Update base register and read back to verify hw accepted our write */ @@ -480,15 +467,15 @@ static irqreturn_t riscv_iommu_cmdq_process(int irq, = void *data) } =20 /* Send command to the IOMMU command queue */ -static void riscv_iommu_cmd_send(struct riscv_iommu_device *iommu, - struct riscv_iommu_command *cmd) +void riscv_iommu_cmd_send(struct riscv_iommu_device *iommu, + struct riscv_iommu_command *cmd) { riscv_iommu_queue_send(&iommu->cmdq, cmd, sizeof(*cmd)); } =20 /* Send IOFENCE.C command and wait for all scheduled commands to complete.= */ -static void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, - unsigned int timeout_us) +void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, + unsigned int timeout_us) { struct riscv_iommu_command cmd; unsigned int prod; @@ -614,7 +601,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct= riscv_iommu_device *iomm do { ddt =3D READ_ONCE(*(unsigned long *)ddtp); if (ddt & RISCV_IOMMU_DDTE_V) { - ddtp =3D __va(ppn_to_phys(ddt)); + ddtp =3D __va(riscv_iommu_ppn_to_phys(ddt)); break; } =20 @@ -622,7 +609,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct= riscv_iommu_device *iomm if (!ptr) return NULL; =20 - new =3D phys_to_ppn(__pa(ptr)) | RISCV_IOMMU_DDTE_V; + new =3D riscv_iommu_phys_to_ppn(__pa(ptr)) | RISCV_IOMMU_DDTE_V; old =3D cmpxchg_relaxed((unsigned long *)ddtp, ddt, new); =20 if (old =3D=3D ddt) { @@ -687,7 +674,7 @@ static int riscv_iommu_iodir_alloc(struct riscv_iommu_d= evice *iommu) if (ddtp & RISCV_IOMMU_DDTP_BUSY) return -EBUSY; =20 - iommu->ddt_phys =3D ppn_to_phys(ddtp); + iommu->ddt_phys =3D riscv_iommu_ppn_to_phys(ddtp); if (iommu->ddt_phys) iommu->ddt_root =3D devm_ioremap(iommu->dev, iommu->ddt_phys, PAGE_SIZE); @@ -734,7 +721,7 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iomm= u_device *iommu, do { rq_ddtp =3D FIELD_PREP(RISCV_IOMMU_DDTP_IOMMU_MODE, rq_mode); if (rq_mode > RISCV_IOMMU_DDTP_IOMMU_MODE_BARE) - rq_ddtp |=3D phys_to_ppn(iommu->ddt_phys); + rq_ddtp |=3D riscv_iommu_phys_to_ppn(iommu->ddt_phys); =20 riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_DDTP, rq_ddtp); ddtp =3D riscv_iommu_read_ddtp(iommu); @@ -799,49 +786,9 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iom= mu_device *iommu, return 0; } =20 -/* This struct contains protection domain specific IOMMU driver data. */ -struct riscv_iommu_domain { - struct iommu_domain domain; - struct list_head bonds; - spinlock_t lock; /* protect bonds list updates. */ - int pscid; - int gscid; - bool amo_enabled; - int numa_node; - unsigned int pgd_mode; - unsigned long *pgd_root; -}; - #define iommu_domain_to_riscv(iommu_domain) \ container_of(iommu_domain, struct riscv_iommu_domain, domain) =20 -/* Private IOMMU data for managed devices, dev_iommu_priv_* */ -struct riscv_iommu_info { - struct riscv_iommu_domain *domain; -}; - -/* - * Linkage between an iommu_domain and attached devices. - * - * Protection domain requiring IOATC and DevATC translation cache invalida= tions, - * should be linked to attached devices using a riscv_iommu_bond structure. - * Devices should be linked to the domain before first use and unlinked af= ter - * the translations from the referenced protection domain can no longer be= used. - * Blocking and identity domains are not tracked here, as the IOMMU hardwa= re - * does not cache negative and/or identity (BARE mode) translations, and D= evATC - * is disabled for those protection domains. - * - * The device pointer and IOMMU data remain stable in the bond struct after - * _probe_device() where it's attached to the managed IOMMU, up to the - * completion of the _release_device() call. The release of the bond struc= ture - * is synchronized with the device release. - */ -struct riscv_iommu_bond { - struct list_head list; - struct rcu_head rcu; - struct device *dev; -}; - static int riscv_iommu_bond_link(struct riscv_iommu_domain *domain, struct device *dev) { diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index b1c4664542b4..dd538b19fbb7 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -17,8 +17,35 @@ =20 #include "iommu-bits.h" =20 +/* Timeouts in [us] */ +#define RISCV_IOMMU_QCSR_TIMEOUT 150000 +#define RISCV_IOMMU_QUEUE_TIMEOUT 150000 +#define RISCV_IOMMU_DDTP_TIMEOUT 10000000 +#define RISCV_IOMMU_IOTINVAL_TIMEOUT 90000000 + +/* This struct contains protection domain specific IOMMU driver data. */ +struct riscv_iommu_domain { + struct iommu_domain domain; + struct list_head bonds; + spinlock_t lock; /* protect bonds list updates. */ + int pscid; + int gscid; + int amo_enabled; + int numa_node; + unsigned int pgd_mode; + unsigned long *pgd_root; +}; + +/* Private IOMMU data for managed devices, dev_iommu_priv_* */ +struct riscv_iommu_info { + struct riscv_iommu_domain *domain; +}; + struct riscv_iommu_device; =20 +#define dev_to_iommu(dev) \ + iommu_get_iommu_dev(dev, struct riscv_iommu_device, iommu) + struct riscv_iommu_queue { atomic_t prod; /* unbounded producer allocation index */ atomic_t head; /* unbounded shadow ring buffer consumer index */ @@ -62,9 +89,36 @@ struct riscv_iommu_device { u64 *ddt_root; }; =20 +/* + * Linkage between an iommu_domain and attached devices. + * + * Protection domain requiring IOATC and DevATC translation cache invalida= tions, + * should be linked to attached devices using a riscv_iommu_bond structure. + * Devices should be linked to the domain before first use and unlinked af= ter + * the translations from the referenced protection domain can no longer be= used. + * Blocking and identity domains are not tracked here, as the IOMMU hardwa= re + * does not cache negative and/or identity (BARE mode) translations, and D= evATC + * is disabled for those protection domains. + * + * The device pointer and IOMMU data remain stable in the bond struct after + * _probe_device() where it's attached to the managed IOMMU, up to the + * completion of the _release_device() call. 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada2da2sm1862201f8f.15.2024.11.14.08.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:00 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 08/15] iommu/riscv: Add IRQ domain for interrupt remapping Date: Thu, 14 Nov 2024 17:18:53 +0100 Message-ID: <20241114161845.502027-25-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This is just a skeleton. Until irq_set_vcpu_affinity() is implemented the IRQ domain doesn't serve any purpose. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Makefile | 2 +- drivers/iommu/riscv/iommu-ir.c | 209 +++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 43 ++++++- drivers/iommu/riscv/iommu.h | 21 ++++ 4 files changed, 270 insertions(+), 5 deletions(-) create mode 100644 drivers/iommu/riscv/iommu-ir.c diff --git a/drivers/iommu/riscv/Makefile b/drivers/iommu/riscv/Makefile index f54c9ed17d41..8420dd1776cb 100644 --- a/drivers/iommu/riscv/Makefile +++ b/drivers/iommu/riscv/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_RISCV_IOMMU) +=3D iommu.o iommu-platform.o +obj-$(CONFIG_RISCV_IOMMU) +=3D iommu.o iommu-ir.o iommu-platform.o obj-$(CONFIG_RISCV_IOMMU_PCI) +=3D iommu-pci.o diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c new file mode 100644 index 000000000000..c177e064b205 --- /dev/null +++ b/drivers/iommu/riscv/iommu-ir.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * IOMMU Interrupt Remapping + * + * Copyright =C2=A9 2024 Ventana Micro Systems Inc. + */ +#include +#include + +#include "../iommu-pages.h" +#include "iommu.h" + +static size_t riscv_iommu_ir_get_msipte_idx(struct riscv_iommu_domain *dom= ain, + phys_addr_t msi_pa) +{ + phys_addr_t addr =3D msi_pa >> 12; + size_t idx; + + if (domain->group_index_bits) { + phys_addr_t group_mask =3D BIT(domain->group_index_bits) - 1; + phys_addr_t group_shift =3D domain->group_index_shift - 12; + phys_addr_t group =3D (addr >> group_shift) & group_mask; + phys_addr_t mask =3D domain->msiptp.msi_addr_mask & ~(group_mask << grou= p_shift); + + idx =3D addr & mask; + idx |=3D group << fls64(mask); + } else { + idx =3D addr & domain->msiptp.msi_addr_mask; + } + + return idx; +} + +static struct riscv_iommu_msipte *riscv_iommu_ir_get_msipte(struct riscv_i= ommu_domain *domain, + phys_addr_t msi_pa) +{ + size_t idx; + + if (((msi_pa >> 12) & ~domain->msiptp.msi_addr_mask) !=3D domain->msiptp.= msi_addr_pattern) + return NULL; + + idx =3D riscv_iommu_ir_get_msipte_idx(domain, msi_pa); + return &domain->msi_root[idx]; +} + +static size_t riscv_iommu_ir_nr_msiptes(struct riscv_iommu_domain *domain) +{ + phys_addr_t base =3D domain->msiptp.msi_addr_pattern << 12; + phys_addr_t max_addr =3D base | (domain->msiptp.msi_addr_mask << 12); + size_t max_idx =3D riscv_iommu_ir_get_msipte_idx(domain, max_addr); + + return max_idx + 1; +} + +static struct irq_chip riscv_iommu_irq_chip =3D { + .name =3D "IOMMU-IR", + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, +}; + +static int riscv_iommu_irq_domain_alloc_irqs(struct irq_domain *irqdomain, + unsigned int irq_base, unsigned int nr_irqs, + void *arg) +{ + struct irq_data *data; + int i, ret; + + ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + data =3D irq_domain_get_irq_data(irqdomain, irq_base + i); + data->chip =3D &riscv_iommu_irq_chip; + } + + return 0; +} + +static const struct irq_domain_ops riscv_iommu_irq_domain_ops =3D { + .alloc =3D riscv_iommu_irq_domain_alloc_irqs, + .free =3D irq_domain_free_irqs_parent, +}; + +static const struct msi_parent_ops riscv_iommu_msi_parent_ops =3D { + .prefix =3D "IR-", + .supported_flags =3D MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX, + .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS, + .init_dev_msi_info =3D msi_parent_init_dev_msi_info, +}; + +int riscv_iommu_irq_domain_create(struct riscv_iommu_domain *domain, + struct device *dev) +{ + struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); + struct fwnode_handle *fn; + char *fwname; + + if (domain->irqdomain) { + dev_set_msi_domain(dev, domain->irqdomain); + return 0; + } + + if (!(iommu->caps & RISCV_IOMMU_CAPABILITIES_MSI_FLAT)) { + dev_warn(iommu->dev, "Cannot enable interrupt remapping\n"); + return 0; + } + + spin_lock_init(&domain->msi_lock); + /* + * TODO: The hypervisor should be in control of this size. For now + * we just allocate enough space for 512 VCPUs. + */ + domain->msi_order =3D 1; + domain->msi_root =3D iommu_alloc_pages_node(domain->numa_node, + GFP_KERNEL_ACCOUNT, domain->msi_order); + if (!domain->msi_root) + return -ENOMEM; + + fwname =3D kasprintf(GFP_KERNEL, "IOMMU-IR-%s", dev_name(dev)); + if (!fwname) { + iommu_free_pages(domain->msi_root, domain->msi_order); + return -ENOMEM; + } + + fn =3D irq_domain_alloc_named_fwnode(fwname); + kfree(fwname); + if (!fn) { + dev_err(iommu->dev, "Couldn't allocate fwnode\n"); + iommu_free_pages(domain->msi_root, domain->msi_order); + return -ENOMEM; + } + + domain->irqdomain =3D irq_domain_create_hierarchy(dev_get_msi_domain(dev), + 0, 0, fn, + &riscv_iommu_irq_domain_ops, + domain); + if (!domain->irqdomain) { + dev_err(iommu->dev, "Failed to create IOMMU irq domain\n"); + iommu_free_pages(domain->msi_root, domain->msi_order); + irq_domain_free_fwnode(fn); + return -ENOMEM; + } + + domain->irqdomain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT | + IRQ_DOMAIN_FLAG_ISOLATED_MSI; + domain->irqdomain->msi_parent_ops =3D &riscv_iommu_msi_parent_ops; + irq_domain_update_bus_token(domain->irqdomain, DOMAIN_BUS_MSI_REMAP); + dev_set_msi_domain(dev, domain->irqdomain); + + return 0; +} + +void riscv_iommu_ir_get_resv_regions(struct device *dev, struct list_head = *head) +{ + struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); + struct riscv_iommu_domain *domain =3D info->domain; + struct iommu_resv_region *reg; + phys_addr_t base, addr; + size_t nr_pages, i; + + if (!domain || !domain->msiptp.msiptp) + return; + + base =3D domain->msiptp.msi_addr_pattern << 12; + + if (domain->group_index_bits) { + phys_addr_t group_mask =3D BIT(domain->group_index_bits) - 1; + phys_addr_t group_shift =3D domain->group_index_shift - 12; + phys_addr_t mask =3D domain->msiptp.msi_addr_mask & ~(group_mask << grou= p_shift); + + nr_pages =3D mask + 1; + } else { + nr_pages =3D domain->msiptp.msi_addr_mask + 1; + } + + for (i =3D 0; i < BIT(domain->group_index_bits); i++) { + addr =3D base | (i << domain->group_index_shift); + reg =3D iommu_alloc_resv_region(addr, nr_pages * 4096, + 0, IOMMU_RESV_MSI, GFP_KERNEL); + if (reg) + list_add_tail(®->list, head); + } +} + +void riscv_iommu_irq_domain_remove(struct riscv_iommu_domain *domain) +{ + struct fwnode_handle *fn; + + if (!domain->irqdomain) + return; + + iommu_free_pages(domain->msi_root, domain->msi_order); + + fn =3D domain->irqdomain->fwnode; + irq_domain_remove(domain->irqdomain); + irq_domain_free_fwnode(fn); +} + +void riscv_iommu_irq_domain_unlink(struct riscv_iommu_domain *domain, + struct device *dev) +{ + if (!domain || !domain->irqdomain) + return; + + dev_set_msi_domain(dev, domain->irqdomain->parent); +} diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 6e8ea3d22ff5..c4a47b21c58f 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -943,7 +943,8 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_= domain *domain, rcu_read_unlock(); } =20 -#define RISCV_IOMMU_FSC_BARE 0 +#define RISCV_IOMMU_FSC_BARE 0 +#define RISCV_IOMMU_IOHGATP_BARE 0 =20 /* * Update IODIR for the device. @@ -1245,6 +1246,8 @@ static void riscv_iommu_free_paging_domain(struct iom= mu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 + riscv_iommu_irq_domain_remove(domain); + if (domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); if (domain->gscid > 0) @@ -1276,10 +1279,30 @@ static int riscv_iommu_attach_paging_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); struct riscv_iommu_dc dc =3D {0}; + int ret; =20 if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) return -ENODEV; =20 + if (riscv_iommu_bond_link(domain, dev)) + return -ENOMEM; + + if (iommu_domain->type =3D=3D IOMMU_DOMAIN_UNMANAGED) { + domain->gscid =3D ida_alloc_range(&riscv_iommu_gscids, 1, + RISCV_IOMMU_MAX_GSCID, GFP_KERNEL); + if (domain->gscid < 0) { + riscv_iommu_bond_unlink(domain, dev); + return -ENOMEM; + } + + ret =3D riscv_iommu_irq_domain_create(domain, dev); + if (ret) { + riscv_iommu_bond_unlink(domain, dev); + ida_free(&riscv_iommu_gscids, domain->gscid); + return ret; + } + } + if (domain->gscid) { dc.iohgatp =3D FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, domain->pgd_mode)= | FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | @@ -1292,10 +1315,9 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, dc.ta =3D FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; =20 - if (riscv_iommu_bond_link(domain, dev)) - return -ENOMEM; - riscv_iommu_iodir_update(iommu, dev, &dc); + + riscv_iommu_irq_domain_unlink(info->domain, dev); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; =20 @@ -1389,9 +1411,12 @@ static int riscv_iommu_attach_blocking_domain(struct= iommu_domain *iommu_domain, struct riscv_iommu_dc dc =3D {0}; =20 dc.fsc =3D RISCV_IOMMU_FSC_BARE; + dc.iohgatp =3D RISCV_IOMMU_IOHGATP_BARE; =20 /* Make device context invalid, translation requests will fault w/ #258 */ riscv_iommu_iodir_update(iommu, dev, &dc); + + riscv_iommu_irq_domain_unlink(info->domain, dev); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 @@ -1413,15 +1438,24 @@ static int riscv_iommu_attach_identity_domain(struc= t iommu_domain *iommu_domain, struct riscv_iommu_dc dc =3D {0}; =20 dc.fsc =3D RISCV_IOMMU_FSC_BARE; + dc.iohgatp =3D RISCV_IOMMU_IOHGATP_BARE; dc.ta =3D RISCV_IOMMU_PC_TA_V; =20 riscv_iommu_iodir_update(iommu, dev, &dc); + + riscv_iommu_irq_domain_unlink(info->domain, dev); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D NULL; =20 return 0; } =20 +static void riscv_iommu_get_resv_regions(struct device *dev, + struct list_head *head) +{ + riscv_iommu_ir_get_resv_regions(dev, head); +} + static struct iommu_domain riscv_iommu_identity_domain =3D { .type =3D IOMMU_DOMAIN_IDENTITY, .ops =3D &(const struct iommu_domain_ops) { @@ -1516,6 +1550,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .blocked_domain =3D &riscv_iommu_blocking_domain, .release_domain =3D &riscv_iommu_blocking_domain, .domain_alloc_paging =3D riscv_iommu_alloc_paging_domain, + .get_resv_regions =3D riscv_iommu_get_resv_regions, .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, .release_device =3D riscv_iommu_release_device, diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index dd538b19fbb7..6ce71095781c 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -23,6 +23,12 @@ #define RISCV_IOMMU_DDTP_TIMEOUT 10000000 #define RISCV_IOMMU_IOTINVAL_TIMEOUT 90000000 =20 +struct riscv_iommu_msiptp_state { + u64 msiptp; + u64 msi_addr_mask; + u64 msi_addr_pattern; +}; + /* This struct contains protection domain specific IOMMU driver data. */ struct riscv_iommu_domain { struct iommu_domain domain; @@ -34,6 +40,13 @@ struct riscv_iommu_domain { int numa_node; unsigned int pgd_mode; unsigned long *pgd_root; + u32 group_index_bits; + u32 group_index_shift; + int msi_order; + struct riscv_iommu_msipte *msi_root; + spinlock_t msi_lock; + struct riscv_iommu_msiptp_state msiptp; + struct irq_domain *irqdomain; }; =20 /* Private IOMMU data for managed devices, dev_iommu_priv_* */ @@ -119,6 +132,14 @@ void riscv_iommu_cmd_send(struct riscv_iommu_device *i= ommu, void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, unsigned int timeout_us); =20 +int riscv_iommu_irq_domain_create(struct riscv_iommu_domain *domain, + struct device *dev); +void riscv_iommu_irq_domain_remove(struct riscv_iommu_domain *domain); +void riscv_iommu_irq_domain_unlink(struct riscv_iommu_domain *domain, + struct device *dev); +void riscv_iommu_ir_get_resv_regions(struct device *dev, + struct list_head *head); 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Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- arch/riscv/kvm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index 0c3cbb0915ff..333d95da8ebe 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -29,10 +29,12 @@ config KVM select KVM_GENERIC_DIRTYLOG_READ_PROTECT select KVM_GENERIC_HARDWARE_ENABLING select KVM_MMIO + select KVM_VFIO select KVM_XFER_TO_GUEST_WORK select KVM_GENERIC_MMU_NOTIFIER select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS + select SRCU help Support hosting virtualized guest machines. =20 --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EFC819E98B for ; Thu, 14 Nov 2024 16:19:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601148; cv=none; b=E7a2y4HfsWmNBQhwXR1QMUW/bQ37awqkdQ6Ij7j4QYOb7O47imQsqLXZKrngr6ch6HI2KTUYihz5EyBbFcr6k7+tuK3qBIPRro/wQZdihwLbYBPvZJSZCImieiNN9BhdFLFiDpGjq4otgGIjG4BEYz15ShCnr0MVWbB9koMnODU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601148; c=relaxed/simple; bh=UESyK8Uc8qhnyUFE7sWCeUfzwrVwuw9Qm2LYqZNp+fo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Tk4cCE6KJKBvvCk3jrjNXccEERZF6NAtTMMRWyvUpy7FsciZpHg6YsLvbRmufeb//+5marDcssx8KcyfNPGIfNIJBwaiein21BdlJFmkNH7bRnf9IZqwJbVIMdiN3cOfuLvaCRuEp+2VfVddTf2GV3aW8e5KA2Mz/GU/xorPTV8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=DZIjfuan; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="DZIjfuan" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-382185ed80eso537589f8f.3 for ; Thu, 14 Nov 2024 08:19:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601145; x=1732205945; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JmyAZwFmuLjn3p39hRK9ePQAJ1PSqwbQ6F/1nOHrEzM=; b=DZIjfuancE62FVd5pElzCWaDhWZzUbPRjpUcOwPOqX3NUfD2KqxBkWC0qie5IovXOt +oSnJDvYreXF7KKEaNIKY6qECF6rsme87Xqvq39u1k51nyLwODtS8Zjz1n+w+Oo0vXb4 sWNV5sR7+f/HaCTksTzicGELUlkwxAD0yPsc9NHCpXYV5Jq4FSatznfSLaBhjYp+hwFR T/CJETXvKVjCwFikKNY9OyDOEtW5f9q978eTDWeIMMY4cTfKZ/1v+fdJ/1UAJQgf4HBn A+qRrBVNrYfLUJYRoYITLqP7Ijj5FzTLZvX0xzniGCSckHjSY/TObd/moVJL999r8QpQ a8Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601145; x=1732205945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JmyAZwFmuLjn3p39hRK9ePQAJ1PSqwbQ6F/1nOHrEzM=; b=HB7y92qDqvEDsP21l+rZWiH+J3rQYAJ6ciGKyofuKFCjugHbXauk1QVRZb+Wfx5CMs +ykOLYh2JrnHGeSeCv0QUpl293UUbo/Ohmddf10wr0KzK75li47own5dlOKR89FSKqf0 GZYfNtwi+4cUtdEO++givA54OZ4U5Cm8b/5tDbuXlUXzkjNmBBYZQRx15P6CcKAnmamd xzZ3HIuVaJ4F/La16Ks1GdamW7hp8H1WGgpTXpMkN+jFBgpYgRYITwrkqn+gSRr8XFL2 lyyoswoU5DY/1L08zYbVJOCD7XUTLKcJXaIDYd5pwaiY7+DitJ36j8010SSikKWd09kR QQQg== X-Forwarded-Encrypted: i=1; AJvYcCW0pPPJH3Od1cRtFvuC9fBkHb6KFnfOzUiccwbPwab+OLW0NqFcKBYSTP5+JrFR5NWSEBJ+mXrLYxzKMq0=@vger.kernel.org X-Gm-Message-State: AOJu0YzKatWb9X8zAAMRwqZg5Vj6FXtQLkZ4zsHyaraNLc3hKXhVnmSM OXSOctl5An7dOa97M7LvOi3ih+iGKRybLDOodIrRykM4kSYPGWGMzc1eoO1wsZ4= X-Google-Smtp-Source: AGHT+IEn3qlHsw/D0PT2IEwLbgj1uEV7tnlyKBH8z2H1adqlOAImJaC/GmimW4BKxNwCPjE/Y1igiA== X-Received: by 2002:a05:6000:210e:b0:382:424:94fe with SMTP id ffacd0b85a97d-382042495edmr11613726f8f.36.1731601144686; Thu, 14 Nov 2024 08:19:04 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae161d8sm1901964f8f.78.2024.11.14.08.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:04 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 10/15] RISC-V: KVM: Add irqbypass skeleton Date: Thu, 14 Nov 2024 17:18:55 +0100 Message-ID: <20241114161845.502027-27-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add all the functions needed to wire up irqbypass support. kvm_arch_update_irqfd_routing() is left unimplemented, so return false from kvm_arch_has_irq_bypass(). Signed-off-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 3 ++ arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/aia_imsic.c | 6 ++++ arch/riscv/kvm/vm.c | 60 +++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 35eab6e0f4ae..fef7422939f6 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -114,6 +114,9 @@ struct kvm_arch { =20 /* AIA Guest/VM context */ struct kvm_aia aia; + +#define __KVM_HAVE_ARCH_ASSIGNED_DEVICE + atomic_t assigned_device_count; }; =20 struct kvm_cpu_trap { diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index 333d95da8ebe..9a4feb1e671d 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -21,6 +21,7 @@ config KVM tristate "Kernel-based Virtual Machine (KVM) support (EXPERIMENTAL)" depends on RISCV_SBI && MMU select HAVE_KVM_IRQCHIP + select HAVE_KVM_IRQ_BYPASS select HAVE_KVM_IRQ_ROUTING select HAVE_KVM_MSI select HAVE_KVM_VCPU_ASYNC_IOCTL diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c index a8085cd8215e..64b1f3713dd5 100644 --- a/arch/riscv/kvm/aia_imsic.c +++ b/arch/riscv/kvm/aia_imsic.c @@ -727,6 +727,12 @@ void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu = *vcpu) kvm_riscv_aia_free_hgei(old_vsfile_cpu, old_vsfile_hgei); } =20 +int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, + uint32_t guest_irq, bool set) +{ + return -ENXIO; +} + int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu) { unsigned long flags; diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index 7396b8654f45..9c5837518c1a 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -11,6 +11,9 @@ #include #include #include +#include + +#include =20 const struct _kvm_stats_desc kvm_vm_stats_desc[] =3D { KVM_GENERIC_VM_STATS() @@ -55,6 +58,63 @@ void kvm_arch_destroy_vm(struct kvm *kvm) kvm_riscv_aia_destroy_vm(kvm); } =20 +void kvm_arch_start_assignment(struct kvm *kvm) +{ + atomic_inc(&kvm->arch.assigned_device_count); +} +EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); + +void kvm_arch_end_assignment(struct kvm *kvm) +{ + atomic_dec(&kvm->arch.assigned_device_count); +} +EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); + +bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) +{ + return arch_atomic_read(&kvm->arch.assigned_device_count); +} +EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); + +bool kvm_arch_has_irq_bypass(void) +{ + return false; +} + +int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, + struct irq_bypass_producer *prod) +{ + struct kvm_kernel_irqfd *irqfd =3D + container_of(cons, struct kvm_kernel_irqfd, consumer); + int ret; + + irqfd->producer =3D prod; + kvm_arch_start_assignment(irqfd->kvm); + ret =3D kvm_arch_update_irqfd_routing(irqfd->kvm, prod->irq, irqfd->gsi, = true); + if (ret) + kvm_arch_end_assignment(irqfd->kvm); + + return ret; +} + +void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, + struct irq_bypass_producer *prod) +{ + struct kvm_kernel_irqfd *irqfd =3D + container_of(cons, struct kvm_kernel_irqfd, consumer); + int ret; + + WARN_ON(irqfd->producer !=3D prod); + irqfd->producer =3D NULL; + + ret =3D kvm_arch_update_irqfd_routing(irqfd->kvm, prod->irq, irqfd->gsi, = false); + if (ret) + pr_info("irq bypass consumer (token %p) unregistration fails: %d\n", + irqfd->consumer.token, ret); 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab76dafsm25510275e9.10.2024.11.14.08.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:05 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 11/15] RISC-V: Define irqbypass vcpu_info Date: Thu, 14 Nov 2024 17:18:56 +0100 Message-ID: <20241114161845.502027-28-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The vcpu_info parameter to irq_set_vcpu_affinity() effectively defines an arch specific IOMMU <=3D> hypervisor protocol. Provide a definition for the RISCV IOMMU. Signed-off-by: Andrew Jones --- arch/riscv/include/asm/irq.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 7b038f3b7cb0..8588667cbb5f 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -23,6 +23,15 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn= )(void)); =20 struct fwnode_handle *riscv_get_intc_hwnode(void); =20 +struct riscv_iommu_vcpu_info { + u64 msi_addr_pattern; + u64 msi_addr_mask; + u32 group_index_bits; + u32 group_index_shift; + u64 gpa; + u64 hpa; +}; + #ifdef CONFIG_ACPI =20 enum riscv_irqchip_type { --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E9711AAE23 for ; Thu, 14 Nov 2024 16:19:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601151; cv=none; b=Ye21ttvDIZGm6rV6ZGIuFJEyaU9Yf09XCTNshKNttFJuh0ELiFw/pWQ40A4Hl/Ls5bwX8zdNE4Wa86Jmn6y/NTZGnBdie1yxszJ+J1aMYfFcLGo2o2FwUEzy6WVRimqUaV857qfboL59/yZw/Xr09Pa4PGT58hTtafZ8mIID08M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601151; c=relaxed/simple; bh=TFtkar47iRvavG7LpOfAS59Gk/J7yKNnx1BiLzNhwhw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z1jOi1WMBidhz4W1WTPEDPfj+YhRwn5lyQku6f5vHP3+2clW38vqF46hC2dLi4PVRD+tc791aIj4shGPbEnWGiw/OyXjDJ/ST/vIOICsMQDV2DmbfYGGnRi4gaVBESn42sTE6vFXH0qe9G6ysHMo30BNjafqiQddCaCA+1wjXYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=A4X/nqPm; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="A4X/nqPm" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4315c1c7392so7767745e9.1 for ; Thu, 14 Nov 2024 08:19:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601147; x=1732205947; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+uTuyHOKGUnE3VHWBJ7LYW/wszuVbaF5PQNKaXjnEr8=; b=A4X/nqPms2mqzeEN8bCdMwJ7VrdUuhdRMDBevZ1teUFRb15Zz6gUVroQep235Cgp0l d/c9yEx2lyl2PTPlaDqIo4vl0HrNY1IoPD7iWGYkyYHKBRM8F51lp7/DRWFl0aGl8KmD wK3zoKKsQKplorDb2XRnwv8cpUwyd0i4Y1uu3rsYptB87LulN5mENL3Vlll26vpRSRdG p4Onza33DjBnAs2xsQEKsTj7HLXUwBk9jjUslyaurnj1i3sPb8+yBKq5hH1Fo1EU8/4r 153gXU46g/2Mf3s9QNQV4GXhbO82XpOIrBfIdL8q7lzZFhN7AxzQ5hQD1sErngJ/hITG CZKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601147; x=1732205947; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+uTuyHOKGUnE3VHWBJ7LYW/wszuVbaF5PQNKaXjnEr8=; b=icntyIAV2sut+qF1Iu/6QHLFoKLbb90s8YJd9XSo6qMDi342dkvwUsgORxFKiII2Fu zKNGKONFNlkF/SlorTrJ2yrCBfr10f12m/1fP/uq0znSJN1y6RWDkTkcJ/8jcQbRj4lb PAP8KYHAvoN+pCdX6779CwQWbsBiV2IYpalnRGIf5K5xH1KZb4y8jt3tz1f4Lh/v9pV2 DX49sxkRgIxmX+8h4iTqlR457aWDN6dWNIF1pCqPHTxZPoRx6EGVGkiFhsRggPDxyz3f 78yViFl1Rv9ezO29KMrswAohEjmt3ZmzawNz8SML7jGPApHwkEEPQU0F5NBEgOF+9ek9 Tm3w== X-Forwarded-Encrypted: i=1; AJvYcCW0tGrUy5xGrj1s1zqThTmJSRB6dl1D+BHmAk7/UgIC7kKeZtH4jsJtsHlwqphNk5MCYZMSL5sG74IXlLU=@vger.kernel.org X-Gm-Message-State: AOJu0YwhH1/QI84YiH3S3lOrX18peTuS3NowttArF7drJcqSnB3ni608 kEeJY/vo1NoKRROfO4RYpilgEKCBU9mBcwjDGb6SMwozAw7OcEmEuIDdcIPng1A= X-Google-Smtp-Source: AGHT+IF+dux3jioiQujAjXbkRVUUE8HYuaL/Pb+N/XvgW2ONJ3mvlvI5/3yMLnI7JF+vXby3PurS7Q== X-Received: by 2002:a05:6000:156b:b0:37d:498a:a233 with SMTP id ffacd0b85a97d-382185391demr2252298f8f.43.1731601147550; Thu, 14 Nov 2024 08:19:07 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada4076sm1858965f8f.16.2024.11.14.08.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:07 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 12/15] iommu/riscv: Add guest file irqbypass support Date: Thu, 14 Nov 2024 17:18:57 +0100 Message-ID: <20241114161845.502027-29-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement irq_set_vcpu_affinity() in the RISCV IOMMU driver. irq_set_vcpu_affinity() is the channel from a hypervisor to the IOMMU needed to ensure that assigned devices which direct MSIs to guest IMSIC addresses will have those MSI writes redirected to their corresponding guest interrupt files. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 151 +++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 4 +- drivers/iommu/riscv/iommu.h | 3 + 3 files changed, 156 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index c177e064b205..958270450ec1 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -7,6 +7,8 @@ #include #include =20 +#include + #include "../iommu-pages.h" #include "iommu.h" =20 @@ -52,10 +54,159 @@ static size_t riscv_iommu_ir_nr_msiptes(struct riscv_i= ommu_domain *domain) return max_idx + 1; } =20 +static void riscv_iommu_ir_msitbl_inval(struct riscv_iommu_domain *domain, + struct riscv_iommu_msipte *pte) +{ + struct riscv_iommu_bond *bond; + struct riscv_iommu_device *iommu, *prev; + struct riscv_iommu_command cmd; + u64 addr; + + addr =3D pfn_to_phys(FIELD_GET(RISCV_IOMMU_MSIPTE_PPN, pte->pte)); + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_addr(&cmd, addr); + + /* Like riscv_iommu_iotlb_inval(), synchronize with riscv_iommu_bond_link= () */ + smp_mb(); + + rcu_read_lock(); + + prev =3D NULL; + list_for_each_entry_rcu(bond, &domain->bonds, list) { + iommu =3D dev_to_iommu(bond->dev); + + if (iommu =3D=3D prev) + continue; + + riscv_iommu_cmd_send(iommu, &cmd); + riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT); + prev =3D iommu; + } + + rcu_read_unlock(); +} + +static void riscv_iommu_ir_msitbl_update(struct riscv_iommu_domain *domain, + struct riscv_iommu_msiptp_state *msiptp) +{ + struct riscv_iommu_bond *bond; + struct riscv_iommu_device *iommu, *prev; + struct riscv_iommu_command cmd; + struct iommu_fwspec *fwspec; + struct riscv_iommu_dc *dc; + int i; + + /* Like riscv_iommu_ir_msitbl_inval(), synchronize with riscv_iommu_bond_= link() */ + smp_mb(); + rcu_read_lock(); + + prev =3D NULL; + list_for_each_entry_rcu(bond, &domain->bonds, list) { + iommu =3D dev_to_iommu(bond->dev); + fwspec =3D dev_iommu_fwspec_get(bond->dev); + + for (i =3D 0; i < fwspec->num_ids; i++) { + dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); + WRITE_ONCE(dc->msiptp, msiptp->msiptp); + WRITE_ONCE(dc->msi_addr_mask, msiptp->msi_addr_mask); + WRITE_ONCE(dc->msi_addr_pattern, msiptp->msi_addr_pattern); + } + + dma_wmb(); + + if (iommu =3D=3D prev) + continue; + + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_send(iommu, &cmd); + riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT); + prev =3D iommu; + } + + rcu_read_unlock(); +} + +static int riscv_iommu_ir_msitbl_init(struct riscv_iommu_domain *domain, + struct riscv_iommu_vcpu_info *vcpu_info) +{ + domain->msiptp.msi_addr_pattern =3D vcpu_info->msi_addr_pattern; + domain->msiptp.msi_addr_mask =3D vcpu_info->msi_addr_mask; + domain->group_index_bits =3D vcpu_info->group_index_bits; + domain->group_index_shift =3D vcpu_info->group_index_shift; + + if (riscv_iommu_ir_nr_msiptes(domain) * sizeof(*domain->msi_root) > PAGE_= SIZE * 2) + return -ENOMEM; + + domain->msiptp.msiptp =3D virt_to_pfn(domain->msi_root) | + FIELD_PREP(RISCV_IOMMU_DC_MSIPTP_MODE, + RISCV_IOMMU_DC_MSIPTP_MODE_FLAT); + + riscv_iommu_ir_msitbl_update(domain, &domain->msiptp); + + return 0; +} + +static int riscv_iommu_irq_set_vcpu_affinity(struct irq_data *data, void *= info) +{ + struct riscv_iommu_vcpu_info *vcpu_info =3D info; + struct riscv_iommu_domain *domain =3D data->domain->host_data; + struct riscv_iommu_msipte *pte; + int ret =3D -EINVAL; + u64 pteval; + + if (WARN_ON(domain->domain.type !=3D IOMMU_DOMAIN_UNMANAGED)) + return ret; + + spin_lock(&domain->msi_lock); + + if (!domain->msiptp.msiptp) { + if (WARN_ON(!vcpu_info)) + goto out_unlock; + + ret =3D riscv_iommu_ir_msitbl_init(domain, vcpu_info); + if (ret) + goto out_unlock; + } else if (!vcpu_info) { + /* + * Nothing to do here since we don't track host_irq <=3D> msipte mappings + * nor reference count the ptes. If we did do that tracking then we would + * decrement the reference count of the pte for the host_irq and possibly + * clear its valid bit if it was the last one mapped. + */ + ret =3D 0; + goto out_unlock; + } else if (WARN_ON(vcpu_info->msi_addr_pattern !=3D domain->msiptp.msi_ad= dr_pattern || + vcpu_info->msi_addr_mask !=3D domain->msiptp.msi_addr_mask || + vcpu_info->group_index_bits !=3D domain->group_index_bits || + vcpu_info->group_index_shift !=3D domain->group_index_shift)) { + goto out_unlock; + } + + pte =3D riscv_iommu_ir_get_msipte(domain, vcpu_info->gpa); + if (!pte) + goto out_unlock; + + pteval =3D FIELD_PREP(RISCV_IOMMU_MSIPTE_M, 3) | + riscv_iommu_phys_to_ppn(vcpu_info->hpa) | + FIELD_PREP(RISCV_IOMMU_MSIPTE_V, 1); + + if (pte->pte !=3D pteval) { + pte->pte =3D pteval; + riscv_iommu_ir_msitbl_inval(domain, pte); + } + + ret =3D 0; + +out_unlock: + spin_unlock(&domain->msi_lock); + return ret; +} + static struct irq_chip riscv_iommu_irq_chip =3D { .name =3D "IOMMU-IR", .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_vcpu_affinity =3D riscv_iommu_irq_set_vcpu_affinity, }; =20 static int riscv_iommu_irq_domain_alloc_irqs(struct irq_domain *irqdomain, diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index c4a47b21c58f..46ac228ba7ac 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -544,8 +544,8 @@ static irqreturn_t riscv_iommu_fltq_process(int irq, vo= id *data) } =20 /* Lookup and initialize device context info structure. */ -static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device= *iommu, - unsigned int devid) +struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iommu, + unsigned int devid) { const bool base_format =3D !(iommu->caps & RISCV_IOMMU_CAPABILITIES_MSI_F= LAT); unsigned int depth; diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 6ce71095781c..2ca76edf48f5 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -127,6 +127,9 @@ struct riscv_iommu_bond { int riscv_iommu_init(struct riscv_iommu_device *iommu); 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28b76fsm29185835e9.28.2024.11.14.08.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:08 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 13/15] RISC-V: KVM: Add guest file irqbypass support Date: Thu, 14 Nov 2024 17:18:58 +0100 Message-ID: <20241114161845.502027-30-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement kvm_arch_update_irqfd_routing() which makes irq_set_vcpu_affinity() calls whenever the assigned device updates its target addresses and whenever the hypervisor has migrated a VCPU to another CPU (which requires changing the guest interrupt file). Signed-off-by: Andrew Jones --- arch/riscv/kvm/aia_imsic.c | 132 ++++++++++++++++++++++++++++++++++++- arch/riscv/kvm/vm.c | 2 +- 2 files changed, 130 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c index 64b1f3713dd5..6a7c23e25f79 100644 --- a/arch/riscv/kvm/aia_imsic.c +++ b/arch/riscv/kvm/aia_imsic.c @@ -11,11 +11,13 @@ #include #include #include +#include #include #include #include #include #include +#include =20 #define IMSIC_MAX_EIX (IMSIC_MAX_ID / BITS_PER_TYPE(u64)) =20 @@ -676,6 +678,14 @@ static void imsic_swfile_update(struct kvm_vcpu *vcpu, imsic_swfile_extirq_update(vcpu); } =20 +static u64 kvm_riscv_aia_msi_addr_mask(struct kvm_aia *aia) +{ + u64 group_mask =3D BIT(aia->nr_group_bits) - 1; + + return (group_mask << (aia->nr_group_shift - IMSIC_MMIO_PAGE_SHIFT)) | + (BIT(aia->nr_hart_bits + aia->nr_guest_bits) - 1); +} + void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu) { unsigned long flags; @@ -730,7 +740,120 @@ void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu= *vcpu) int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, bool set) { - return -ENXIO; + struct irq_data *irqdata =3D irq_get_irq_data(host_irq); + struct kvm_irq_routing_table *irq_rt; + struct kvm_vcpu *vcpu; + unsigned long tmp, flags; + int idx, ret =3D -ENXIO; + + if (!set) + return irq_set_vcpu_affinity(host_irq, NULL); + + idx =3D srcu_read_lock(&kvm->irq_srcu); + irq_rt =3D srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); + if (guest_irq >=3D irq_rt->nr_rt_entries || + hlist_empty(&irq_rt->map[guest_irq])) { + pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", + guest_irq, irq_rt->nr_rt_entries); + goto out; + } + + kvm_for_each_vcpu(tmp, vcpu, kvm) { + struct imsic *imsic =3D vcpu->arch.aia_context.imsic_state; + gpa_t ippn =3D vcpu->arch.aia_context.imsic_addr >> IMSIC_MMIO_PAGE_SHIF= T; + struct kvm_aia *aia =3D &kvm->arch.aia; + struct kvm_kernel_irq_routing_entry *e; + + hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { + struct msi_msg msg[2] =3D { + { + .address_hi =3D e->msi.address_hi, + .address_lo =3D e->msi.address_lo, + .data =3D e->msi.data, + }, + }; + struct riscv_iommu_vcpu_info vcpu_info =3D { + .msi_addr_mask =3D kvm_riscv_aia_msi_addr_mask(aia), + .group_index_bits =3D aia->nr_group_bits, + .group_index_shift =3D aia->nr_group_shift, + }; + gpa_t target, tppn; + + if (e->type !=3D KVM_IRQ_ROUTING_MSI) + continue; + + target =3D ((gpa_t)e->msi.address_hi << 32) | e->msi.address_lo; + tppn =3D target >> IMSIC_MMIO_PAGE_SHIFT; + + WARN_ON(target & (IMSIC_MMIO_PAGE_SZ - 1)); + + if (ippn !=3D tppn) + continue; + + vcpu_info.msi_addr_pattern =3D tppn & ~vcpu_info.msi_addr_mask; + vcpu_info.gpa =3D target; + + read_lock_irqsave(&imsic->vsfile_lock, flags); + + if (WARN_ON_ONCE(imsic->vsfile_cpu < 0)) { + read_unlock_irqrestore(&imsic->vsfile_lock, flags); + goto out; + } + + vcpu_info.hpa =3D imsic->vsfile_pa; + + ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); + if (ret) { + read_unlock_irqrestore(&imsic->vsfile_lock, flags); + goto out; + } + + irq_data_get_irq_chip(irqdata)->irq_write_msi_msg(irqdata, msg); + + read_unlock_irqrestore(&imsic->vsfile_lock, flags); + } + } + + ret =3D 0; +out: + srcu_read_unlock(&kvm->irq_srcu, idx); + return ret; +} + +static int kvm_riscv_vcpu_irq_update(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm =3D vcpu->kvm; + struct imsic *imsic =3D vcpu->arch.aia_context.imsic_state; + struct kvm_aia *aia =3D &kvm->arch.aia; + u64 mask =3D kvm_riscv_aia_msi_addr_mask(aia); + u64 target =3D vcpu->arch.aia_context.imsic_addr; + struct riscv_iommu_vcpu_info vcpu_info =3D { + .msi_addr_pattern =3D (target >> IMSIC_MMIO_PAGE_SHIFT) & ~mask, + .msi_addr_mask =3D mask, + .group_index_bits =3D aia->nr_group_bits, + .group_index_shift =3D aia->nr_group_shift, + .gpa =3D target, + .hpa =3D imsic->vsfile_pa, + }; + struct kvm_kernel_irqfd *irqfd; + int host_irq, ret; + + spin_lock_irq(&kvm->irqfds.lock); + + list_for_each_entry(irqfd, &kvm->irqfds.items, list) { + if (!irqfd->producer) + continue; + host_irq =3D irqfd->producer->irq; + ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); + if (ret) { + spin_unlock_irq(&kvm->irqfds.lock); + return ret; + } + } + + spin_unlock_irq(&kvm->irqfds.lock); + + return 0; } =20 int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu) @@ -797,14 +920,17 @@ int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *= vcpu) if (ret) goto fail_free_vsfile_hgei; =20 - /* TODO: Update the IOMMU mapping ??? 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821adbe779sm1834550f8f.60.2024.11.14.08.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:09 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 14/15] vfio: enable IOMMU_TYPE1 for RISC-V Date: Thu, 14 Nov 2024 17:18:59 +0100 Message-ID: <20241114161845.502027-31-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tomasz Jeznach Enable VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index ceae52fd7586..ad62205b4e45 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -39,7 +39,7 @@ config VFIO_GROUP =20 config VFIO_CONTAINER bool "Support for the VFIO container /dev/vfio/vfio" - select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV) depends on VFIO_GROUP default y help --=20 2.47.0 From nobody Sat Nov 23 02:02:04 2024 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3B601ADFE0 for ; Thu, 14 Nov 2024 16:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601155; cv=none; b=JB0/j0+JIzrRAHkNCtkNbHDnonQbsHrWaQ6YbyLTy1m89m82M8bG4athDravjfRdv0OmbrvDHi+L9bxF0MMf7KDlnyDZtIIkfro2t0VfoICtP768Z+N1Z3zQ8ySRG9ArULcx6fxOZVCXFhwvIY6ByfRONd9w1SoF/1ELMxx6tpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731601155; c=relaxed/simple; bh=nPnauxX7TiBvZUSelznoj4ZrHIzLIbMVHtA1EyH4RVI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bJm/ImB1izp2K2Bc5qBZVWAfB/pnBkNwYSG82aDSZUV81v1FBBFOQOTP6dHIs2nBTMXcAsfa46PVZVDIRrIQ4B0Dfz8+AnhsHsEY3eu1jhRwJslXlfXuSPKUTFVNg1AqFd1lOaV6tIk4QlAKlP8lsVUDFYqUxZzlQ8EtxoTD9gs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=i/dm21c6; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="i/dm21c6" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4314b316495so7194845e9.2 for ; Thu, 14 Nov 2024 08:19:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601152; x=1732205952; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bLyjPEUjYy3GGHllbim/73zpVvmemz3R8H3vfZF+LqU=; b=i/dm21c6mHbPUh0kR2V+NaD9L4LdKkTk3mInd+TPeSVk7MDkqijGAwQrIB9Z+T1zJc xmfoA+ATnVC7IRs/FxWba3DRi/SGb+YLPbfDLxhAE3ccENfNOQA6fpzeA3CQlyJ0aOs5 wboMSAFzZrIVvtHiYsvDar7j2RDk3qRxZpbmhPlnAeR34oS3U4jkMHMyJ1v/vKx7+j4P TLnqGL7KqozomSlKbuk8pOW6oKctTDeAza+O5PP0S3VJGnXumADG8H0T2sL/WT+XER1s Nff69oehon4dCrZ+XEi+GZ64a4nRuKatR39W/gcl3wV4YEiMqM3CdzpuKxGxpa9UT0Dg RbVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601152; x=1732205952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bLyjPEUjYy3GGHllbim/73zpVvmemz3R8H3vfZF+LqU=; b=ZppChIfj69rgJ5KqyPZCXBtqCOQrdiDwzOcLFsnYMRkzHrkcx2aBRnfugQcY8AxWH0 u9cFtURztCDsjfT4nylUIsN5t2XLjicV3sBSBsGzmqDeGoM34rK3XeRCmKS8hX/e7mJX UgvVf9IUsirUEr+Is+NYTvwUcw61lZGu0omASm/ZEkSqyjSuTZOUr4uzt/SLivEMHxPi tbev0fIFIVLyLVTCi/pJIK/ca32KYSDzjPVM8uJTUzNXIFtRT1GTONh7KqbW30U55sJ+ 03Fi/wqNCpU7x8Xr5zPOCDkd0mJHbPDTrF8idKlhXS2KFOAF43jo+qsHwbAVmfd/WTNe /gIQ== X-Forwarded-Encrypted: i=1; AJvYcCU1xZl50IYRol3A65N2qILKDNLPFVNedkEHPzj07Aj7C7PkPCBEW6jBCrrDXuDBEhe4Oj5f6XwyS8aExq8=@vger.kernel.org X-Gm-Message-State: AOJu0YwBYXvwpcbIA1zfLTURu/L1u2AptESKOvaLY8HWa5aZ5DR3GY2s pcrDHY3cEAya0PiEpTQdn3wRuWz9ux0Fz0jOubtwG9PcB6IMgcvnfGoQVRSNjlk= X-Google-Smtp-Source: AGHT+IHKQidNVhwcm1UkvoSFM0iFKvguMA4Koj+yRoQBZD+zU91sO767fbB1E85gsh6vbgzv0SLQ3g== X-Received: by 2002:a05:600c:c08:b0:42c:bd27:4c12 with SMTP id 5b1f17b1804b1-432d4aae6b7mr76573235e9.10.1731601152220; Thu, 14 Nov 2024 08:19:12 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da298a41sm29066525e9.38.2024.11.14.08.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:11 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 15/15] RISC-V: defconfig: Add VFIO modules Date: Thu, 14 Nov 2024 17:19:00 +0100 Message-ID: <20241114161845.502027-32-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the VFIO modules to the defconfig to complement KVM now that there is IOMMU support. Signed-off-by: Andrew Jones --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index b4a37345703e..10fc9d84a28c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -242,6 +242,8 @@ CONFIG_RTC_DRV_SUN6I=3Dy CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy +CONFIG_VFIO=3Dm +CONFIG_VFIO_PCI=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.47.0