From nobody Sat Nov 23 02:09:26 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 049E8166F3D; Thu, 14 Nov 2024 16:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600618; cv=none; b=ShHn2hxoh8WD4NxFbdy09ppxJAZaN4MjGCTxyGpX5auq+u+9lDUT5pUER2ZoX4WarlfUKQJOihWuQJR5U4rjZXxLeqU4PVRd2m7SAtJnobjCMqo/XlUAOOqVKaxTL1w5ehr4HSsuvFBdQ0EYrnzXFfeQ4heIkqqXxE55wEbwR0w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600618; c=relaxed/simple; bh=tTVfRhy+0cF1QAQhvZ8/YDlf/6fJ73Gxjjobgn53D20=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BbWFFvXS6N+G/mXAwNFQuadsANbsj7Ux/BzyFMOsDrA3uGTC3v81k5/4IEXLtXvzBdZy3+NILWC85P2Ti8Kvu4R8Ef99EXB3au6uprH5HvOp7OC2edI99D+s1vaL6LOlBybC5pHPVfBcLx9+jL1HcLbtqmkSiwrtYJc1MwJObsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Z8piJrYQ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Z8piJrYQ" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AEEkTW0026116; Thu, 14 Nov 2024 16:09:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= V4gvQXnQ/TnC4ga3wtGtB/oOq2kR1vd+H2yGj2bJNZk=; b=Z8piJrYQqjovqqnr +g7P+rFYAgxtKXyj3hjlPCWZTpzqHsh/QILLMrmMWYs26CDji4HJXo5lqHYb1BZo NhWNS3a0HqNOKnzjh9BwXhHrlf+9RcUksxeCQNnjEcshFuXuAjymLsc69wGCy6pB mo2B62wit+5w5BSRmRZLbv+9rnxdrQZq+Er3iLkbnXQ3vbZ5+k/qkX0gjk8Oy5PL 9S84cXvYii0/XnOiplewGdNfr4MNTW9zt7lgvwd/980sP9TV7pRk9lQRrgdcI8yu qfXDEHd4YriPZQRFt1kZvhnJgWRyEhP5TomhOzoP1y3wI/SJE/MpmMCBfKToVgJz +j2tFQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42va07g3jx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:09:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AEG9mNS027583 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:09:48 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 14 Nov 2024 08:09:44 -0800 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , Subject: [PATCH RESEND v17 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation Date: Thu, 14 Nov 2024 21:37:17 +0530 Message-ID: <20241114160721.1527934-2-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> References: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yN6n7R4DqVW3mzj55BwPy_hZcOdiQiZ9 X-Proofpoint-ORIG-GUID: yN6n7R4DqVW3mzj55BwPy_hZcOdiQiZ9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140126 Content-Type: text/plain; charset="utf-8" Default MMU-500 reset operation disables context caching in prefetch buffer. It is however expected for context banks using the ACTLR register to retain their prefetch value during reset and runtime suspend. Add config 'ARM_SMMU_MMU_500_CPRE_ERRATA' to gate this errata workaround in default MMU-500 reset operation which defaults to 'Y' and provide option to disable workaround for context caching in prefetch buffer as and when needed. Suggested-by: Will Deacon Signed-off-by: Bibek Kumar Patro --- Documentation/arch/arm64/silicon-errata.rst | 3 ++- drivers/iommu/Kconfig | 12 ++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +++-- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 65bfab1b1861..92207d55fd1c 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -198,7 +198,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_31943= 86 | +----------------+-----------------+-----------------+--------------------= ---------+ -| ARM | MMU-500 | #841119,826419 | N/A = | +| ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CP= RE_ERRATA| +| | | #562869,1047329 | = | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | MMU-600 | #1076982,1209401| N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index b3aa1f5d5321..7eb67608a519 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -366,6 +366,18 @@ config ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT 'arm-smmu.disable_bypass' will continue to override this config. +config ARM_SMMU_MMU_500_CPRE_ERRATA + bool "Enable errata workaround for CPRE in SMMU reset path" + depends on ARM_SMMU + default y + help + Say Y here (by default) to apply workaround to disable + MMU-500's next-page prefetcher for sake of 4 known errata. + + Say N here only when it is sure that any errata related to + prefetch enablement are not applicable on the platform. + Refer silicon-errata.rst for info on errata IDs. + config ARM_SMMU_QCOM def_tristate y depends on ARM_SMMU && ARCH_QCOM diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-impl.c index 99030e6b16e7..db9b9a8e139c 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c @@ -110,7 +110,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(st= ruct arm_smmu_device *smm int arm_mmu500_reset(struct arm_smmu_device *smmu) { u32 reg, major; - int i; /* * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before * writes to the context bank ACTLRs will stick. And we just hope that @@ -128,11 +127,12 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu) reg |=3D ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN; arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg); +#ifdef CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA /* * Disable MMU-500's not-particularly-beneficial next-page * prefetcher for the sake of at least 5 known errata. */ - for (i =3D 0; i < smmu->num_context_banks; ++i) { + for (int i =3D 0; i < smmu->num_context_banks; ++i) { reg =3D arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); reg &=3D ~ARM_MMU500_ACTLR_CPRE; arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); @@ -140,6 +140,7 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu) if (reg & ARM_MMU500_ACTLR_CPRE) dev_warn_once(smmu->dev, "Failed to disable prefetcher for errata worka= rounds, check SACR.CACHE_LOCK\n"); } +#endif return 0; } -- 2.34.1 From nobody Sat Nov 23 02:09:26 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA85617ADE1; Thu, 14 Nov 2024 16:10:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600611; cv=none; b=afvx4lEX4hu5XK/POaq3m0yVL6Fc162EmpeuC7hNupM2w89FdkM2rbXa7JdQ+rjI55agXr73NLFMA0fQ4xZxaqD7XEhVvAol31wmpLAuSehWd5za8kJn1I/CXtuVQHn0zBm1NyopmTP/7pFgFtcUStat4MJzf7MV/SjNhuRj15g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600611; c=relaxed/simple; bh=bYBlmRZnSP1+6bbO6DyCu9HwcvNxZ82NbuYVPGaawCk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rb+UWcKMYBGDKHb/OGrk+AcCYOhFiBsygM7OdsTvETukVbdKy1ACmfDwjjNF33sssAsifjUjfZxj2RY/YADg6kl4XO5n8TIrIMPsXH7WfvDVgEWkz1urmCNIM3D93hwaV+/QouuMPmThudJ/VlqtjBqSaHvU3cJW1FkW7DVa4Jc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=NK4Gc9Q+; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="NK4Gc9Q+" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AEEP0xN021058; Thu, 14 Nov 2024 16:09:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= U0jvV2u/4nB0nNLZJ5fmuVk3Sm8TxGDd+eRh6fPI5u8=; b=NK4Gc9Q+t8wcOSbv gYwLLsduJi1GQJ5M1q1SyaKzQZoy9ys9azizNcawxcyjm293O3vkWPl+jvvS1TBr VjmjLrTP3qOcIprFXN/Y5fRIFhF4U3ImQXke6Cu7cetHHWa3posMy2eNOxpc2ZGf LrFF5/+5zzUk5toISEUkHYMayUUZ3+EexzfABKX8Q5p7xKonffdsISFq5leQoMz4 UTtmolgrMv/34/49ibYX3TE92thwJvU39rR4tG5vCEB/WeygaxCtilCBJbuIRP9u 13v5Lyl3IxRxvDN9YsWd06ZKWDhxf6iva+9Jyvy3wVAK+bZWWrVWITNrAlRVWpYm n/sdbg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42v4kr1019-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:09:53 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AEG9rsJ018594 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:09:53 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 14 Nov 2024 08:09:48 -0800 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , Subject: [PATCH RESEND v17 2/5] iommu/arm-smmu: refactor qcom_smmu structure to include single pointer Date: Thu, 14 Nov 2024 21:37:18 +0530 Message-ID: <20241114160721.1527934-3-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> References: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: B-dkL8kiqbglIEvFEg0T92DuvfAx24gi X-Proofpoint-GUID: B-dkL8kiqbglIEvFEg0T92DuvfAx24gi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140126 Content-Type: text/plain; charset="utf-8" qcom_smmu_match_data is static and constant so refactor qcom_smmu to store single pointer to qcom_smmu_match_data instead of replicating multiple child members of the same and handle the further dereferences in the places that want them. Suggested-by: Robin Murphy Reviewed-by: Dmitry Baryshkov Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iom= mu/arm/arm-smmu/arm-smmu-qcom-debug.c index 548783f3f8e8..d03b2239baad 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c @@ -73,7 +73,7 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smm= u) if (__ratelimit(&rs)) { dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n"); - cfg =3D qsmmu->cfg; + cfg =3D qsmmu->data->cfg; if (!cfg) return; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 6372f3e25c4b..d26f5aea248e 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -507,7 +507,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct = arm_smmu_device *smmu, return ERR_PTR(-ENOMEM); qsmmu->smmu.impl =3D impl; - qsmmu->cfg =3D data->cfg; + qsmmu->data =3D data; return &qsmmu->smmu; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.h index 3c134d1a6277..b55cd3e3ae48 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -8,7 +8,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; - const struct qcom_smmu_config *cfg; + const struct qcom_smmu_match_data *data; bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; -- 2.34.1 From nobody Sat Nov 23 02:09:26 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9EE184528; Thu, 14 Nov 2024 16:10:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600614; cv=none; b=j8RgaJehhbBUSBucKW3/HY+XKbWn6k9Gu50xj0lIu8ii+YPzV2DurMmthQMEsIdwGj2bpDOfrrL3ZOonV+jUH6aVPpzyDfeTVviwKYIwY/ezRcyDrCDwUBDR/CCe9k8y6D6H3HVENy/DfTuGXT+Enu2827NgY2CWWJr6/cydx4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600614; c=relaxed/simple; bh=CXtZ+PaPn/nkVw1bXLGecyOZdbbB46QA4QY3jiBrGw4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PSTt5oKFns9ZHtLKsZDzXg6w+EJeN0hiNxOxiVxGw3BdVnRwUe8iaNCsVCmJCoowt78llgnSgtSeORVNiO7XJPagco0okQiLukIXAEpH6YIj3rn8cWcw9a642szA8WXPdxJdrae7A8EovRxTixWuQJeaGtd5GUB2hgcUp6NuciE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=cNj6+QpA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cNj6+QpA" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AEAvhWf007265; Thu, 14 Nov 2024 16:09:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= PPIsNByjG9dF2PwiVs+mc7dHm6mYJURBXoCSGmZI260=; b=cNj6+QpAsABAGZCB ghy7dOX3ZlmKvX7/PmHnMki1OHQ887gf4h0G+2G0RP1rKXimnjTGy81JfdDfwZBj x5pZCmqwiUEe6NrtfIHliKlCsu9JfKTZ0JYEP8UXuLjhM2ILt2PNiQ/s+B5+kdnC 1ndvXF/5sRhUQqWAc8pLpDgKdCesyDkjYRzFSPbSFIAfnNtI+qJDzgzxuZQi0Y0h g4H/xbQflnvoxKaA3mA2AP0/uRlRgaQJ01A3Nv/eC0tAs5lxNR3Ilpt89n3AADtX Bw/aWAQxdbfBYsNqNbqiG9Psw3DtzoTNjU2csBGlEUOSxUTO8MHyvoElhyd7CNjj fiUCDQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42w7ekk87e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:09:58 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AEG9wFi018627 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:09:58 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 14 Nov 2024 08:09:53 -0800 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , Subject: [PATCH RESEND v17 3/5] iommu/arm-smmu: add support for PRR bit setup Date: Thu, 14 Nov 2024 21:37:19 +0530 Message-ID: <20241114160721.1527934-4-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> References: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 1OvdT-52SioxjhO66dWHHFtDpkHQ57b6 X-Proofpoint-GUID: 1OvdT-52SioxjhO66dWHHFtDpkHQ57b6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140126 Content-Type: text/plain; charset="utf-8" Add an adreno-smmu-priv interface for drm/msm to call into arm-smmu-qcom and initiate the PRR bit setup or reset sequence as per request. This will be used by GPU to setup the PRR bit and related configuration registers through adreno-smmu private interface instead of directly poking the smmu hardware. Suggested-by: Rob Clark Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ include/linux/adreno-smmu-priv.h | 14 ++++++++ 3 files changed, 53 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index d26f5aea248e..0e4f3fbda961 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -16,6 +16,8 @@ #define QCOM_DUMMY_VAL -1 +#define GFX_ACTLR_PRR (1 << 5) + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -99,6 +101,32 @@ static void qcom_adreno_smmu_resume_translation(const v= oid *cookie, bool termina arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); } +static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set) +{ + struct arm_smmu_domain *smmu_domain =3D (void *)cookie; + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct arm_smmu_cfg *cfg =3D &smmu_domain->cfg; + u32 reg =3D 0; + + reg =3D arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR); + reg &=3D ~GFX_ACTLR_PRR; + if (set) + reg |=3D FIELD_PREP(GFX_ACTLR_PRR, 1); + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg); +} + +static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t = page_addr) +{ + struct arm_smmu_domain *smmu_domain =3D (void *)cookie; + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + + writel_relaxed(lower_32_bits(page_addr), + smmu->base + ARM_SMMU_GFX_PRR_CFG_LADDR); + + writel_relaxed(upper_32_bits(page_addr), + smmu->base + ARM_SMMU_GFX_PRR_CFG_UADDR); +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -210,6 +238,7 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_de= vice *smmu) static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_doma= in, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + const struct device_node *np =3D smmu_domain->smmu->dev->of_node; struct adreno_smmu_priv *priv; smmu_domain->cfg.flush_walk_prefer_tlbiasid =3D true; @@ -239,6 +268,14 @@ static int qcom_adreno_smmu_init_context(struct arm_sm= mu_domain *smmu_domain, priv->get_fault_info =3D qcom_adreno_smmu_get_fault_info; priv->set_stall =3D qcom_adreno_smmu_set_stall; priv->resume_translation =3D qcom_adreno_smmu_resume_translation; + priv->set_prr_bit =3D NULL; + priv->set_prr_addr =3D NULL; + + if (of_device_is_compatible(np, "qcom,smmu-500") && + of_device_is_compatible(np, "qcom,adreno-smmu")) { + priv->set_prr_bit =3D qcom_adreno_smmu_set_prr_bit; + priv->set_prr_addr =3D qcom_adreno_smmu_set_prr_addr; + } return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-= smmu/arm-smmu.h index e2aeb511ae90..2dbf3243b5ad 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -154,6 +154,8 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_SCTLR_M BIT(0) #define ARM_SMMU_CB_ACTLR 0x4 +#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008 +#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_RESUME_TERMINATE BIT(0) diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-p= riv.h index c637e0997f6d..614665153b3e 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -50,6 +50,18 @@ struct adreno_smmu_fault_info { * the GPU driver must call resume_translation() * @resume_translation: Resume translation after a fault * + * *CAUTION* : PRR callbacks (set_prr_bit/set_prr_addr) are NULL terminate= d for + * targets without PRR support. Exercise caution and verify ta= rget + * capabilities before invoking these callbacks to prevent pot= ential + * runtime errors or unexpected behavior. + * + * @set_prr_bit: Extendible interface to be used by GPU to modify the + * ACTLR register bits, currently used to configure + * Partially-Resident-Region (PRR) bit for feature's + * setup and reset sequence as requested. + * @set_prr_addr: Configure the PRR_CFG_*ADDR register with the + * physical address of PRR page passed from + * GPU driver. * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -67,6 +79,8 @@ struct adreno_smmu_priv { void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_in= fo *info); void (*set_stall)(const void *cookie, bool enabled); void (*resume_translation)(const void *cookie, bool terminate); + void (*set_prr_bit)(const void *cookie, bool set); + void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr); }; #endif /* __ADRENO_SMMU_PRIV_H */ -- 2.34.1 From nobody Sat Nov 23 02:09:26 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB24518C039; Thu, 14 Nov 2024 16:10:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600623; cv=none; b=HP9b85Zm/x/fm2AY2rVIk8ArCcI9EZKRAHYCwDACxmpf7ncbp3Cpj5/AQ7eRSfYZvjrcRX+rznNcw4LHGjcHNoy+5P7XXw2Kzqu1mdu/wD4jHLIXYyPjly3rt/EpOijNCt/N2KduSe7xvJRW67g1J4Vj7B9FYdrVtS8oKgP09+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600623; c=relaxed/simple; bh=K1TKFWrXrTxyJs5X/6wELhG8DlYidaX42aF2JFk2gbo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jcVlTwFBPa7uP4Bxr3oFV4zuk8qMqcKq87INEsAikt2Tz2/9mVpg2Vaxk569bAWEqWuR9n2+NRCybFm/DoGdr6LowX652i8qm1tOmbXCfiVcqfOGqDhW1tcyNHtLCVhu3mfU4C7WIghiYHdxiI+HQB0LbgxlOfNV/MXWQst/rlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=a1eMepaf; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="a1eMepaf" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AEE26i0026909; Thu, 14 Nov 2024 16:10:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= wCVnf/TyUHhxgeZ7ScMhiy4Pc0EXuCRI9iHUN3SXrRg=; b=a1eMepafJBaa0ZvX KdUrkwmgoN+USscv/0NYSxs7iJQOBnQLK5W+vWVFwY/Leyg/W43w0xmDCNtq5eup N2ZAn7H7Q888AvBp23OdfDdBc8PcemSRJK/t8BI7y0EJsnTrKLGnxmU/yFVEHUhc 0QWj620yx87YM6fMVkcgS14Qj0rqtgrKAhKndFw1BUMjy97vKLrM49w0+QoHeo6V M+Z9ZCib4oTmXNsg2YCtbS4FldnOkBo/9mf6N4oWIKcw34dTdsQSPPFXA59kYMjI myTRPrMjAlHBz7dFmrfAb3twUbLxaWHt6MetQFj6plG7UeRqW9ykARrDG+aUKuRb knIo1w== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42vt735fcy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:10:03 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AEGA2dG027952 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:10:02 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 14 Nov 2024 08:09:58 -0800 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , Subject: [PATCH RESEND v17 4/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings Date: Thu, 14 Nov 2024 21:37:20 +0530 Message-ID: <20241114160721.1527934-5-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> References: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: XaVnIpUvDliN6DdIBE6WG6FIdC66Lo28 X-Proofpoint-GUID: XaVnIpUvDliN6DdIBE6WG6FIdC66Lo28 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 phishscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140125 Content-Type: text/plain; charset="utf-8" Currently in Qualcomm SoCs the default prefetch is set to 1 which allows the TLB to fetch just the next page table. MMU-500 features ACTLR register which is implementation defined and is used for Qualcomm SoCs to have a custom prefetch setting enabling TLB to prefetch the next set of page tables accordingly allowing for faster translations. ACTLR value is unique for each SMR (Stream matching register) and stored in a pre-populated table. This value is set to the register during context bank initialisation. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 0e4f3fbda961..b595fee23836 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -235,14 +235,37 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_= device *smmu) return true; } +static void qcom_smmu_set_actlr_dev(struct device *dev, struct arm_smmu_de= vice *smmu, int cbndx, + const struct of_device_id *client_match) +{ + const struct of_device_id *match =3D + of_match_device(client_match, dev); + + if (!match) { + dev_dbg(dev, "no ACTLR settings present\n"); + return; + } + + arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, (unsigned long)match->d= ata); +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_doma= in, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { const struct device_node *np =3D smmu_domain->smmu->dev->of_node; + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct qcom_smmu *qsmmu =3D to_qcom_smmu(smmu); + const struct of_device_id *client_match; + int cbndx =3D smmu_domain->cfg.cbndx; struct adreno_smmu_priv *priv; smmu_domain->cfg.flush_walk_prefer_tlbiasid =3D true; + client_match =3D qsmmu->data->client_match; + + if (client_match) + qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match); + /* Only enable split pagetables for the GPU device (SID 0) */ if (!qcom_adreno_smmu_is_gpu_device(dev)) return 0; @@ -306,8 +329,18 @@ static const struct of_device_id qcom_smmu_client_of_m= atch[] __maybe_unused =3D { static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct qcom_smmu *qsmmu =3D to_qcom_smmu(smmu); + const struct of_device_id *client_match; + int cbndx =3D smmu_domain->cfg.cbndx; + smmu_domain->cfg.flush_walk_prefer_tlbiasid =3D true; + client_match =3D qsmmu->data->client_match; + + if (client_match) + qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match); + return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.h index b55cd3e3ae48..8addd453f5f1 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -28,6 +28,7 @@ struct qcom_smmu_match_data { const struct qcom_smmu_config *cfg; const struct arm_smmu_impl *impl; const struct arm_smmu_impl *adreno_impl; + const struct of_device_id * const client_match; }; irqreturn_t qcom_smmu_context_fault(int irq, void *dev); -- 2.34.1 From nobody Sat Nov 23 02:09:26 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1CB518C326; Thu, 14 Nov 2024 16:10:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600623; cv=none; b=kRiRJ+MxoRA3s2ezAfT5iAGPuDu7Ua84yEr9sCctvpxkdIxSaVD/cvtdMACNs6XYL4O+KrAwq1WP7QVek5+hS/FS00j0WVV8tkVw/EjuJLK3FcIhPj4+r8izDmkdqcG3EftWhEx/9KDmc9eOeqSCCIPWkqU6zp3/3F8WJmCaw5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731600623; c=relaxed/simple; bh=tASBFVxte4jEeogh15aOK8X6fcTnpTqFcvGjwQ8/BbY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gIGFVU739wnHPcVynPUM3lalb7otjeCtTpjkVe+t78mSAiyttmpGba8q6a58l0APjRAeSw7bPYsvYqg55w7VvRJAOKExQ1OGhvQt+unLPx/x/1IBnOthmB1NAM3XGpJ5KnfyaaMoPItQsNnNfTt3EG/JBk2Cw46rN1ebN6ioFw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=KPTaZ21q; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KPTaZ21q" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AEAPvdJ031268; Thu, 14 Nov 2024 16:10:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2d8lH+LvVClXz36Mw/guiwdLgrwKANSS/DsNzWrGd9Q=; b=KPTaZ21qXAW0gQc+ Xd/9monuKIiczx6ORPV69hBYzKaJEFY7lb6RFG+2PuDKFeTW2/WGmvdokDCXTMIJ gVFjqAPx6D0jOHdIVoMoTnScBfZRZjMipMWA7hUDAY1QqfUd+gpuebhA4X6onyaU IOiVZogv3i++uMWL+C6tnMvTzKFKCF5kHJSghgBchbTF8FFhp0zorE+GYFdboKmK RbdIXBpCs87iCeT/Pg5juac6dU7PEeNqkiLYqRm4Ke4WJq6J6+bzGZj3P6jpLcXt lgdTfNSt0ueR+5meFsLDktKs3WVYFHMsfLI7oNMJGeXFyd1cQCY3bV4ZVMbky5Ea 7IvuIw== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42w66gucpv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:10:08 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AEGA7JI019116 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 16:10:07 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 14 Nov 2024 08:10:02 -0800 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , Subject: [PATCH RESEND v17 5/5] iommu/arm-smmu: add ACTLR data and support for qcom_smmu_500 Date: Thu, 14 Nov 2024 21:37:21 +0530 Message-ID: <20241114160721.1527934-6-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> References: <20241114160721.1527934-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: q47SVlZGnUZsOv5plWKerGt4nUpGic5e X-Proofpoint-ORIG-GUID: q47SVlZGnUZsOv5plWKerGt4nUpGic5e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 suspectscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140126 Content-Type: text/plain; charset="utf-8" Add ACTLR data table for qcom_smmu_500 including corresponding data entry and set prefetch value by way of a list of compatible strings. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index b595fee23836..5106103574ab 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -16,8 +16,40 @@ #define QCOM_DUMMY_VAL -1 +/* + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch + * buffer). The remaining bits are implementation defined and vary across + * SoCs. + */ + +#define CPRE (1 << 1) +#define CMTLB (1 << 0) +#define PREFETCH_SHIFT 8 +#define PREFETCH_DEFAULT 0 +#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) +#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) +#define PREFETCH_DEEP (3 << PREFETCH_SHIFT) #define GFX_ACTLR_PRR (1 << 5) +static const struct of_device_id qcom_smmu_actlr_client_of_match[] =3D { + { .compatible =3D "qcom,adreno", + .data =3D (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, + { .compatible =3D "qcom,adreno-gmu", + .data =3D (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, + { .compatible =3D "qcom,adreno-smmu", + .data =3D (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, + { .compatible =3D "qcom,fastrpc", + .data =3D (const void *) (PREFETCH_DEEP | CPRE | CMTLB) }, + { .compatible =3D "qcom,sc7280-mdss", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sc7280-venus", + .data =3D (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) }, + { .compatible =3D "qcom,sm8550-mdss", + .data =3D (const void *) (PREFETCH_DEFAULT | CMTLB) }, + { } +}; + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -620,6 +652,7 @@ static const struct qcom_smmu_match_data qcom_smmu_500_= impl0_data =3D { .impl =3D &qcom_smmu_500_impl, .adreno_impl =3D &qcom_adreno_smmu_500_impl, .cfg =3D &qcom_smmu_impl0_cfg, + .client_match =3D qcom_smmu_actlr_client_of_match, }; /* -- 2.34.1