From nobody Sat Nov 23 02:01:46 2024 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE2DB1885A0 for ; Thu, 14 Nov 2024 15:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731598094; cv=none; b=YHRMQOKiHMC+shAM19HA6EO+qQgbYlRaGdzpQ5kHIjcPFuAhW+Ri7YBHbWOYKJ1GVzBZwMgIZ+cgwghLBnQnVKj3WbvZBYmkuGhGsMP5ORABvUcvlQr3SODrZPd6PksksiRfmAC27ucFaXDGAYvkO6BPeYuehFVqEL6k8RWyajo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731598094; c=relaxed/simple; bh=1NDcJXAKcGZ1dPpljAd9JktQomawPmUw/nribxH/D24=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Oufd1wFjU65bab3xiUBibVm6L56Jr+TkmUZHL1VkBE4RqzPRqbG1m8iXIAU3AmNXP75OrHk6N3XetOSVmTFPxiNtxTpRY93OW/Jn2KLc2HzG3qmKyvQOrf3P7yck+Ok1yPkgIFAPPd6jC/9ruRGCrnpy5vlZe1G6od99AAovUYE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from [2601:18c:9101:a8b6:6e0b:84ff:fee2:98bb] (helo=imladris.surriel.com) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tBbkp-000000008IN-1kfO; Thu, 14 Nov 2024 10:27:31 -0500 From: Rik van Riel To: linux-kernel@vger.kernel.org Cc: dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, kernel-team@meta.com, hpa@zytor.com, Rik van Riel Subject: [PATCH 1/2] x86,tlb: update mm_cpumask lazily Date: Thu, 14 Nov 2024 10:26:16 -0500 Message-ID: <20241114152723.1294686-2-riel@surriel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114152723.1294686-1-riel@surriel.com> References: <20241114152723.1294686-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" On busy multi-threaded workloads, there can be significant contention on the mm_cpumask at context switch time. Reduce that contention by updating mm_cpumask lazily, setting the CPU bit at context switch time (if not already set), and clearing the CPU bit at the first TLB flush sent to a CPU where the process isn't running. When a flurry of TLB flushes for a process happen, only the first one will be sent to CPUs where the process isn't running. The others will be sent to CPUs where the process is currently running. On an AMD Milan system with 36 cores, there is a noticeable difference: $ hackbench --groups 20 --loops 10000 Before: ~4.5s +/- 0.1s After: ~4.2s +/- 0.1s Signed-off-by: Rik van Riel --- arch/x86/kernel/alternative.c | 10 +++++++--- arch/x86/mm/tlb.c | 19 +++++++++---------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index d17518ca19b8..8b66a555d2f0 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -1825,11 +1825,18 @@ static inline temp_mm_state_t use_temporary_mm(stru= ct mm_struct *mm) return temp_state; } =20 +__ro_after_init struct mm_struct *poking_mm; +__ro_after_init unsigned long poking_addr; + static inline void unuse_temporary_mm(temp_mm_state_t prev_state) { lockdep_assert_irqs_disabled(); + switch_mm_irqs_off(NULL, prev_state.mm, current); =20 + /* Clear the cpumask, to indicate no TLB flushing is needed anywhere */ + cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(poking_mm)); + /* * Restore the breakpoints if they were disabled before the temporary mm * was loaded. @@ -1838,9 +1845,6 @@ static inline void unuse_temporary_mm(temp_mm_state_t= prev_state) hw_breakpoint_restore(); } =20 -__ro_after_init struct mm_struct *poking_mm; -__ro_after_init unsigned long poking_addr; - static void text_poke_memcpy(void *dst, const void *src, size_t len) { memcpy(dst, src, len); diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index b0d5a644fc84..cc4e57ae690f 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -606,18 +606,15 @@ void switch_mm_irqs_off(struct mm_struct *unused, str= uct mm_struct *next, cond_mitigation(tsk); =20 /* - * Stop remote flushes for the previous mm. - * Skip kernel threads; we never send init_mm TLB flushing IPIs, - * but the bitmap manipulation can cause cache line contention. + * Leave this CPU in prev's mm_cpumask. Atomic writes to + * mm_cpumask can be expensive under contention. The CPU + * will be removed lazily at TLB flush time. */ - if (prev !=3D &init_mm) { - VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu, - mm_cpumask(prev))); - cpumask_clear_cpu(cpu, mm_cpumask(prev)); - } + VM_WARN_ON_ONCE(prev !=3D &init_mm && !cpumask_test_cpu(cpu, + mm_cpumask(prev))); =20 /* Start receiving IPIs and then read tlb_gen (and LAM below) */ - if (next !=3D &init_mm) + if (next !=3D &init_mm && !cpumask_test_cpu(cpu, mm_cpumask(next))) cpumask_set_cpu(cpu, mm_cpumask(next)); next_tlb_gen =3D atomic64_read(&next->context.tlb_gen); =20 @@ -761,8 +758,10 @@ static void flush_tlb_func(void *info) count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED); =20 /* Can only happen on remote CPUs */ - if (f->mm && f->mm !=3D loaded_mm) + if (f->mm && f->mm !=3D loaded_mm) { + cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(f->mm)); return; + } } =20 if (unlikely(loaded_mm =3D=3D &init_mm)) --=20 2.45.2 From nobody Sat Nov 23 02:01:46 2024 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE39518CC00 for ; Thu, 14 Nov 2024 15:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731598094; cv=none; b=eby4dLG/SrlOi1OuqK2OtLfAI9OijVrjRNs061AGX6KIbkexi7SNaLmGBp2u84HwlS+o9F1y/Jq4NX7osazkFdGB/by8fGM8qbKn769fOVCnVT3UoGh6hs5XMHvU/htOeJ4EaPILPvhgneOusQK+Ts5Lj3oKxLu6qM/XJ3Bxy00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731598094; c=relaxed/simple; bh=YrWLsmiA2Vcjb4xRQDtplzTczIAp+pjAu2Wsj235wHw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iASErfEJ1U7i+74NlM9W1K7PSao2Qj32pHqNPopQTRkChGrabKBdQDypCWKjMTR77BneCm2VgVrHnajo2lyRxBAQhSiTTo26CJrNWHqklrr7a9Ej9VEMzY0ZNGYBJ1UhHGPgrc9HxDr27bpO2SE13pqZj+Zo4ceX7OiVnF9t1wE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from [2601:18c:9101:a8b6:6e0b:84ff:fee2:98bb] (helo=imladris.surriel.com) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tBbkp-000000008IN-1vYC; Thu, 14 Nov 2024 10:27:31 -0500 From: Rik van Riel To: linux-kernel@vger.kernel.org Cc: dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, kernel-team@meta.com, hpa@zytor.com, Rik van Riel , Dave Hansen Subject: [PATCH 2/2] x86,tlb: add tracepoint for TLB flush IPI to stale CPU Date: Thu, 14 Nov 2024 10:26:17 -0500 Message-ID: <20241114152723.1294686-3-riel@surriel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114152723.1294686-1-riel@surriel.com> References: <20241114152723.1294686-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Add a tracepoint when we send a TLB flush IPI to a CPU that used to be in the mm_cpumask, but isn't any more. Suggested-by: Dave Hansen Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 1 + include/linux/mm_types.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index cc4e57ae690f..1aac4fa90d3d 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -760,6 +760,7 @@ static void flush_tlb_func(void *info) /* Can only happen on remote CPUs */ if (f->mm && f->mm !=3D loaded_mm) { cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(f->mm)); + trace_tlb_flush(TLB_REMOTE_WRONG_CPU, 0); return; } } diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index 6e3bdf8e38bc..6b6f05404304 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -1335,6 +1335,7 @@ enum tlb_flush_reason { TLB_LOCAL_SHOOTDOWN, TLB_LOCAL_MM_SHOOTDOWN, TLB_REMOTE_SEND_IPI, + TLB_REMOTE_WRONG_CPU, NR_TLB_FLUSH_REASONS, }; =20 --=20 2.45.2