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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2024 11:03:02.4393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cf2a6c8-25b9-478f-ac4b-08dd049be897 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B077.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7986 Content-Type: text/plain; charset="utf-8" Add AMDI0015 _HID for Designware I3C driver so that the dw-i3c-master driver can be probed on AMD platforms. Reviewed-by: Jarkko Nikula Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/dw-i3c-master.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 8d694672c110..1a7c300b6d45 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -1748,12 +1748,19 @@ static const struct of_device_id dw_i3c_master_of_m= atch[] =3D { }; MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); =20 +static const struct acpi_device_id amd_i3c_device_match[] =3D { + { "AMDI0015" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match); + static struct platform_driver dw_i3c_driver =3D { .probe =3D dw_i3c_probe, .remove_new =3D dw_i3c_remove, .driver =3D { .name =3D "dw-i3c-master", .of_match_table =3D dw_i3c_master_of_match, + .acpi_match_table =3D amd_i3c_device_match, .pm =3D &dw_i3c_pm_ops, }, }; --=20 2.34.1 From nobody Sat Nov 23 04:59:14 2024 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2065.outbound.protection.outlook.com [40.107.101.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5BDA1F8F0A for ; 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Thu, 14 Nov 2024 05:03:02 -0600 From: Shyam Sundar S K To: Alexandre Belloni , Jarkko Nikula CC: , , , Shyam Sundar S K Subject: [PATCH v2 2/2] i3c: dw: Add quirk to address OD/PP timing issue on AMD platform Date: Thu, 14 Nov 2024 16:32:39 +0530 Message-ID: <20241114110239.660551-3-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114110239.660551-1-Shyam-sundar.S-k@amd.com> References: <20241114110239.660551-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B076:EE_|DS7PR12MB8249:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d0cc0dc-4c62-4c10-2c56-08dd049be9fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2024 11:03:04.7625 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d0cc0dc-4c62-4c10-2c56-08dd049be9fa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B076.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8249 Content-Type: text/plain; charset="utf-8" The AMD Legacy I3C is having a problem with its IP, specifically with the push-pull and open-drain pull-up registers. These registers need to be manually programmed for every CCC submission to align with the duty cycle. Therefore, add a quirk to address this issue. Reviewed-by: Jarkko Nikula Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K --- drivers/i3c/master/dw-i3c-master.c | 29 ++++++++++++++++++++++++++++- drivers/i3c/master/dw-i3c-master.h | 1 + 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 1a7c300b6d45..5b5c2e4bdc51 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -220,6 +220,14 @@ =20 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) #define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */ + +/* Timing values to configure 12.5MHz frequency */ +#define AMD_I3C_OD_TIMING 0x4C007C +#define AMD_I3C_PP_TIMING 0x8001A + +/* List of quirks */ +#define AMD_I3C_OD_PP_TIMING BIT(1) + struct dw_i3c_cmd { u32 cmd_lo; u32 cmd_hi; @@ -794,6 +802,12 @@ static int dw_i3c_ccc_get(struct dw_i3c_master *master= , struct i3c_ccc_cmd *ccc) return ret; } =20 +static void amd_configure_od_pp_quirk(struct dw_i3c_master *master) +{ + master->i3c_od_timing =3D AMD_I3C_OD_TIMING; + master->i3c_pp_timing =3D AMD_I3C_PP_TIMING; +} + static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, struct i3c_ccc_cmd *ccc) { @@ -803,6 +817,13 @@ static int dw_i3c_master_send_ccc_cmd(struct i3c_maste= r_controller *m, if (ccc->id =3D=3D I3C_CCC_ENTDAA) return -EINVAL; =20 + /* AMD platform specific OD and PP timings */ + if (master->quirks & AMD_I3C_OD_PP_TIMING) { + amd_configure_od_pp_quirk(master); + writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); + writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); + } + ret =3D pm_runtime_resume_and_get(master->dev); if (ret < 0) { dev_err(master->dev, @@ -1602,6 +1623,8 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, master->maxdevs =3D ret >> 16; master->free_pos =3D GENMASK(master->maxdevs - 1, 0); =20 + master->quirks =3D (unsigned long)device_get_match_data(&pdev->dev); + INIT_WORK(&master->hj_work, dw_i3c_hj_work); ret =3D i3c_master_register(&master->base, &pdev->dev, &dw_mipi_i3c_ops, false); @@ -1675,6 +1698,10 @@ static void dw_i3c_master_restore_addrs(struct dw_i3= c_master *master) =20 static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master) { + /* AMD platform specific OD and PP timings */ + if (master->quirks & AMD_I3C_OD_PP_TIMING) + amd_configure_od_pp_quirk(master); + writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING); writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); @@ -1749,7 +1776,7 @@ static const struct of_device_id dw_i3c_master_of_mat= ch[] =3D { MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); =20 static const struct acpi_device_id amd_i3c_device_match[] =3D { - { "AMDI0015" }, + { "AMDI0015", AMD_I3C_OD_PP_TIMING }, { } }; MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match); diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c= -master.h index 219ff815d3a7..c5cb695c16ab 100644 --- a/drivers/i3c/master/dw-i3c-master.h +++ b/drivers/i3c/master/dw-i3c-master.h @@ -50,6 +50,7 @@ struct dw_i3c_master { u32 bus_free_timing; u32 i2c_fm_timing; u32 i2c_fmp_timing; + u32 quirks; /* * Per-device hardware data, used to manage the device address table * (DAT) --=20 2.34.1