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Thu, 14 Nov 2024 09:55:06 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4AE9t3n2002284; Thu, 14 Nov 2024 09:55:03 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 42t0tm9vy1-1; Thu, 14 Nov 2024 09:55:03 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4AE9t2Oi002264; Thu, 14 Nov 2024 09:55:02 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 4AE9t2SN002254; Thu, 14 Nov 2024 09:55:02 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id 0BC9A5009E0; Thu, 14 Nov 2024 15:25:02 +0530 (+0530) From: Soutrik Mukhopadhyay To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com, quic_abhinavk@quicinc.com Subject: [PATCH v3 1/2] arm64: dts: qcom: sa8775p: add DisplayPort device nodes Date: Thu, 14 Nov 2024 15:24:59 +0530 Message-Id: <20241114095500.18616-2-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241114095500.18616-1-quic_mukhopad@quicinc.com> References: <20241114095500.18616-1-quic_mukhopad@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pNw6C0cxTMleEnvbbgSSUMIFNMbim9oi X-Proofpoint-GUID: pNw6C0cxTMleEnvbbgSSUMIFNMbim9oi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=792 impostorscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140076 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add device tree nodes for the DPTX0 and DPTX1 controllers with their corresponding PHYs found on Qualcomm SA8775P SoC. Signed-off-by: Soutrik Mukhopadhyay --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 216 +++++++++++++++++++++++++- 1 file changed, 215 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index f7a9d1684a79..b272feae8da1 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3343,6 +3343,25 @@ interrupt-parent =3D <&mdss0>; interrupts =3D <0>; =20 + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss0_dp0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf4_out: endpoint { + remote-endpoint =3D <&mdss0_dp1_in>; + }; + }; + }; + mdss0_mdp_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 @@ -3367,6 +3386,200 @@ }; }; }; + + mdss0_dp0_phy: phy@aec2a00 { + compatible =3D "qcom,sa8775p-edp-phy"; + + reg =3D <0x0 0xaec2a00 0x0 0x200>, + <0x0 0xaec2200 0x0 0xd0>, + <0x0 0xaec2600 0x0 0xd0>, + <0x0 0xaec2000 0x0 0x1c8>; + + clocks =3D<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names =3D "aux", + "cfg_ahb"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss0_dp1_phy: phy@aec5a00 { + compatible =3D "qcom,sa8775p-edp-phy"; + + reg =3D <0x0 0xaec5a00 0x0 0x200>, + <0x0 0xaec5200 0x0 0xd0>, + <0x0 0xaec5600 0x0 0xd0>, + <0x0 0xaec5000 0x0 0x1c8>; + + clocks =3D<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names =3D "aux", + "cfg_ahb"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss0_dp0: displayport-controller@af54000 { + compatible =3D "qcom,sa8775p-dp"; + + reg =3D <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0x0c0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x09c>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <12>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + phys =3D <&mdss0_dp0_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss0_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss0_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp1: displayport-controller@af5c000 { + compatible =3D "qcom,sa8775p-dp"; + + reg =3D <0x0 0xaf5c000 0x0 0x104>, + <0x0 0xaf5c200 0x0 0x0c0>, + <0x0 0xaf5d000 0x0 0x770>, + <0x0 0xaf5e000 0x0 0x09c>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <13>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; + phys =3D <&mdss0_dp1_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp1_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss0_dp1_in: endpoint { + remote-endpoint =3D <&dpu_intf4_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss0_dp1_out: endpoint { }; + }; + }; + + dp1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; }; =20 dispcc0: clock-controller@af00000 { @@ -3376,7 +3589,8 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, + <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, <0>, <0>, <0>, <0>; power-domains =3D <&rpmhpd SA8775P_MMCX>; #clock-cells =3D <1>; --=20 2.17.1