From nobody Sat Nov 23 05:50:37 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E75C21DED49; Thu, 14 Nov 2024 05:52:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731563541; cv=none; b=g2uSf3yiOyRAJD+4wroy+WvrgQZesQbUxbvG+zbVCnwVksFmQxkiJUKbVdEj1dFj4jJAA4tJvx+ISZ7EL7BuKvrwO0rd6Mu9j46WeiIlto4G6nMnR/PkP8JSkbMIf/9Sb0YWDa+nvBf4LNh9rum5ig9NCYapniMNbfKPFd5r7X0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731563541; c=relaxed/simple; bh=Ew4z1WBIcmqukoK01moZWAum8Hdt8Tycrv6IwEAEKgI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ucCioS0C0QN7EhwwS2Pre5H7udjY0lnSwTzV1yd3gAG8kbRj6GL0qo8hWyF09beUJlXBFi6wmWVlqmOVxpybai9gHHYcRLesnh+rDinrydSYTgD4vcidPDdnUVsuNQ+VH8nz++b+h0u1B9a3P7QGe2obxY5/7Q1MkEHjVOanfAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Jep60mUz; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Jep60mUz" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ADH1Qgs015443; Thu, 14 Nov 2024 05:52:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VmJX73oqsgn97s2X9yAj6SChKCmcJdHnetJDJrx/F8A=; b=Jep60mUzJ54gffmt CQVvEhGalGwMen5lRsFFlCqLVBsJtaPrc9bH8gHV6dTLwgztJLqsgh1LVVtYUErM dsih9IpjkK8QOYOxEu2NmpTFoxKfmt+r1T6ggPv4LZ9YpIpjV65b1p2ydOd7sygy Fy+ildIGCO/Y2hr+YtziOvxDD6Dlwm0CqlCjovBUI7dCBinkx25nmDkzvl8ZJEWx oO2gAOGu922hhSIkl00rDbcRSrTdxscBQLlBIyfCiVE1jSnxzIAk7IzwVJCSF1jP 0Gq9FyCg/J4m2m9yoRSE/RxgafxEXxOC4zzjdZik+HY/GagVxCe0z7ADvr/Es3kq 4l0qyg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42vsf32utu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 05:52:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AE5qFun004973 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Nov 2024 05:52:15 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 21:52:11 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Konrad Dybcio , Conor Dooley , "Dmitry Baryshkov" CC: , , , , , Krishna Kurapati Subject: [PATCH v4 1/2] arm64: dts: qcom: Add support for usb nodes on QCS8300 Date: Thu, 14 Nov 2024 11:21:51 +0530 Message-ID: <20241114055152.1562116-2-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241114055152.1562116-1-quic_kriskura@quicinc.com> References: <20241114055152.1562116-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wtABYQ5AORiAH18Q5mDIwP3JmFLYpvdf X-Proofpoint-GUID: wtABYQ5AORiAH18Q5mDIwP3JmFLYpvdf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140043 Content-Type: text/plain; charset="utf-8" Add support for USB controllers on QCS8300. The second controller is only High Speed capable. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 187 ++++++++++++++++++++++++++ 1 file changed, 187 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 2c35f96c3f28..b4116ce68f4f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -1363,6 +1363,193 @@ IPCC_MPROC_SIGNAL_GLINK_QMP qcom,remote-pid =3D <5>; }; }; + + usb_1_hsphy: phy@8904000 { + compatible =3D "qcom,qcs8300-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg =3D <0x0 0x08904000 0x0 0x400>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_USB2_PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_2_hsphy: phy@8906000 { + compatible =3D "qcom,qcs8300-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg =3D <0x0 0x08906000 0x0 0x400>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_USB2_PHY_SEC_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_qmpphy: phy@8907000 { + compatible =3D "qcom,qcs8300-qmp-usb3-uni-phy"; + reg =3D <0x0 0x08907000 0x0 0x2000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "com_aux", + "pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names =3D "phy", "phy_phy"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "usb3_prim_phy_pipe_clk_src"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible =3D "qcom,qcs8300-dwc3", "qcom,dwc3"; + reg =3D <0x0 0x0a6f8800 0x0 0x400>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + wakeup-source; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xe000>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x80 0x0>; + phys =3D <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + + usb_2: usb@a4f8800 { + compatible =3D "qcom,qcs8300-dwc3", "qcom,dwc3"; + reg =3D <0x0 0x0a4f8800 0x0 0x400>; + + clocks =3D <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <120000000>; + + interrupts-extended =3D <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains =3D <&gcc GCC_USB20_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB20_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + qcom,select-utmi-as-pipe-clk; + wakeup-source; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x0a400000 0x0 0xe000>; + + interrupts =3D ; + iommus =3D <&apps_smmu 0x20 0x0>; + + phys =3D <&usb_2_hsphy>; + phy-names =3D "usb2-phy"; + maximum-speed =3D "high-speed"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; 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charset="utf-8" Enable primary USB controller on QCS8300 Ride platform. The primary USB controller is made "peripheral", as this is intended to be connected to a host for debugging use cases. For using the controller in host mode, changing the dr_mode and adding appropriate pinctrl nodes to provide vbus would be sufficient. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index 7eed19a694c3..3e925228379c 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -265,3 +265,26 @@ &ufs_mem_phy { vdda-pll-supply =3D <&vreg_l5a>; status =3D "okay"; }; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l7a>; + vdda18-supply =3D <&vreg_l7c>; + vdda33-supply =3D <&vreg_l9a>; + + status =3D "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply =3D <&vreg_l7a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; --=20 2.34.1