From nobody Sat Nov 23 08:46:26 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D0C31F81AC for ; Wed, 13 Nov 2024 09:49:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491386; cv=none; b=M+RmtGEA93W4ha8IpSYpqmDb5XaUmn2ArXs/W4MBHlHGhQxPCspdCtdUvv3MhWUlKJH6+QeMiBUFaR96wfHfKbbyxD4XYVsbWses8FEh2nA/APn3EtSxDPElhooe2IkbhCJp5K+l0Ri2yyh1pvV5Z5SPOp/NSASwpot1IDECejg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491386; c=relaxed/simple; bh=rpZVhh7T3jG7l1qF+ddAzi2T8R7C+nAAJv+RA4LhY3w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UFnuhqhw60HBkRMDeLIz4NZO4CMDswCfDwFL4g61b+FrPaSKcayyxCgWtzaP+nzoeA15GQBX4NQeAPO5n2Nxt8XRfHPnbZmckmLdD2UG6PxvK9BrxNPtTyQwoXTDy34xbOvb3PZnN7kF0oyyH2cxfFF6etffhSuFEagOSXfqRRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=RpX7YP4x; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="RpX7YP4x" Received: by mail.gandi.net (Postfix) with ESMTPA id 1AAB1C0009; Wed, 13 Nov 2024 09:49:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731491382; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DboNf32L7z0z0SUhP1AY5oAny3hFWKZHz0IZ1px16rw=; b=RpX7YP4xy23C0dEMl+n1w4m1fJ9N6NKulXQmrzL7D671API6QHv+ABkN1mUokm7dXspswo 4XFC038lVVCNTF0DKZx9RS+tCKHYn4eHyNLN7DMAjsYAx7rIOhatNDzXeYY4gUWetAVjTQ DdGmTpHSUhN98RDqi19W4SNoowRQg2/5wO3TtWpMsDQ34pbuhQ3aAdUpztR2bkRlgI1AuX K5VFcvQrW8S4rg/P7omNy2H49noPDYbjpvYNox7mEnzOYgroaFzNc8lAOy0tdhX6pv0XKK L52cBSK7NIlmvPw/wXj/nlMP21FfvQ5UFJrEuER4GG0uLfvp1Nm14oE3QO+Rzg== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v3 1/7] memory: ti-aemif: Create aemif_check_cs_timings() Date: Wed, 13 Nov 2024 10:49:32 +0100 Message-ID: <20241113094938.44817-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113094938.44817-1-bastien.curutchet@bootlin.com> References: <20241113094938.44817-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" aemif_calc_rate() check the validity of a new computed timing against a 'max' value given as input. This isn't convenient if we want to check the CS timing configuration somewhere else in the code. Wrap the verification of all the chip select's timing configuration into a single function to ease its exportation in upcoming patches. Remove the 'max' input from aemif_calc_rate() as it's no longer used. Signed-off-by: Bastien Curutchet --- drivers/memory/ti-aemif.c | 89 ++++++++++++++++++++++++++++++--------- 1 file changed, 69 insertions(+), 20 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index d54dc3cfff73..eef086c8371b 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -107,6 +107,27 @@ struct aemif_cs_data { u8 asize; }; =20 +/** + * struct aemif_cs_timings: structure to hold CS timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold: read hold width + * @rstrobe: read strobe width + * @rsetup: read setup width + * @whold: write hold width + * @wstrobe: write strobe width + * @wsetup: write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -125,18 +146,48 @@ struct aemif_device { struct aemif_cs_data cs_data[NUM_CS]; }; =20 +/** + * aemif_check_cs_timings - Check the validity of a CS timing configuratio= n. + * @timings: timings configuration + * + * @return: 0 if the timing configuration is valid, negative errno otherwi= se. + */ +static int aemif_check_cs_timings(struct aemif_cs_timings *timings) +{ + if (timings->ta > TA_MAX) + return -EINVAL; + + if (timings->rhold > RHOLD_MAX) + return -EINVAL; + + if (timings->rstrobe > RSTROBE_MAX) + return -EINVAL; + + if (timings->rsetup > RSETUP_MAX) + return -EINVAL; + + if (timings->whold > WHOLD_MAX) + return -EINVAL; + + if (timings->wstrobe > WSTROBE_MAX) + return -EINVAL; + + if (timings->wsetup > WSETUP_MAX) + return -EINVAL; + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for * @wanted: The cycle time needed in nanoseconds. * @clk: The input clock rate in kHz. - * @max: The maximum divider value that can be programmed. * * On success, returns the calculated timing value minus 1 for easy * programming into AEMIF timing registers, else negative errno. */ -static int aemif_calc_rate(struct platform_device *pdev, int wanted, - unsigned long clk, int max) +static int aemif_calc_rate(struct platform_device *pdev, int wanted, unsig= ned long clk) { int result; =20 @@ -149,10 +200,6 @@ static int aemif_calc_rate(struct platform_device *pde= v, int wanted, if (result < 0) result =3D 0; =20 - /* ... But configuring tighter timings is not an option. */ - else if (result > max) - result =3D -EINVAL; - return result; } =20 @@ -174,30 +221,32 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned long clk_rate =3D aemif->clk_rate; + struct aemif_cs_timings timings; unsigned offset; u32 set, val; + int ret; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); - rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); - rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); - rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); - whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); - wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); - wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); + timings.ta =3D aemif_calc_rate(pdev, data->ta, clk_rate); + timings.rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate); + timings.rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate); + timings.rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate); + timings.whold =3D aemif_calc_rate(pdev, data->whold, clk_rate); + timings.wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate); + timings.wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate); =20 - if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || - whold < 0 || wstrobe < 0 || wsetup < 0) { + ret =3D aemif_check_cs_timings(&timings); + if (ret) { dev_err(&pdev->dev, "%s: cannot get suitable timings\n", __func__); - return -EINVAL; + return ret; } =20 - set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | - WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + set =3D TA(timings.ta) | + RHOLD(timings.rhold) | RSTROBE(timings.rstrobe) | RSETUP(timings.rsetup)= | + WHOLD(timings.whold) | WSTROBE(timings.wstrobe) | WSETUP(timings.wsetup); =20 set |=3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) --=20 2.47.0 From nobody Sat Nov 23 08:46:26 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2902C1F8EF3 for ; Wed, 13 Nov 2024 09:49:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491387; cv=none; b=XmZSmg1NfgHF444l4BvpfnqKpfXU22XeligOlubJAtx2Ai0nYIlbqt5N97cheLLC/yoh6KTPZGYWwz7UMuSbPQpZ/3Ek9zI6Z9d2ENwSJhlNwvzcGCiPl0Zt4dldOnmkEPzfEw/ti8dxLjvLBFz9KnmIXXxhDBSGWc5vjtQV3So= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491387; c=relaxed/simple; bh=3ypZsUz4tTp5D7oBMBsyNYdL595hWT8C2TIRWapqBF4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hugM6mJq4IDLLlnRY1qFg1VNzrc1xp0ihloElNCFzgQfHCN/LK5PGMdykTvTkT2uMnApckCj3XemVSkRKznfJ/uW9g/A2x9d5afsPwjUQwGdLbm4SuU1gXaa/bOyng9jE6zGWiOmUSbX/sx7xosQL5hTGIqkhhN9NZ2D0Tuo3vI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=FUXEMt5A; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="FUXEMt5A" Received: by mail.gandi.net (Postfix) with ESMTPA id A4328C000D; Wed, 13 Nov 2024 09:49:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731491383; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e12TUryYZQDpAftpWISfRSW9eY/LIPfb/YxlEWXq1Ws=; b=FUXEMt5AiYsS+gIvemKoLqcLfoQJvjqMiEkKNOc6wHWdbaJd4kP25/BBPEmmPxYV/9DX4h TgNcBqfOGP1xEGCujVlbVZh3dRXueMeDx3SflQk/D0BsE6pLwWKRTJa9kjhBce6Q/jMY7K 1B5u8agXRk4xh7FKsmNQIZ45fkYsE1ODp+Ko6RdsG1vf6eYBKvvHg7G4KOGEZbfxqcSIPG ppM7klwgEjGwHVTfSpBeQXAJFqWzR2U1SXg1Em24syT2iQuaKKwoEjPRM/LgyuHseLohDU f3QYUHF+6CgKZMedpl2crfU2rXi/g91aRg1nwQFqV7a31S/N09z0USk729sNCQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v3 2/7] memory: ti-aemif: Create aemif_set_cs_timings() Date: Wed, 13 Nov 2024 10:49:33 +0100 Message-ID: <20241113094938.44817-3-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113094938.44817-1-bastien.curutchet@bootlin.com> References: <20241113094938.44817-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Create an aemif_set_cs_timings() function to isolate the setting of a chip select timing configuration and ease its exportation. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 64 ++++++++++++++++++++++++++++++--------- 1 file changed, 49 insertions(+), 15 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index eef086c8371b..b1236cc9ce92 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,15 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 =20 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) =20 /** * struct aemif_cs_data: structure to hold cs parameters @@ -178,6 +178,44 @@ static int aemif_check_cs_timings(struct aemif_cs_timi= ngs *timings) return 0; } =20 +/** + * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure + * @timings: timings configuration to set + * + * @return: 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + int ret; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + ret =3D aemif_check_cs_timings(timings); + if (ret) + return ret; + + set =3D TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrob= e) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset =3D A1CR_OFFSET + cs * 4; + + val =3D readl(aemif->base + offset); + val &=3D ~TIMINGS_MASK; + val |=3D set; + writel(val, aemif->base + offset); + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for @@ -244,11 +282,7 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) return ret; } =20 - set =3D TA(timings.ta) | - RHOLD(timings.rhold) | RSTROBE(timings.rstrobe) | RSETUP(timings.rsetup)= | - WHOLD(timings.whold) | WSTROBE(timings.wstrobe) | WSETUP(timings.wsetup); - - set |=3D (data->asize & ACR_ASIZE_MASK); + set =3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |=3D ACR_EW_MASK; if (data->enable_ss) @@ -259,7 +293,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) val |=3D set; writel(val, aemif->base + offset); =20 - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } =20 static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) --=20 2.47.0 From nobody Sat Nov 23 08:46:26 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2F651F8907 for ; Wed, 13 Nov 2024 09:49:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491387; cv=none; b=QvNfxNAmao3ii3qvubUWrmD6bCoBrtIizl2PGcgOMm8gECQniDTk+nDx45RpSXPsR8zQrP6OTt1mc3KTjJslS+m74+oF5njD/BUpeuEaTtaiBeUsp7FWTXqasiSrN9foXNLIVE+jAgnvhQ3qMhifw9RrZyAsIcogVPtWtLHscPA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491387; c=relaxed/simple; bh=1FwHQEoA2YTJoBbFBsF4uPWOlB+W/e37wZ4S+srxhIc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=feMSBAOAaKf3/wf5lMrFr/EzZsHUhvb1nMwyqqVyTMIqo/RZGBbCnH26lkmjfzPAqXP5aKbvQr4HQSm78mfg7wgiZvmiOvBLETIKKPvF5bD965zeUY5DlR1ErXaGBaRE6IL8OoskdVn2GFjSk5geZVH+c0UF41pdXHevMdu2eOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=n6trIros; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="n6trIros" Received: by mail.gandi.net (Postfix) with ESMTPA id 44304C0010; Wed, 13 Nov 2024 09:49:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731491383; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ftvpwn96mp9ab3nuZr5CAWZJs/gZEbrT9Z+Np+LNnAM=; b=n6trIrospMQgZEq1BIu99SNM5abH5y0xz3gZAp+DtEcJarVmJhOTtczdlEMc8odqe6p74c 6fGSAGEpuXisjfl7T0iDAstHe9fFwwmuYI9LrQETe/Lmu3mCR4BWw+aN8X0xdHuzQEtp4i gVNxLjABRCWchK7QCDWzkZ7vLVTvlP8QC0MpGf85tDLb8RydvhOBYRr/C/OZuZ5RHD2Ugu iHMwaw5TAkRLjKX5TaAwrcmwlVpY1OFWMylnIN+cpCWeQJJADZDT9hm1GgZAC3g7fHas8/ 0Eln6DaDFXHMlxPvlq5zmLGn4mzPyiUmWCfsb5sJ3zY59Op0RT/P5qUEeCca1w== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v3 3/7] memory: ti-aemif: Export aemif_*_cs_timings() Date: Wed, 13 Nov 2024 10:49:34 +0100 Message-ID: <20241113094938.44817-4-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113094938.44817-1-bastien.curutchet@bootlin.com> References: <20241113094938.44817-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Export the aemif_set_cs_timing() and aemif_check_cs_timing() symbols so they can be used by other drivers Add a mutex to protect the CS configuration register from concurrent accesses between the AEMIF and its 'children'. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 36 ++++++++++++--------------------- include/linux/memory/ti-aemif.h | 32 +++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 23 deletions(-) create mode 100644 include/linux/memory/ti-aemif.h diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index b1236cc9ce92..7f0ca256db3c 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -13,7 +13,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -107,27 +109,6 @@ struct aemif_cs_data { u8 asize; }; =20 -/** - * struct aemif_cs_timings: structure to hold CS timing configuration - * values are expressed in number of clock cycles - 1 - * @ta: minimum turn around time - * @rhold: read hold width - * @rstrobe: read strobe width - * @rsetup: read setup width - * @whold: write hold width - * @wstrobe: write strobe width - * @wsetup: write setup width - */ -struct aemif_cs_timings { - u32 ta; - u32 rhold; - u32 rstrobe; - u32 rsetup; - u32 whold; - u32 wstrobe; - u32 wsetup; -}; - /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -136,6 +117,7 @@ struct aemif_cs_timings { * @num_cs: number of assigned chip-selects * @cs_offset: start number of cs nodes * @cs_data: array of chip-select settings + * @config_cs_lock: lock used to access CS configuration */ struct aemif_device { void __iomem *base; @@ -144,6 +126,7 @@ struct aemif_device { u8 num_cs; int cs_offset; struct aemif_cs_data cs_data[NUM_CS]; + struct mutex config_cs_lock; }; =20 /** @@ -152,7 +135,7 @@ struct aemif_device { * * @return: 0 if the timing configuration is valid, negative errno otherwi= se. */ -static int aemif_check_cs_timings(struct aemif_cs_timings *timings) +int aemif_check_cs_timings(struct aemif_cs_timings *timings) { if (timings->ta > TA_MAX) return -EINVAL; @@ -177,6 +160,7 @@ static int aemif_check_cs_timings(struct aemif_cs_timin= gs *timings) =20 return 0; } +EXPORT_SYMBOL(aemif_check_cs_timings); =20 /** * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. @@ -186,7 +170,7 @@ static int aemif_check_cs_timings(struct aemif_cs_timin= gs *timings) * * @return: 0 on success, else negative errno. */ -static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings) { unsigned int offset; u32 val, set; @@ -208,13 +192,16 @@ static int aemif_set_cs_timings(struct aemif_device *= aemif, u8 cs, struct aemif_ =20 offset =3D A1CR_OFFSET + cs * 4; =20 + mutex_lock(&aemif->config_cs_lock); val =3D readl(aemif->base + offset); val &=3D ~TIMINGS_MASK; val |=3D set; writel(val, aemif->base + offset); + mutex_unlock(&aemif->config_cs_lock); =20 return 0; } +EXPORT_SYMBOL(aemif_set_cs_timings); =20 /** * aemif_calc_rate - calculate timing data. @@ -288,10 +275,12 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) if (data->enable_ss) set |=3D ACR_SSTROBE_MASK; =20 + mutex_lock(&aemif->config_cs_lock); val =3D readl(aemif->base + offset); val &=3D ~CONFIG_MASK; val |=3D set; writel(val, aemif->base + offset); + mutex_unlock(&aemif->config_cs_lock); =20 return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } @@ -434,6 +423,7 @@ static int aemif_probe(struct platform_device *pdev) if (IS_ERR(aemif->base)) return PTR_ERR(aemif->base); =20 + mutex_init(&aemif->config_cs_lock); if (np) { /* * For every controller device node, there is a cs device node diff --git a/include/linux/memory/ti-aemif.h b/include/linux/memory/ti-aemi= f.h new file mode 100644 index 000000000000..0640d30f6321 --- /dev/null +++ b/include/linux/memory/ti-aemif.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TI_AEMIF_H +#define __TI_AEMIF_H + +/** + * struct aemif_cs_timings: structure to hold CS timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold: read hold width + * @rstrobe: read strobe width + * @rsetup: read setup width + * @whold: write hold width + * @wstrobe: write strobe width + * @wsetup: write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + +struct aemif_device; + +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings); +int aemif_check_cs_timings(struct aemif_cs_timings *timings); + +#endif // __TI_AEMIF_H --=20 2.47.0 From nobody Sat Nov 23 08:46:26 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5C31F8F09 for ; Wed, 13 Nov 2024 09:49:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491388; cv=none; b=Qo+55k16pz1jqVDbrUuxa0BbyjXMW1mpF/aXrXLMoqjlHM7TTTIiFSE4T20hzWhJ+tTXfiBIN3jVISKzChUuWovL+oSMlobQCKeOhGeP7dhFRQPomqz6xI1SgJup8skgfYpA6FhfG2IocEj7x45lkgLJ34zrccNrFZXboLMCWk4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491388; c=relaxed/simple; bh=h6Ixu3RgfB/yKWn7YlzSBsiXSugceNv8TIHypQHazUA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XklbF/Ehtk71PSyGzJ+kbzgrsiIeF+uELSfthdyvcnm2XEG9/fUKQ35N6SF/VRwYeHpUH9jfLfdqdnhoiUf+HJMQMxXQOEH+NGUESTevBB3LufoIazxe3JXFHf5+vlzec+1+Jt7JqIkQSMelXRMGvIoW7dBvPwWwEwE65HlslrA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=IMq96P9I; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="IMq96P9I" Received: by mail.gandi.net (Postfix) with ESMTPA id D46D2C000E; Wed, 13 Nov 2024 09:49:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731491384; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=260i8Kmy1qIGGfd2CxjTGXG+BKpSWuDOsQ7KscW8IdI=; b=IMq96P9In6IIpdHVT6qJIa3yVx92sCrs2ivv9hdzVcY3aaZbT369sgXTGVN/d/OZR0e7/K ZA47g3QqlSDTjktZoJrkHNf7/hmc3rYHhqZ89LXL1W/qBChmNhq+8PmCuN8aCPDelDUM7J 3lHb7TPnGjimMm2QvHyEtsiPRHaCnDhbYs+QVmtNNRr/7Zm6yBdS5Ij1e8K6bf8qlbAj8U 6dd8GFtihedzk66zZX+7ykVRIjwCVjHm90427ZX0jFK/BPjgOeAHCajN7n1uhzwDDKRuxO wyp6wCe63JLZQ5mgtCrpWU8d0vaCLKZoX5VPa8SMn2K3h6sk9rKLm6eauaVygQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet , kernel test robot Subject: [PATCH v3 4/7] mtd: rawnand: davinci: Always depends on TI_AEMIF Date: Wed, 13 Nov 2024 10:49:35 +0100 Message-ID: <20241113094938.44817-5-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113094938.44817-1-bastien.curutchet@bootlin.com> References: <20241113094938.44817-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" DAVINCI_NAND depends on TI_AEMIF only when ARCH_KEYSTONE is selected while the NAND controller is also always a part of the AEMIF controller on DaVinci SoCs. Set a dependency on TI_AEMIF regardless of the selected architecture. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202411020140.3wsKJOSB-lkp@int= el.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202411020957.X1T8T9ZR-lkp@int= el.com/ Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d0aaccf72d78..bb61434347bd 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -279,8 +279,8 @@ config MTD_NAND_SH_FLCTL =20 config MTD_NAND_DAVINCI tristate "DaVinci/Keystone NAND controller" - depends on ARCH_DAVINCI || (ARCH_KEYSTONE && TI_AEMIF) || COMPILE_TEST - depends on HAS_IOMEM + depends on COMPILE_TEST || ARCH_DAVINCI || ARCH_KEYSTONE + depends on HAS_IOMEM && TI_AEMIF help Enable the driver for NAND flash chips on Texas Instruments DaVinci/Keystone processors. --=20 2.47.0 From nobody Sat Nov 23 08:46:26 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AEF31F8F17 for ; Wed, 13 Nov 2024 09:49:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491389; cv=none; b=HY6VRKn9Vb69u+rLlL/EY7sTB9mYgx+ca2ysM4fjvkrxw+lamzfha+/l5DatixNl/QV/r8idBtiAAXpj3cXeTAtlN9fpiL6YxkpAdNx1z5VHAHOvSWwaQTBA3sKTNgrvXb3fzdwpvL/whLT70r2pMdwvim7J26+Mjy7DXtmXL1g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491389; c=relaxed/simple; bh=deaieWFiVONpNRlAhKMPRKsF7JDojpQ/DZGVZJ9W5Dg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Atzq7uTcoBiaLvWLeEqj1hL0seLKP6zRCYGGSLHpHMdsosmiWjTcJR7w1ISrRSxYIeSMkHiAPp05CBTtHYiCfh5Tp37EwAPsd/tappm9phCntHB+hNTLwBLEyxRwi9dDcd7dGwWub0F+KEACk5PjS1tPw0Bjni1c3ZCEfijoMm0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=G6fus04p; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="G6fus04p" Received: by mail.gandi.net (Postfix) with ESMTPA id B537CC0015; Wed, 13 Nov 2024 09:49:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731491385; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=khZM5fFii6r1q+Z9uZi3Zgk6G9+0lCTuTox0qCES4xo=; b=G6fus04pgyae3nSlDlFWrBF12kmjcAp2kkEukWQwgsFLZV0EYdZxH/fxAQw+TR+r/UN9eo IJm6A0JrbjU7J7KwoGHOgLJJ7Lx83NzMzZtu0n7sDis7qc6E67hrTgoQRpjX4QreskI9MU pzANRQZyMR2dorrEPZniD4VCfSBj7TgyJwIRp6+CNaGZ0dsjDQTFKBBp8AZ2bYi4iLOcZt VggKgwFoeE93a+1xKcTtgwnMvbrD19exqMCmTjg8/1BU9KNrzfQdBzg6jIYSk1jh9Ge56A YjverQ9YVOP2ZXcLVvCoKcXVK5deWTOf265qPcTYCnNN9GTR3jHyY4qiVrtmTg== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v3 5/7] mtd: rawnand: davinci: Order headers alphabetically Date: Wed, 13 Nov 2024 10:49:36 +0100 Message-ID: <20241113094938.44817-6-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113094938.44817-1-bastien.curutchet@bootlin.com> References: <20241113094938.44817-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Order headers alphabetically for better readability. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36..3c0efbdd789e 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,15 +10,15 @@ * Dirk Behme */ =20 -#include -#include -#include #include #include +#include +#include #include #include -#include #include +#include +#include =20 #define NRCSR_OFFSET 0x00 #define NANDFCR_OFFSET 0x60 --=20 2.47.0 From nobody Sat Nov 23 08:46:26 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9E861F8F06 for ; Wed, 13 Nov 2024 09:49:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491389; cv=none; b=H2p58CJUrIQDF/rxB5+QBO5xbsVVvGklYEni0+BCNhx4LIk+SkBWzzuakstNdwx5Rf+snatDxhcACEoCeWaayD2Oq7dfc8ZwDuk0F3EqdUnZbH2L+e3rQWFIdMwZDXUzFTOV1iR2YauJ8FV7CZuQ1N3f7BT3NFqbD5nZ+9NQt48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491389; c=relaxed/simple; bh=jq/HxwUks//QkKP3ZJZNN0GtGvXs1KXTbgyq1k0z2kU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ExxmiNlQ6QrmW0EgV7yng5jHs9qCVBBzqzLAyRPqO9HO8hxrPFQFYlENj0FC2yn42gtwKnG9l5b/MgoVJP0Axq+zt5akSv2AuBgleBf0dN9YIeNcpv6jKpv3KLtSh97hUN5YoPv+mEWCFiwT9HqxyrvLPSPKjttpsS2CuDatUww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=pdPkcgsN; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="pdPkcgsN" Received: by mail.gandi.net (Postfix) with ESMTPA id 63B31C0005; Wed, 13 Nov 2024 09:49:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731491385; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ONE5RIDa+M5HrCVn5iTpaeEU6VZHpy9NTdUHLDL3hak=; b=pdPkcgsNZr9bGMJRCtJGG6Kp9JOneqiNmeOHO3VmnQwisps53nzoczoic5DMXpqBw+a02h TVI3z1jLaK56EReo3fgnPg7YN2kgc4wL/W/zRjuOpb427i+FiDpEmdRpH9h2E72co2OGN4 WtT1uTc4IHf0Xpn8ZsoWsRQBdWq3lmH4q8j7O3kcuJHzVrY3K1tEAsm6ND8nZQ+bBWc0R4 nFQe6sDNjmxjisT94Dq19Dra0FtCQwiakMODZXcKzNaDzidcK1rXOmFRxvTRfBO3uIEvsK 0R6sX/vctlZXoK6kMjTAAkGeLBJ54biRThG4GRxZUq8PZd0X7DMKqfXgOwMebA== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v3 6/7] mtd: rawnand: davinci: Add clock resource Date: Wed, 13 Nov 2024 10:49:37 +0100 Message-ID: <20241113094938.44817-7-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113094938.44817-1-bastien.curutchet@bootlin.com> References: <20241113094938.44817-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" NAND controller has a reference clock inherited from the AEMIF (cf. Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt) This clock isn't used yet by the driver. Add a struct clock in the struct davinci_nand_info so it can be used to compute timings. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 3c0efbdd789e..563045c7ce08 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,6 +10,7 @@ * Dirk Behme */ =20 +#include #include #include #include @@ -117,6 +118,8 @@ struct davinci_nand_info { uint32_t mask_cle; =20 uint32_t core_chipsel; + + struct clk *clk; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -822,6 +825,10 @@ static int nand_davinci_probe(struct platform_device *= pdev) return -EADDRNOTAVAIL; } =20 + info->clk =3D devm_clk_get_enabled(&pdev->dev, "aemif"); + if (IS_ERR(info->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed to get cloc= k"); + info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; --=20 2.47.0 From nobody Sat Nov 23 08:46:26 2024 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 414691F9416 for ; Wed, 13 Nov 2024 09:49:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491390; cv=none; b=R1CLgpG4mQGv3n2w4sg7NbxIW22ZsywFRKw2Cv+2rI9e96z/pqk9/fPhaiZCwW9/Q/UAgUgIqOYDJi7Ja7FKx2i0qcBJ8QSN3yHh7f4gKwHywVUC4NLb0b1Czabtpn2wvEpQG0ql3/sXYPXJZKskhjWQLiuDHNDFq0HUWG0se+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731491390; c=relaxed/simple; bh=pAsRe15o8KtYw/7E0XKTJksMgDoXXLxLoIwfb4FVUuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O9JAdhkVZvO1W1At+3tHHxbGKtFnP/RTYhk0JVvHwVxMs67K+HbF/J3iWYQ3Tvhp78n/Yq7khyLTFhfkLeHUR2qlI2Qbju584CEqVbQJ6+0MzIxZlnkZFJNZBG/2CxKM6q21pouKhlB9kLKRa/yUZupPJmmTVCy0hi4ksSUXG64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=PWh73TkX; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="PWh73TkX" Received: by mail.gandi.net (Postfix) with ESMTPA id 0841DC0014; Wed, 13 Nov 2024 09:49:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731491386; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iaf75RKxvR9hDjbOf8OF/9PhJbQC3X5yKc/JDdimNdQ=; b=PWh73TkXzIlF6hnNs1QIev1z5a0k70PCKg8O5rG3fqtH9+kpiqlOIAB3iwJfYrsJSDpAPj atjVKpSu9FnR8sIdMYIvgPjDm9/FW5as+VVBp2t66Jz4O4sIiwS958u6qnHhOpSLl5VvJO JKRdsNA3p4fQGqiNFt5Hwi8gvJbQZyy/8vyMQwEGIOqzkNtjVB9DuD64DKgw0E0RYqRRiu 7kU3eBeS7JY88rgxYRdGyCwuZCn7I80hOYwvRfLgiygP5A6QCMvB+Utq+5wQ/sj4tnXLKN POX6BnLboUm77Ivequb+dVqdkDZyv07509n0CCrB7FDn5yvpBa2TCf9I+XuzUw== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v3 7/7] mtd: rawnand: davinci: Implement setup_interface() operation Date: Wed, 13 Nov 2024 10:49:38 +0100 Message-ID: <20241113094938.44817-8-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113094938.44817-1-bastien.curutchet@bootlin.com> References: <20241113094938.44817-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com The setup_interface() operation isn't implemented. It forces the driver to use the ONFI mode 0, though it could use more optimal modes. Implement the setup_interface() operation. It uses the aemif_set_cs_timings() function from the AEMIF driver to update the chip select timings. The calculation of the register's contents is directly extracted from =C2=A720.3.2.3 of the DaVinci TRM [1] MAX_TH_PS and MAX_TSU_PS are the worst case timings based on the Keystone2 and DaVinci datasheets. [1] : https://www.ti.com/lit/ug/spruh77c/spruh77c.pdf Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 79 +++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 563045c7ce08..00627c2783f8 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,9 @@ #define MASK_ALE 0x08 #define MASK_CLE 0x10 =20 +#define MAX_TSU_PS 3000 /* Input setup time in ps */ +#define MAX_TH_PS 1600 /* Input hold time in ps */ + struct davinci_nand_pdata { uint32_t mask_ale; uint32_t mask_cle; @@ -120,6 +124,7 @@ struct davinci_nand_info { uint32_t core_chipsel; =20 struct clk *clk; + struct aemif_device *aemif; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -767,9 +772,82 @@ static int davinci_nand_exec_op(struct nand_chip *chip, return 0; } =20 +#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns))) + +static int davinci_nand_setup_interface(struct nand_chip *chip, int chipnr, + const struct nand_interface_config *conf) +{ + struct davinci_nand_info *info =3D to_davinci_nand(nand_to_mtd(chip)); + const struct nand_sdr_timings *sdr; + struct aemif_cs_timings timings; + s32 cfg, min, cyc_ns; + int ret; + + cyc_ns =3D 1000000000 / clk_get_rate(info->clk); + + sdr =3D nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + cfg =3D TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1; + timings.rsetup =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns), + TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1; + timings.rstrobe =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2; + while ((s32)(timings.rsetup + timings.rstrobe) < min) + timings.rstrobe++; + + cfg =3D TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1; + timings.rhold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tRC_min, cyc_ns) - 3; + while ((s32)(timings.rsetup + timings.rstrobe + timings.rhold) < min) + timings.rhold++; + + cfg =3D TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 10= 00), cyc_ns); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1; + timings.ta =3D cfg > 0 ? cfg : 0; + + cfg =3D TO_CYCLES(sdr->tWP_min, cyc_ns) - 1; + timings.wstrobe =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tALS_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1; + timings.wsetup =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tDS_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe) < min) + timings.wstrobe++; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tALH_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1; + timings.whold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tWC_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe + timings.whold) < min) + timings.whold++; + + dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n", + timings.rsetup, timings.rstrobe, timings.rhold); + dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta); + dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n", + timings.wsetup, timings.wstrobe, timings.whold); + + ret =3D aemif_check_cs_timings(&timings); + if (ret || chipnr =3D=3D NAND_DATA_IFACE_CHECK_ONLY) + return ret; + + return aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings); +} + static const struct nand_controller_ops davinci_nand_controller_ops =3D { .attach_chip =3D davinci_nand_attach_chip, .exec_op =3D davinci_nand_exec_op, + .setup_interface =3D davinci_nand_setup_interface, }; =20 static int nand_davinci_probe(struct platform_device *pdev) @@ -832,6 +910,7 @@ static int nand_davinci_probe(struct platform_device *p= dev) info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; + info->aemif =3D dev_get_drvdata(pdev->dev.parent); =20 mtd =3D nand_to_mtd(&info->chip); mtd->dev.parent =3D &pdev->dev; --=20 2.47.0