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Acked-by: Conor Dooley Signed-off-by: Varadarajan Narayanan --- v2: Add 'Acked-by: Conor Dooley' --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Do= cumentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 4aed4b5d65ec..39851ba9de43 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - qcom,ipq5424-qusb2-phy - qcom,ipq6018-qusb2-phy - qcom,ipq8074-qusb2-phy - qcom,ipq9574-qusb2-phy --=20 2.34.1 From nobody Sat Nov 23 09:22:13 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC1F917B4E9; Wed, 13 Nov 2024 07:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add the phy init sequence for the Super Speed ports found on IPQ5424. Signed-off-by: Varadarajan Narayanan Reviewed-by: Dmitry Baryshkov --- v2: Change uppercase hexdigits to lowercase --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/p= hy-qcom-qusb2.c index c52655a383ce..2d8fe9bc40f9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -151,6 +151,21 @@ static const struct qusb2_phy_init_tbl ipq6018_init_tb= l[] =3D { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F), }; =20 +static const struct qusb2_phy_init_tbl ipq5424_init_tbl[] =3D { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x00), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc3), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), +}; + static const unsigned int ipq6018_regs_layout[] =3D { [QUSB2PHY_PLL_STATUS] =3D 0x38, [QUSB2PHY_PORT_TUNE1] =3D 0x80, @@ -331,6 +346,16 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg =3D { .autoresume_en =3D BIT(0), }; =20 +static const struct qusb2_phy_cfg ipq5424_phy_cfg =3D { + .tbl =3D ipq5424_init_tbl, + .tbl_num =3D ARRAY_SIZE(ipq5424_init_tbl), + .regs =3D ipq6018_regs_layout, + + .disable_ctrl =3D POWER_DOWN, + .mask_core_ready =3D PLL_LOCKED, + .autoresume_en =3D BIT(0), +}; + static const struct qusb2_phy_cfg qusb2_v2_phy_cfg =3D { .tbl =3D qusb2_v2_init_tbl, .tbl_num =3D ARRAY_SIZE(qusb2_v2_init_tbl), @@ -905,6 +930,9 @@ static const struct phy_ops qusb2_phy_gen_ops =3D { =20 static const struct of_device_id qusb2_phy_of_match_table[] =3D { { + .compatible =3D "qcom,ipq5424-qusb2-phy", + .data =3D &ipq5424_phy_cfg, + }, { .compatible =3D "qcom,ipq6018-qusb2-phy", .data =3D &ipq6018_phy_cfg, }, { --=20 2.34.1 From nobody Sat Nov 23 09:22:13 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F8E617B4E9; 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charset="utf-8" Add dt-bindings for USB3 PHY found on Qualcomm IPQ5424 Acked-by: Conor Dooley Signed-off-by: Varadarajan Narayanan --- v2: Add 'Acked-by: Conor Dooley' --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-u= ni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-= uni-phy.yaml index baf5134ea3d8..a1b55168e050 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.= yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.= yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,ipq5424-qmp-usb3-phy - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy @@ -89,6 +90,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5424-qmp-usb3-phy - qcom,ipq6018-qmp-usb3-phy - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy --=20 2.34.1 From nobody Sat Nov 23 09:22:13 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0878D188013; 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charset="utf-8" Enable QMP USB3 phy support for IPQ5424 SoC. Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- v2: Add 'Reviewed-by: Dmitry Baryshkov' --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm= /phy-qcom-qmp-usb.c index acd6075bf6d9..f43823539a3b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -2298,6 +2298,9 @@ static int qmp_usb_probe(struct platform_device *pdev) =20 static const struct of_device_id qmp_usb_of_match_table[] =3D { { + .compatible =3D "qcom,ipq5424-qmp-usb3-phy", + .data =3D &ipq9574_usb3phy_cfg, + }, { .compatible =3D "qcom,ipq6018-qmp-usb3-phy", .data =3D &ipq6018_usb3phy_cfg, }, { --=20 2.34.1 From nobody Sat Nov 23 09:22:13 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5DAF18A94C; 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charset="utf-8" Update dt-bindings to add IPQ5424 to USB DWC3 controller list. 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charset="utf-8" The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0 can connect to either of USB2.0 or USB3.0 phy and operate in the respective mode. Signed-off-by: Varadarajan Narayanan --- v2: Add dm/dp_hs_phy_irq to usb3@8a00000 node Add u1/u2-entry quirks to usb@8a00000 node --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 67 +++++++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 159 ++++++++++++++++++++ 2 files changed, 226 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index d4d31026a026..3d50a419139d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -16,12 +16,71 @@ / { aliases { serial0 =3D &uart1; }; + + regulator_fixed_3p3: s3300 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "fixed_3p3"; + }; + + regulator_fixed_1p8: s1800 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "fixed_1p8"; + }; + + regulator_fixed_0p925: s0925 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <925000>; + regulator-max-microvolt =3D <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "fixed_0p925"; + }; + +}; + +&dwc_0 { + dr_mode =3D "host"; +}; + +&dwc_1 { + dr_mode =3D "host"; +}; + +&qusb_phy_0 { + vdd-supply =3D <®ulator_fixed_0p925>; + vdda-pll-supply =3D <®ulator_fixed_1p8>; + vdda-phy-dpdm-supply =3D <®ulator_fixed_3p3>; + + status =3D "okay"; +}; + +&qusb_phy_1 { + vdd-supply =3D <®ulator_fixed_0p925>; + vdda-pll-supply =3D <®ulator_fixed_1p8>; + vdda-phy-dpdm-supply =3D <®ulator_fixed_3p3>; + + status =3D "okay"; }; =20 &sleep_clk { clock-frequency =3D <32000>; }; =20 +&ssphy_0 { + vdda-pll-supply =3D <®ulator_fixed_1p8>; + vdda-phy-supply =3D <®ulator_fixed_0p925>; + + status =3D "okay"; +}; + &tlmm { sdc_default_state: sdc-default-state { clk-pins { @@ -53,6 +112,14 @@ &uart1 { status =3D "okay"; }; =20 +&usb2 { + status =3D "okay"; +}; + +&usb3 { + status =3D "okay"; +}; + &xo_board { clock-frequency =3D <24000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 5e219f900412..f8afd6f0412d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -233,6 +233,165 @@ intc: interrupt-controller@f200000 { msi-controller; }; =20 + qusb_phy_1: phy@71000 { + compatible =3D "qcom,ipq5424-qusb2-phy"; + reg =3D <0 0x00071000 0 0x180>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names =3D "cfg_ahb", "ref"; + + resets =3D <&gcc GCC_QUSB2_1_PHY_BCR>; + status =3D "disabled"; + }; + + usb2: usb2@1e00000 { + compatible =3D "qcom,ipq5424-dwc3", "qcom,dwc3"; + reg =3D <0 0x01ef8800 0 0x400>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>, + <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&gcc GCC_CNOC_USB_CLK>; + + clock-names =3D "core", + "sleep", + "mock_utmi", + "iface", + "cfg_noc"; + + assigned-clocks =3D <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates =3D <200000000>, + <24000000>; + + interrupts-extended =3D <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "qusb2_phy", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + resets =3D <&gcc GCC_USB1_BCR>; + qcom,select-utmi-as-pipe-clk; + status =3D "disabled"; + + dwc_1: usb@1e00000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x01e00000 0 0xe000>; + clocks =3D <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names =3D "ref"; + interrupts =3D ; + phys =3D <&qusb_phy_1>; + phy-names =3D "usb2-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + + qusb_phy_0: phy@7b000 { + compatible =3D "qcom,ipq5424-qusb2-phy"; + reg =3D <0 0x0007b000 0 0x180>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names =3D "cfg_ahb", "ref"; + + resets =3D <&gcc GCC_QUSB2_0_PHY_BCR>; + status =3D "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible =3D "qcom,ipq5424-qmp-usb3-phy"; + reg =3D <0 0x0007d000 0 0xa00>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB0_AUX_CLK>, + <&xo_board>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names =3D "phy", + "phy_phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "usb0_pipe_clk"; + + status =3D "disabled"; + }; + + usb3: usb3@8a00000 { + compatible =3D "qcom,ipq5424-dwc3", "qcom,dwc3"; + reg =3D <0 0x08af8800 0 0x400>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clocks =3D <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_CNOC_USB_CLK>; + + clock-names =3D "core", + "sleep", + "mock_utmi", + "iface", + "cfg_noc"; + + assigned-clocks =3D <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates =3D <200000000>, + <24000000>; + + interrupts-extended =3D <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "qusb2_phy", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + resets =3D <&gcc GCC_USB_BCR>; + status =3D "disabled"; + + dwc_0: usb@8a00000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x08a00000 0 0xcd00>; + clocks =3D <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names =3D "ref"; + interrupts =3D ; + phys =3D <&qusb_phy_0>, <&ssphy_0>; + phy-names =3D "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + }; + }; + timer@f420000 { compatible =3D "arm,armv7-timer-mem"; reg =3D <0 0xf420000 0 0x1000>; --=20 2.34.1