From nobody Sat Nov 23 09:09:08 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C5AE208239; Wed, 13 Nov 2024 21:12:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731532348; cv=none; b=t19qdKUZAAtg/chmzZVxAdntxGKd2ZikQEStHwaBTPJ23tcCJfkDwA/roRR1h0XIL6ndp8Sg30nHF6pGCCo3yQfspWqCENwJPpIlnRgZTXE5rZ9BvewDpeasGFNb7ThHi9S2aiLOle4983ED1Y5x0/m3EIxmZteNBrtN2qn3/5o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731532348; c=relaxed/simple; bh=RcHLfgcSHz1AR6bIJm3t4pmOATMcmKjLpWbNz628tX0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Xhy0yTsrCxHwlAWYfS/C0OuDK6DaYWTxQFS39haqe8wNVI5Q4ykuz5ZNzERk5kNwE4EIrVx+Qo8N3Djp9wHDr4vy9Xy+FM99WHgcI8L57bsyUBhZjKyQy/C2+piMnbeuqx5U6Idln9XVBbKnLYu8a+rKcuOxFx7sJdFiyCps9uM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Qai+9EYe; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Qai+9EYe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1731532347; x=1763068347; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=RcHLfgcSHz1AR6bIJm3t4pmOATMcmKjLpWbNz628tX0=; b=Qai+9EYe8FzGbyuYX4TgHp94MqPYfDCOWe+mHSt/i1QqwMFuYX9Sgi1S PCwaWctq3nI7/79AmGObN9WqEYv+9UrapwGlXPMhapfz+/w0nSND0ir5j xhgBf8XYJX0NP8IgXsEibMbE3UkA4K2Dy+yVSkKEusVAVXLOSaqbF3lz/ 2EJ5tLcRhAT4AMKhJD8zNBRW+PK5DvVNv+0Nm7UY8eweQC0lDNbLlTMaS 7Kdm2hxcSW3cQOvAbAtVKoTNQNbczGC/7zxDwG+ozk5XZAKEXpMLZf4ah MRNW0NrZ9AljasxbaDI8Jm/gDHbWidmc8kYz1vM8hcWRxzqX/tpgOg482 Q==; X-CSE-ConnectionGUID: F8Mv1SaFTZWcTt5A65WwiA== X-CSE-MsgGUID: PlvVJhjRTS2zbkXVkrCmNw== X-IronPort-AV: E=Sophos;i="6.12,152,1728975600"; d="scan'208";a="34014109" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 13 Nov 2024 14:12:24 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 13 Nov 2024 14:11:50 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 13 Nov 2024 14:11:47 -0700 From: Daniel Machon Date: Wed, 13 Nov 2024 22:11:13 +0100 Subject: [PATCH net-next v2 5/8] net: sparx5: verify RGMII speeds Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-sparx5-lan969x-switch-driver-4-v2-5-0db98ac096d1@microchip.com> References: <20241113-sparx5-lan969x-switch-driver-4-v2-0-0db98ac096d1@microchip.com> In-Reply-To: <20241113-sparx5-lan969x-switch-driver-4-v2-0-0db98ac096d1@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , , , , CC: , , , X-Mailer: b4 0.14-dev When doing a port config, we verify the port speed against the PHY mode and supported speeds of that PHY mode. Add checks for the four RGMII phy modes: RGMII, RGMII_ID, RGMII_TXID and RGMII_RXID. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index b494970752fd..9f0f687bd994 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -257,6 +257,15 @@ static int sparx5_port_verify_speed(struct sparx5 *spa= rx5, conf->speed !=3D SPEED_25000)) return sparx5_port_error(port, conf, SPX5_PERR_SPEED); break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + if (conf->speed !=3D SPEED_1000 && + conf->speed !=3D SPEED_100 && + conf->speed !=3D SPEED_10) + return sparx5_port_error(port, conf, SPX5_PERR_SPEED); + break; default: return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); } --=20 2.34.1