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Wed, 13 Nov 2024 11:53:15 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADBrExI029812 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 11:53:14 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 03:53:07 -0800 From: Fange Zhang Date: Wed, 13 Nov 2024 19:51:46 +0800 Subject: [PATCH v2 4/9] drm/msm/dpu: Add QCS615 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-add-display-support-for-qcs615-platform-v2-4-2873eb6fb869@quicinc.com> References: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> In-Reply-To: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Catalin Marinas , Will Deacon , "Li Liu" , Fange Zhang , "Xiangxu Yin" CC: , , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731498758; l=10868; i=quic_fangez@quicinc.com; s=20241014; h=from:subject:message-id; bh=3PhDDeJCx8L0LA/r3qGqfz8D/v3KL5dKEOr/s+OT80I=; b=MstcRgx+CI2Gd+fs2koYaYdH5eRp0sEPk4qRP5dlJtUDqJf/VT3oHI2bI6cIiMtJReWw8ayJr 4+6P+BMKfecDlDYnr8kUkqecMlN4/n/N1xzNY4xQ1JjJ02KKTq6RRI+ X-Developer-Key: i=quic_fangez@quicinc.com; a=ed25519; pk=tJv8Cz0npA34ynt53o5GaQfBC0ySFhyb2FGj+V2Use4= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sd0ndqKTqQFEtKPqBOmWQ79q2Wq8AzO5 X-Proofpoint-ORIG-GUID: sd0ndqKTqQFEtKPqBOmWQ79q2Wq8AzO5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130102 From: Li Liu Add definitions for the display hardware used on the Qualcomm QCS615 platform. Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 263 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 266 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h new file mode 100644 index 0000000000000000000000000000000000000000..6ad9bb787c27a9bd5afba347810= 8f81c3ea34ca2 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DPU_5_3_QCS615_H +#define _DPU_5_3_QCS615_H + +static const struct dpu_caps qcs615_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x9, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg qcs615_mdp =3D { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x45c, + .features =3D 0, + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg qcs615_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x1800, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a00, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg qcs615_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x1f0, + .features =3D VIG_SDM845_MASK, + .sblk =3D &dpu_vig_sblk_qseed3_2_4, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x1f0, + .features =3D DMA_SDM845_MASK, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x1f0, + .features =3D DMA_SDM845_MASK, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA1, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x1f0, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA2, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x1f0, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA3, + }, +}; + +static const struct dpu_lm_cfg qcs615_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + .lm_pair =3D LM_1, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_1, + .lm_pair =3D LM_0, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_2, + }, +}; + +static const struct dpu_dspp_cfg qcs615_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg qcs615_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x70800, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x71000, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, +}; + +static const struct dpu_intf_cfg qcs615_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x6a000, .len =3D 0x280, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x2c0, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x6b000, .len =3D 0x2c0, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_NONE, + .controller_id =3D 0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x6b800, .len =3D 0x280, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg qcs615_perf_data =3D { + .max_bw_low =3D 4800000, + .max_bw_high =3D 4800000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 24, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfff8, 0xf000, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm8150_qos_linear), + .entries =3D sm8150_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version qcs615_mdss_ver =3D { + .core_major_ver =3D 5, + .core_minor_ver =3D 3, +}; + +const struct dpu_mdss_cfg dpu_qcs615_cfg =3D { + .mdss_ver =3D &qcs615_mdss_ver, + .caps =3D &qcs615_dpu_caps, + .mdp =3D &qcs615_mdp, + .ctl_count =3D ARRAY_SIZE(qcs615_ctl), + .ctl =3D qcs615_ctl, + .sspp_count =3D ARRAY_SIZE(qcs615_sspp), + .sspp =3D qcs615_sspp, + .mixer_count =3D ARRAY_SIZE(qcs615_lm), + .mixer =3D qcs615_lm, + .dspp_count =3D ARRAY_SIZE(qcs615_dspp), + .dspp =3D qcs615_dspp, + .pingpong_count =3D ARRAY_SIZE(qcs615_pp), + .pingpong =3D qcs615_pp, + .intf_count =3D ARRAY_SIZE(qcs615_intf), + .intf =3D qcs615_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .perf =3D &qcs615_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 2cbf41f33cc034fd3e649d1168ed65937e811d11..3fd6c5f3ca7c5f3a3cd98acd34d= 9a60c0f91b37f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -765,6 +765,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" #include "catalog/dpu_5_2_sm7150.h" +#include "catalog/dpu_5_3_qcs615.h" #include "catalog/dpu_5_4_sm6125.h" =20 #include "catalog/dpu_6_0_sm8250.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index c701d18c3522393b7d18d085d6554119f27f737b..c3b780405f3cb0882857ee9f79d= 93b8d5f74a383 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -841,6 +841,7 @@ extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6125_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_qcs615_cfg; extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index ca4847b2b73876c59dedff1e3ec4188ea70860a7..bc4a1ac61609cf19b456e2034b1= 2980c03f9a925 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1467,6 +1467,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,msm8996-mdp5", .data =3D &dpu_msm8996_cfg, }, { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, { .compatible =3D "qcom,qcm2290-dpu", .data =3D &dpu_qcm2290_cfg, }, + { .compatible =3D "qcom,qcs615-dpu", .data =3D &dpu_qcs615_cfg, }, { .compatible =3D "qcom,sa8775p-dpu", .data =3D &dpu_sa8775p_cfg, }, { .compatible =3D "qcom,sdm630-mdp5", .data =3D &dpu_sdm630_cfg, }, { .compatible =3D "qcom,sdm660-mdp5", .data =3D &dpu_sdm660_cfg, }, --=20 2.34.1