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Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yam= l b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index 52bbe132e6dae57246200757767edcd1c8ec2d77..babd73cdc44f6d12fdc59c6bef2= 7c544d91f1afa 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,dsi-phy-14nm - qcom,dsi-phy-14nm-2290 + - qcom,dsi-phy-14nm-615 - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 - qcom,sm6125-dsi-phy-14nm --=20 2.34.1 From nobody Sat Nov 23 08:34:05 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 679C8204947; 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Wed, 13 Nov 2024 11:53:01 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADBr0wI023407 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 11:53:00 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 03:52:53 -0800 From: Fange Zhang Date: Wed, 13 Nov 2024 19:51:44 +0800 Subject: [PATCH v2 2/9] dt-bindings: display/msm: dsi-controller-main: Document QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-add-display-support-for-qcs615-platform-v2-2-2873eb6fb869@quicinc.com> References: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> In-Reply-To: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Catalin Marinas , Will Deacon , "Li Liu" , Fange Zhang , "Xiangxu Yin" CC: , , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 1= + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index b0fd96b76ed1376e429a6168df7e7aaa7aeff2d3..b546d2cf2416fb10736765844dc= 9b5548e30c993 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -23,6 +23,7 @@ properties: - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,qcm2290-dsi-ctrl + - qcom,qcs615-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl --=20 2.34.1 From nobody Sat Nov 23 08:34:05 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8536E20513F; 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Wed, 13 Nov 2024 11:53:08 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADBr7pA018111 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 11:53:07 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 03:53:00 -0800 From: Fange Zhang Date: Wed, 13 Nov 2024 19:51:45 +0800 Subject: [PATCH v2 3/9] dt-bindings: display/msm: Add QCS615 MDSS & DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-add-display-support-for-qcs615-platform-v2-3-2873eb6fb869@quicinc.com> References: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> In-Reply-To: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Catalin Marinas , Will Deacon , "Li Liu" , Fange Zhang , "Xiangxu Yin" CC: , , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731498758; l=12306; i=quic_fangez@quicinc.com; s=20241014; h=from:subject:message-id; bh=X6B4j95tr8gTF/QUHCNWJJboMqoTYG+Ju6t2dxek4k4=; b=QBkve/XYTgxooDTejtCA6eLMk2OeH1W4VSXpfbb/rgoR5ZQh34VATJ5iLxi3oKQY3TlI9Z8wz BHKiruwg8g/DU/cPWb1bJs4ox37RaCHlpPsRDfOUJAyGmboDgXxQL12 X-Developer-Key: i=quic_fangez@quicinc.com; a=ed25519; pk=tJv8Cz0npA34ynt53o5GaQfBC0ySFhyb2FGj+V2Use4= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: yYNkTY9atZRP8Y5LN94lbk1GCROE3dPy X-Proofpoint-GUID: yYNkTY9atZRP8Y5LN94lbk1GCROE3dPy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130102 From: Li Liu Document the MDSS and DPU hardware found on the Qualcomm QCS615 platform. Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- .../bindings/display/msm/qcom,qcs615-dpu.yaml | 118 ++++++++++ .../bindings/display/msm/qcom,qcs615-mdss.yaml | 252 +++++++++++++++++= ++++ 2 files changed, 370 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1372760afd56393e3db2293d8c6= 2fc1c3ce97b66 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS615 Display DPU + +maintainers: + - Abhinav Kumar + - Dmitry Baryshkov + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,qcs615-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display hf axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible =3D "qcom,qcs615-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", "bus", "core", "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a76301d964a87379f7e80a93d3f= 9522b581274a0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml @@ -0,0 +1,252 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS615 Display MDSS + +maintainers: + - Abhinav Kumar + - Dmitry Baryshkov + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsu= lates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Devic= e tree + bindings of MDSS are mentioned for QCS615 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,qcs615-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,qcs615-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + items: + - const: qcom,qcs615-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,dsi-phy-14nm-615 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "qcom,qcs615-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 0 + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ON= LY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE= _ONLY>; + interconnect-names =3D "mdp0-mem", "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_CORE_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x0>; + + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,qcs615-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", "bus", "core", "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,qcs615-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy= 1>; + + operating-points-v2 =3D <&dsi0_opp_table>; + + phys =3D <&mdss_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; 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Wed, 13 Nov 2024 11:53:15 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADBrExI029812 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 11:53:14 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 03:53:07 -0800 From: Fange Zhang Date: Wed, 13 Nov 2024 19:51:46 +0800 Subject: [PATCH v2 4/9] drm/msm/dpu: Add QCS615 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-add-display-support-for-qcs615-platform-v2-4-2873eb6fb869@quicinc.com> References: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> In-Reply-To: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Catalin Marinas , Will Deacon , "Li Liu" , Fange Zhang , "Xiangxu Yin" CC: , , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 263 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 266 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h new file mode 100644 index 0000000000000000000000000000000000000000..6ad9bb787c27a9bd5afba347810= 8f81c3ea34ca2 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DPU_5_3_QCS615_H +#define _DPU_5_3_QCS615_H + +static const struct dpu_caps qcs615_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x9, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg qcs615_mdp =3D { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x45c, + .features =3D 0, + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg qcs615_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x1800, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a00, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg qcs615_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x1f0, + .features =3D VIG_SDM845_MASK, + .sblk =3D &dpu_vig_sblk_qseed3_2_4, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x1f0, + .features =3D DMA_SDM845_MASK, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x1f0, + .features =3D DMA_SDM845_MASK, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA1, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x1f0, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA2, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x1f0, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA3, + }, +}; + +static const struct dpu_lm_cfg qcs615_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + .lm_pair =3D LM_1, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_1, + .lm_pair =3D LM_0, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_2, + }, +}; + +static const struct dpu_dspp_cfg qcs615_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg qcs615_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x70800, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x71000, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, +}; + +static const struct dpu_intf_cfg qcs615_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x6a000, .len =3D 0x280, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x2c0, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x6b000, .len =3D 0x2c0, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_NONE, + .controller_id =3D 0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x6b800, .len =3D 0x280, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg qcs615_perf_data =3D { + .max_bw_low =3D 4800000, + .max_bw_high =3D 4800000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 24, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfff8, 0xf000, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm8150_qos_linear), + .entries =3D sm8150_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version qcs615_mdss_ver =3D { + .core_major_ver =3D 5, + .core_minor_ver =3D 3, +}; + +const struct dpu_mdss_cfg dpu_qcs615_cfg =3D { + .mdss_ver =3D &qcs615_mdss_ver, + .caps =3D &qcs615_dpu_caps, + .mdp =3D &qcs615_mdp, + .ctl_count =3D ARRAY_SIZE(qcs615_ctl), + .ctl =3D qcs615_ctl, + .sspp_count =3D ARRAY_SIZE(qcs615_sspp), + .sspp =3D qcs615_sspp, + .mixer_count =3D ARRAY_SIZE(qcs615_lm), + .mixer =3D qcs615_lm, + .dspp_count =3D ARRAY_SIZE(qcs615_dspp), + .dspp =3D qcs615_dspp, + .pingpong_count =3D ARRAY_SIZE(qcs615_pp), + .pingpong =3D qcs615_pp, + .intf_count =3D ARRAY_SIZE(qcs615_intf), + .intf =3D qcs615_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .perf =3D &qcs615_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 2cbf41f33cc034fd3e649d1168ed65937e811d11..3fd6c5f3ca7c5f3a3cd98acd34d= 9a60c0f91b37f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -765,6 +765,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" #include "catalog/dpu_5_2_sm7150.h" +#include "catalog/dpu_5_3_qcs615.h" #include "catalog/dpu_5_4_sm6125.h" =20 #include "catalog/dpu_6_0_sm8250.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index c701d18c3522393b7d18d085d6554119f27f737b..c3b780405f3cb0882857ee9f79d= 93b8d5f74a383 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -841,6 +841,7 @@ extern const struct dpu_mdss_cfg dpu_sm6115_cfg; extern const struct dpu_mdss_cfg dpu_sm6125_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_qcs615_cfg; extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index ca4847b2b73876c59dedff1e3ec4188ea70860a7..bc4a1ac61609cf19b456e2034b1= 2980c03f9a925 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1467,6 +1467,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,msm8996-mdp5", .data =3D &dpu_msm8996_cfg, }, { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, { .compatible =3D "qcom,qcm2290-dpu", .data =3D &dpu_qcm2290_cfg, }, + { .compatible =3D "qcom,qcs615-dpu", .data =3D &dpu_qcs615_cfg, }, { .compatible =3D "qcom,sa8775p-dpu", .data =3D &dpu_sa8775p_cfg, }, { .compatible =3D "qcom,sdm630-mdp5", .data =3D &dpu_sdm630_cfg, }, { .compatible =3D "qcom,sdm660-mdp5", .data =3D &dpu_sdm660_cfg, }, --=20 2.34.1 From nobody Sat Nov 23 08:34:05 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAD21200CB9; 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Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- drivers/gpu/drm/msm/msm_mdss.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index b7bd899ead44bf86998e7295bccb31a334fa6811..bdd90fc850158060ffa665322e8= b95ed41fd4d04 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -667,6 +667,12 @@ static const struct msm_mdss_data sm6125_data =3D { .highest_bank_bit =3D 1, }; =20 +static const struct msm_mdss_data qcs615_data =3D { + .ubwc_enc_version =3D UBWC_2_0, + .ubwc_dec_version =3D UBWC_2_0, + .highest_bank_bit =3D 1, +}; + static const struct msm_mdss_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, @@ -715,6 +721,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,mdss" }, { .compatible =3D "qcom,msm8998-mdss", .data =3D &msm8998_data }, { .compatible =3D "qcom,qcm2290-mdss", .data =3D &qcm2290_data }, + { .compatible =3D "qcom,qcs615-mdss", .data =3D &qcs615_data }, { .compatible =3D "qcom,sa8775p-mdss", .data =3D &sa8775p_data }, { .compatible =3D "qcom,sdm670-mdss", .data =3D &sdm670_data }, { .compatible =3D "qcom,sdm845-mdss", .data =3D &sdm845_data }, --=20 2.34.1 From nobody Sat Nov 23 08:34:05 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DF73206072; 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Wed, 13 Nov 2024 11:53:28 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADBrRpW030357 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 11:53:27 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 03:53:21 -0800 From: Fange Zhang Date: Wed, 13 Nov 2024 19:51:48 +0800 Subject: [PATCH v2 6/9] drm/msm/dsi: Add support for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-add-display-support-for-qcs615-platform-v2-6-2873eb6fb869@quicinc.com> References: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> In-Reply-To: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Catalin Marinas , Will Deacon , "Li Liu" , Fange Zhang , "Xiangxu Yin" CC: , , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Add phy configuration for QCS615 Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 +++++++++++++++++++++ 5 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index 10ba7d153d1cfc9015f527c911c4658558f6e29e..edbe50305d6e85fb615afa41f3b= 0db664d2f4413 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -221,6 +221,21 @@ static const struct msm_dsi_config sc7280_dsi_cfg =3D { }, }; =20 +static const struct regulator_bulk_data qcs615_dsi_regulators[] =3D { + { .supply =3D "vdda", .init_load_uA =3D 21800 }, +}; + +static const struct msm_dsi_config qcs615_dsi_cfg =3D { + .io_offset =3D DSI_6G_REG_SHIFT, + .regulator_data =3D qcs615_dsi_regulators, + .num_regulators =3D ARRAY_SIZE(qcs615_dsi_regulators), + .bus_clk_names =3D dsi_v2_4_clk_names, + .num_bus_clks =3D ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start =3D { + { 0xae94000 }, + }, +}; + static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops =3D { .link_clk_set_rate =3D dsi_link_clk_set_rate_v2, .link_clk_enable =3D dsi_link_clk_enable_v2, @@ -286,6 +301,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handler= s[] =3D { &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1, + &qcs615_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 4c9b4b37681b066dbbc34876c38d99deee24fc82..120cb65164c1ba1deb9acb513e5= f073bd560c496 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -23,6 +23,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000 #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001 #define MSM_DSI_6G_VER_MINOR_V2_3_0 0x20030000 +#define MSM_DSI_6G_VER_MINOR_V2_3_1 0x20030001 #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index dd58bc0a49eb5ca96370f7832d9251609ac0c552..bc38fcd28e6778f5676983b78f7= 635ce619cd758 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_14nm_cfgs }, { .compatible =3D "qcom,dsi-phy-14nm-2290", .data =3D &dsi_phy_14nm_2290_cfgs }, + { .compatible =3D "qcom,dsi-phy-14nm-615", + .data =3D &dsi_phy_14nm_615_cfgs }, { .compatible =3D "qcom,dsi-phy-14nm-660", .data =3D &dsi_phy_14nm_660_cfgs }, { .compatible =3D "qcom,dsi-phy-14nm-8953", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 4953459edd636363614ecad85654614fc95cfa1d..5a2654a2e2814d21d24d0e6bd1e= 7811e7b537dfa 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -46,6 +46,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfg= s; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_615_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/m= sm/dsi/phy/dsi_phy_14nm.c index 1723f0e4faa4e4fd612d66f9976e80e045eafcc8..42a1c76a25f54be4c8fa7999949= 01e7fd7cfb9d9 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm= _73p4mA_regulators[] =3D { { .supply =3D "vcca", .init_load_uA =3D 73400 }, }; =20 +static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] =3D= { + { .supply =3D "vdda", .init_load_uA =3D 36000 }, +}; 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Wed, 13 Nov 2024 11:53:35 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADBrY5e009616 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 11:53:34 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 03:53:27 -0800 From: Fange Zhang Date: Wed, 13 Nov 2024 19:51:49 +0800 Subject: [PATCH v2 7/9] arm64: dts: qcom: Add display support for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-add-display-support-for-qcs615-platform-v2-7-2873eb6fb869@quicinc.com> References: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> In-Reply-To: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Catalin Marinas , Will Deacon , "Li Liu" , Fange Zhang , "Xiangxu Yin" CC: , , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 186 +++++++++++++++++++++++++++++++= +++- 1 file changed, 185 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 57de1188ca2a34079578816c0c10825431d032bb..4e8ac24f84c8e1acdd357b25828= af9ed6766dcd0 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1184,12 +1185,195 @@ camcc: clock-controller@ad00000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,qcs615-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_CORE_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x800 0x0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,qcs615-dpu"; + reg =3D <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", "bus", "core", "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-164000000 { + opp-hz =3D /bits/ 64 <164000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-14nm-615"; + reg =3D <0 0x0ae94400 0 0x100>, + <0 0x0ae94500 0 0x300>, + <0 0x0ae94800 0 0x188>; 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Wed, 13 Nov 2024 11:53:42 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADBrf6H024860 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 11:53:41 GMT Received: from robotics-lnxbld017.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 03:53:34 -0800 From: Fange Zhang Date: Wed, 13 Nov 2024 19:51:50 +0800 Subject: [PATCH v2 8/9] arm64: dts: qcom: Add display support for QCS615 RIDE board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241113-add-display-support-for-qcs615-platform-v2-8-2873eb6fb869@quicinc.com> References: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> In-Reply-To: <20241113-add-display-support-for-qcs615-platform-v2-0-2873eb6fb869@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , "Bjorn Andersson" , Konrad Dybcio , Catalin Marinas , Will Deacon , "Li Liu" , Fange Zhang , "Xiangxu Yin" CC: , , , , , X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731498759; l=2941; i=quic_fangez@quicinc.com; s=20241014; h=from:subject:message-id; bh=Q8LiZhb/Ep/nJO5Y1DyMDYqgsfi76f6BBkbAUE5K5UM=; b=9pdLoyJ16hbwESroVM8oIGkXSblxtKo2DyQGcCymOT5Bk2gR62TqfAKpGig0w0pFH78s420qg 7fPfblIlKNqBfNqaPIONgiNmplUXoA607/Ny6kZ81/HhOB6jnWEO3t3 X-Developer-Key: i=quic_fangez@quicinc.com; a=ed25519; pk=tJv8Cz0npA34ynt53o5GaQfBC0ySFhyb2FGj+V2Use4= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: a8yQUXGi8b9-YeX12m6xZxLfLitS-NF_ X-Proofpoint-ORIG-GUID: a8yQUXGi8b9-YeX12m6xZxLfLitS-NF_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130102 From: Li Liu Add display MDSS and DSI configuration for QCS615. QCS615 has a DP port, and DP support will be added in a later patch. Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 109 +++++++++++++++++++++++++++= ++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index ee6cab3924a6d71f29934a8debba3a832882abdd..8b9029e96b07cbef950b074a741= 2180d6c27d39a 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -202,6 +202,115 @@ &gcc { <&sleep_clk>; }; =20 +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&qup_i2c2_data_clk &ioexp_intr_active &ioexp_reset_active>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ioexp: gpio@3e { + compatible =3D "semtech,sx1509q"; + reg =3D <0x3e>; + interrupt-parent =3D <&tlmm>; + interrupts =3D <58 0>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + semtech,probe-reset; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dsi_dp_hpd_cfg_pins &dsi_dp_cdet_cfg_pins>; + + // HPD configuration for DSI to DP port + dsi_dp_hpd_cfg_pins: gpio0-cfg { + pins =3D "gpio0"; + bias-pull-up; + }; + + // Connection detect configuration for DSI to DP port + dsi_dp_cdet_cfg_pins: gpio1-cfg { + pins =3D "gpio1"; + bias-pull-down; + }; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9542"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + anx7625@58 { + compatible =3D "analogix,anx7625"; + reg =3D <0x58>; + interrupt-parent =3D <&ioexp>; + interrupts =3D <0 0>; + enable-gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; + wakeup-source; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + anx_7625_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg =3D <1>; + anx_7625_out: endpoint { + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l11a>; + status =3D "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&anx_7625_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&tlmm { + ioexp_intr_active: ioexp_intr_active { + pins =3D "gpio58"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + ioexp_reset_active: ioexp_reset_active { + pins =3D "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; +}; + &qupv3_id_0 { status =3D "okay"; }; --=20 2.34.1 From nobody Sat Nov 23 08:34:05 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E9EE20720B; Wed, 13 Nov 2024 11:54:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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a=ed25519-sha256; t=1731498759; l=882; i=quic_fangez@quicinc.com; s=20241014; h=from:subject:message-id; bh=VdOs56Xri4piaaV5qvYXYFzwm73Lj5QH3tiEDao18/M=; b=wlpXoEu4wKIkhxBcrWWpR/RdPm3fWDxwmfrTM4lT4+DK724QYACs+P9RPgcE6zneC+oCIj+OB xtLungtJoemAHcG9P6xzGNtUXmXmQDvgmoc9UPaJ46xfXMacJynbmpS X-Developer-Key: i=quic_fangez@quicinc.com; a=ed25519; pk=tJv8Cz0npA34ynt53o5GaQfBC0ySFhyb2FGj+V2Use4= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Jiw4ogCKbljuSvUnktCEeVCnGHC9xLY1 X-Proofpoint-ORIG-GUID: Jiw4ogCKbljuSvUnktCEeVCnGHC9xLY1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=917 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130102 From: Li Liu For the QCS615 ride board, enable the SX150X to activate the ANX7625 allowing the DSI to output to the mDP through the external bridge. The ANX7625 relies on the SX150X chip to perform reset and HPD. Signed-off-by: Li Liu Signed-off-by: Fange Zhang --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c0b8482ac6ad7498487718ba01d11b1c95e7543d..599a339a19435efbee7a5ef80c0= 93b0e8c65f7ff 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -631,6 +631,7 @@ CONFIG_PINCTRL_SM8350=3Dy CONFIG_PINCTRL_SM8450=3Dy CONFIG_PINCTRL_SM8550=3Dy CONFIG_PINCTRL_SM8650=3Dy +CONFIG_PINCTRL_SX150X=3Dy CONFIG_PINCTRL_X1E80100=3Dy CONFIG_PINCTRL_QCOM_SPMI_PMIC=3Dy CONFIG_PINCTRL_LPASS_LPI=3Dm --=20 2.34.1