From nobody Sat Nov 23 11:42:32 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A70C185936; Wed, 13 Nov 2024 07:29:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731482982; cv=none; b=VStbESUMo4LMaLDvHGEJlnYpVqWhOpmAW9zVLpJIMIMGGZUExWMRuzBuYwr0j4IQNiQFGIdujYL+ofAQrDDSPt4ZAxOh1OxeMdiD9Qc6JD/5h1/kRIV5qziNCwE7Pi6H5ofVVXFabGTCpwCBNx8d1aJ2O+hbtZSqcXZ4+aOOyho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731482982; c=relaxed/simple; bh=+q9+kwHimxzdccFM9WHvZ5oVGBm30GmyyXsl5gTpFDA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XOu2SdV9NSj84w39WN3VpWTYEoPiNtmM9aVR2V0Gy15pfzoGW9P/xDoPdA1y+/MxP4ofo0WniQovifb5Bw0rTDzRnNx1ORgEcoQoHmCsVzxXpKImUYXIfaUX2AtA8Ff87LR5JlJ+tH+aAthP7nY4o0NEMZXcoLbarltJn3kVa3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ao00HGCL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ao00HGCL" Received: by smtp.kernel.org (Postfix) with ESMTPS id 188FAC4CED7; Wed, 13 Nov 2024 07:29:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731482982; bh=+q9+kwHimxzdccFM9WHvZ5oVGBm30GmyyXsl5gTpFDA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Ao00HGCL7zvsGbGfPUmnW1eYnHnHxiZWlzIcpjEtTC/VFHnsF9AiZIKu6+BnL3IGC 9E2WD/t50hdPCs0WgJHEtkPJzw6+yPXRc9TPNcebC7sFifWKQQ5hzhZYStjnbfvqHR PUI74iCDlnJzgNgr5FAABQat31200ii/TorEM92D+v7mKX86N+lWXw56hyxUnQMEWR 57jH5e4xotQnpmKtNzE6+PaEluOkPQPmiMynB8kjHaaAPSARiiZId9oGRsYM6EB7eW EyejNGquO6LAj0jsa44gRbanarge+6Jomhcu4Cu1gN9VxtWXkGbaRyECS7PI5wyVjV rwGaZCSrgCEMg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05D75D41C10; Wed, 13 Nov 2024 07:29:42 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 13 Nov 2024 15:29:40 +0800 Subject: [PATCH v6 2/5] dt-bindings: pinctrl: Add support for Amlogic A4 SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241113-a4_pinctrl-v6-2-35ba2401ee35@amlogic.com> References: <20241113-a4_pinctrl-v6-0-35ba2401ee35@amlogic.com> In-Reply-To: <20241113-a4_pinctrl-v6-0-35ba2401ee35@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731482979; l=4174; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=glcFuScc78HwQIkHOV1xZntvO1LAOj3S6vCcFCbIJOY=; b=XLFohjqOxL/BLnyUIu5hkiuw7YShB73oyeH0qjwS51fnIh+U/WuMv1MyPopz9NCvFVzL7x8Z0 GucXBLFcXP4BJ9kmvnSvP7FH9GYXvMBy6PilJ0fWsWXJ6Wx6AiUZr8O X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add the dt-bindings for Amlogic A4 pin controller, and add a new dt-binding header file which document the GPIO bank names of all Amlogic subsequent SoCs. Acked-by: Rob Herring (Arm) Signed-off-by: Xianwei Zhao --- .../bindings/pinctrl/amlogic,meson-pinctrl-a4.yaml | 80 ++++++++++++++++++= ++++ include/dt-bindings/gpio/amlogic-gpio.h | 45 ++++++++++++ 2 files changed, 125 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctr= l-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl= -a4.yaml new file mode 100644 index 000000000000..db1d58c29478 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a4.ya= ml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-a4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A4 pinmux controller + +maintainers: + - Neil Armstrong + - Xianwei Zhao + +allOf: + - $ref: amlogic,meson-pinctrl-common.yaml# + +properties: + compatible: + enum: + - amlogic,a4-aobus-pinctrl + - amlogic,a4-periphs-pinctrl + +required: + - compatible + +patternProperties: + "^bank@[0-9a-f]+$": + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio + + unevaluatedProperties: false + + properties: + reg: + maxItems: 2 + + reg-names: + items: + - const: mux + - const: gpio + + "#gpio-cells": + const: 3 + + gpio-line-names: + minItems: 8 + maxItems: 73 + +unevaluatedProperties: + type: object + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins + +examples: + - | + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + periphs_pinctrl: pinctrl@4000 { + compatible =3D "amlogic,a4-periphs-pinctrl"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x02e0>; + + bank@0 { + reg =3D <0x0 0x0 0x0 0x0050>, + <0x0 0xc0 0x0 0x0220>; + reg-names =3D "mux", "gpio"; + gpio-controller; + #gpio-cells =3D <3>; + gpio-ranges =3D <&periphs_pinctrl 0 0 73>; + }; + + cec_ao_a_h_pins: cec_ao_a_h { + mux { + groups =3D "cec_ao_a_h"; + function =3D "cec_ao_a_h"; + bias-disable; + }; + }; + }; + }; diff --git a/include/dt-bindings/gpio/amlogic-gpio.h b/include/dt-bindings/= gpio/amlogic-gpio.h new file mode 100644 index 000000000000..5bfdb39eeda8 --- /dev/null +++ b/include/dt-bindings/gpio/amlogic-gpio.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Xianwei Zhao + */ + +#ifndef _DT_BINDINGS_AMLOGIC_GPIO_H +#define _DT_BINDINGS_AMLOGIC_GPIO_H + +#include + +/* Normal GPIO bank */ +#define AMLOGIC_GPIO_A 0 +#define AMLOGIC_GPIO_B 1 +#define AMLOGIC_GPIO_C 2 +#define AMLOGIC_GPIO_D 3 +#define AMLOGIC_GPIO_E 4 +#define AMLOGIC_GPIO_F 5 +#define AMLOGIC_GPIO_G 6 +#define AMLOGIC_GPIO_H 7 +#define AMLOGIC_GPIO_I 8 +#define AMLOGIC_GPIO_J 9 +#define AMLOGIC_GPIO_K 10 +#define AMLOGIC_GPIO_L 11 +#define AMLOGIC_GPIO_M 12 +#define AMLOGIC_GPIO_N 13 +#define AMLOGIC_GPIO_O 14 +#define AMLOGIC_GPIO_P 15 +#define AMLOGIC_GPIO_Q 16 +#define AMLOGIC_GPIO_R 17 +#define AMLOGIC_GPIO_S 18 +#define AMLOGIC_GPIO_T 19 +#define AMLOGIC_GPIO_U 20 +#define AMLOGIC_GPIO_V 21 +#define AMLOGIC_GPIO_W 22 +#define AMLOGIC_GPIO_X 23 +#define AMLOGIC_GPIO_Y 24 +#define AMLOGIC_GPIO_Z 25 +/* Special GPIO bank */ +#define AMLOGIC_GPIO_DV 26 +#define AMLOGIC_GPIO_AO 27 +#define AMLOGIC_GPIO_CC 28 +#define AMLOGIC_GPIO_TEST_N 29 + +#endif /* _DT_BINDINGS_AMLOGIC_GPIO_H */ --=20 2.37.1