From nobody Sat Nov 23 15:41:24 2024 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36167205ABD; Tue, 12 Nov 2024 23:04:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.18.73.165 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731452693; cv=none; b=LFDLT5K3s0suD1w3x+0zJhXw8Xtv9BSliPyIJKiGgGlBDdtknv8nF27iOMjp2M1Za+R+KjaInB9mR4WEI7wFidi4peAirm7ZuRxdSghsuFZyZ+lEjFZhZkglWdNjYnQ0bQq0vfDZZFY9qtWncm8l2q7Z7BynGHRBVy13lDWMzMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731452693; c=relaxed/simple; bh=/1nt4vdmI/2A6tTv7wnG63dLKS2s9qv1KhnYopqBRw8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PmWAGpf92qWxZdf5kT+Rm9EcYrSNWIduRtGjUe+CaOYGCznOwweRoJ6f3V4qohg0/Z7fHBOorwfHYtIQ+4l67Vn2gaRRc3NRVefsXiAlyF+RkzZJXJBJL7EaVxqwyDJvVGi5jyypTJSdHRTY6TT50mD0Xig6cmYZGax+YCbgFT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com; spf=pass smtp.mailfrom=sberdevices.ru; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b=UwgczBXa; arc=none smtp.client-ip=37.18.73.165 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sberdevices.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b="UwgczBXa" Received: from p-infra-ksmg-sc-msk01.sberdevices.ru (localhost [127.0.0.1]) by mx1.sberdevices.ru (Postfix) with ESMTP id 92807100011; Wed, 13 Nov 2024 02:04:49 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.sberdevices.ru 92807100011 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=salutedevices.com; s=mail; t=1731452689; bh=TTj1RmzlVnOO+4coRwrtQf70SLgxnfgPXQ0h1eNXtEM=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=UwgczBXawuwgNaqqPLfROm231dNZJvMTsUR0HYBoc93T9/fr/DJb9ZOxNHJ12aPyM HIF32nHHRrOxYGmE6ucWW0tA6lonzBg077thTybqWy0Z1B9Wl4Fwp/BgB33II2RzNC IR6GEc+Iki8jpPizjMtHJyDmI1+VAoGSTcAqhwHGenBFoMoIJIK8H6ys/a0x8NY0dd Mv5fC9IRvsq6SswurC4cU4PNT0+h6/Wo3NH873GUKxcDjhEgsIFTIxUpRct2i97qlA p0y23+4Z7pMVfROmZJ7MWg0wh5bJ5zLr9ge2VoAA/NmYFRZYsXUyCLBbPE3gH7fDno 8qZ7D6LnFqdtA== Received: from smtp.sberdevices.ru (p-i-exch-sc-m02.sberdevices.ru [172.16.192.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.sberdevices.ru (Postfix) with ESMTPS; Wed, 13 Nov 2024 02:04:49 +0300 (MSK) From: Jan Dakinevich To: Jan Dakinevich , Conor Dooley , , Jerome Brunet , Kevin Hilman , "Krzysztof Kozlowski" , , , , , Martin Blumenstingl , Michael Turquette , Neil Armstrong , "Rob Herring" , Stephen Boyd Subject: [PATCH v5 1/3] clk: meson: axg: share the set of audio helper macros Date: Wed, 13 Nov 2024 02:04:41 +0300 Message-ID: <20241112230443.1406460-2-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> References: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189131 [Nov 12 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_smtp_not_equal_from}, 127.0.0.199:7.1.2;salutedevices.com:7.1.1;smtp.sberdevices.ru:7.1.1,5.0.1;sberdevices.ru:7.1.1,5.0.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, FromAlignment: n X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/12 21:10:00 #26864167 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" - These macros will be used in upcoming audio clock controller for A1 SoC; - AUD_PCLK_GATE() macro got an extra parameter to be more flexible. Signed-off-by: Jan Dakinevich --- drivers/clk/meson/axg-audio.c | 215 ++++++-------------------------- drivers/clk/meson/meson-audio.h | 156 +++++++++++++++++++++++ 2 files changed, 191 insertions(+), 180 deletions(-) create mode 100644 drivers/clk/meson/meson-audio.h diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 7714bde5ffc0..df6e355d3cef 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -18,6 +18,7 @@ #include =20 #include "meson-clkc-utils.h" +#include "meson-audio.h" #include "axg-audio.h" #include "clk-regmap.h" #include "clk-phase.h" @@ -25,155 +26,9 @@ =20 #include =20 -#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ - .data =3D &(struct clk_regmap_mux_data){ \ - .offset =3D (_reg), \ - .mask =3D (_mask), \ - .shift =3D (_shift), \ - .flags =3D (_dflags), \ - }, \ - .hw.init =3D &(struct clk_init_data){ \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_mux_ops, \ - .parent_data =3D _pdata, \ - .num_parents =3D ARRAY_SIZE(_pdata), \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ - .data =3D &(struct clk_regmap_div_data){ \ - .offset =3D (_reg), \ - .shift =3D (_shift), \ - .width =3D (_width), \ - .flags =3D (_dflags), \ - }, \ - .hw.init =3D &(struct clk_init_data){ \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_divider_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_PCLK_GATE(_name, _reg, _bit) { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]){ "aud_top" }, \ - .num_parents =3D 1, \ - }, \ -} - -#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ - _hi_shift, _hi_width, _pname, _iflags) { \ - .data =3D &(struct meson_sclk_div_data) { \ - .div =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_div_shift), \ - .width =3D (_div_width), \ - }, \ - .hi =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_hi_shift), \ - .width =3D (_hi_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_sclk_div_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ - _pname, _iflags) { \ - .data =3D &(struct meson_clk_triphase_data) { \ - .ph0 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift0), \ - .width =3D (_width), \ - }, \ - .ph1 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift1), \ - .width =3D (_width), \ - }, \ - .ph2 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift2), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_triphase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ - .data =3D &(struct meson_clk_phase_data) { \ - .ph =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_phase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ - _iflags) { \ - .data =3D &(struct meson_sclk_ws_inv_data) { \ - .ph =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift_ph), \ - .width =3D (_width), \ - }, \ - .ws =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift_ws), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_phase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} +static const struct clk_parent_data pclk_parent_data[] =3D { + { .name =3D "aud_top" }, +}; =20 /* Audio Master Clocks */ static const struct clk_parent_data mst_mux_parent_data[] =3D { @@ -327,45 +182,45 @@ static const struct clk_parent_data lrclk_pad_ctrl_pa= rent_data[] =3D { =20 /* Common Clocks */ static struct clk_regmap ddr_arb =3D - AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0); + AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0, pclk_parent_data); static struct clk_regmap pdm =3D - AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1); + AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1, pclk_parent_data); static struct clk_regmap tdmin_a =3D - AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2); + AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2, pclk_parent_data); static struct clk_regmap tdmin_b =3D - AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3); + AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3, pclk_parent_data); static struct clk_regmap tdmin_c =3D - AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4); + AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4, pclk_parent_data); static struct clk_regmap tdmin_lb =3D - AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5); + AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5, pclk_parent_data); static struct clk_regmap tdmout_a =3D - AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6); + AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6, pclk_parent_data); static struct clk_regmap tdmout_b =3D - AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7); + AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7, pclk_parent_data); static struct clk_regmap tdmout_c =3D - AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8); + AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8, pclk_parent_data); static struct clk_regmap frddr_a =3D - AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9); + AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9, pclk_parent_data); static struct clk_regmap frddr_b =3D - AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10); + AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10, pclk_parent_data); static struct clk_regmap frddr_c =3D - AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11); + AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11, pclk_parent_data); static struct clk_regmap toddr_a =3D - AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12); + AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12, pclk_parent_data); static struct clk_regmap toddr_b =3D - AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13); + AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13, pclk_parent_data); static struct clk_regmap toddr_c =3D - AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14); + AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14, pclk_parent_data); static struct clk_regmap loopback =3D - AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15); + AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15, pclk_parent_data); static struct clk_regmap spdifin =3D - AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16); + AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16, pclk_parent_data); static struct clk_regmap spdifout =3D - AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17); + AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17, pclk_parent_data); static struct clk_regmap resample =3D - AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18); + AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18, pclk_parent_data); static struct clk_regmap power_detect =3D - AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19); + AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19, pclk_parent_data); =20 static struct clk_regmap spdifout_clk_sel =3D AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); @@ -633,11 +488,11 @@ static struct clk_regmap g12a_tdmout_c_sclk =3D AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL); =20 static struct clk_regmap toram =3D - AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20); + AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20, pclk_parent_data); static struct clk_regmap spdifout_b =3D - AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21); + AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21, pclk_parent_data); static struct clk_regmap eqdrc =3D - AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22); + AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22, pclk_parent_data); =20 /* SM1 Clocks */ static struct clk_regmap sm1_clk81_en =3D { @@ -742,21 +597,21 @@ static struct clk_regmap sm1_aud_top =3D { }; =20 static struct clk_regmap resample_b =3D - AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26); + AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26, pclk_parent_data); static struct clk_regmap tovad =3D - AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27); + AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27, pclk_parent_data); static struct clk_regmap locker =3D - AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28); + AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28, pclk_parent_data); static struct clk_regmap spdifin_lb =3D - AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29); + AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29, pclk_parent_data); static struct clk_regmap frddr_d =3D - AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0); + AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0, pclk_parent_data); static struct clk_regmap toddr_d =3D - AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1); + AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1, pclk_parent_data); static struct clk_regmap loopback_b =3D - AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2); + AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2, pclk_parent_data); static struct clk_regmap earcrx =3D - AUD_PCLK_GATE(earcrx, AUDIO_CLK_GATE_EN1, 6); + AUD_PCLK_GATE(earcrx, AUDIO_CLK_GATE_EN1, 6, pclk_parent_data); =20 =20 static struct clk_regmap sm1_mst_a_mclk_sel =3D diff --git a/drivers/clk/meson/meson-audio.h b/drivers/clk/meson/meson-audi= o.h new file mode 100644 index 000000000000..16dd044d52bd --- /dev/null +++ b/drivers/clk/meson/meson-audio.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef __MESON_AUDIO_H__ +#define __MESON_AUDIO_H__ + +#define AUD_PCLK_GATE(_name, _reg, _bit, _pdata) { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_data =3D (_pdata), \ + .num_parents =3D 1, \ + }, \ +} + +#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ + .data =3D &(struct clk_regmap_mux_data){ \ + .offset =3D (_reg), \ + .mask =3D (_mask), \ + .shift =3D (_shift), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _pdata, \ + .num_parents =3D ARRAY_SIZE(_pdata), \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ + .data =3D &(struct clk_regmap_div_data){ \ + .offset =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ + _hi_shift, _hi_width, _pname, _iflags) { \ + .data =3D &(struct meson_sclk_div_data) { \ + .div =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_div_shift), \ + .width =3D (_div_width), \ + }, \ + .hi =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_hi_shift), \ + .width =3D (_hi_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_sclk_div_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ + _pname, _iflags) { \ + .data =3D &(struct meson_clk_triphase_data) { \ + .ph0 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift0), \ + .width =3D (_width), \ + }, \ + .ph1 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift1), \ + .width =3D (_width), \ + }, \ + .ph2 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift2), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_triphase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ + .data =3D &(struct meson_clk_phase_data) { \ + .ph =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_phase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ + _iflags) { \ + .data =3D &(struct meson_sclk_ws_inv_data) { \ + .ph =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift_ph), \ + .width =3D (_width), \ + }, \ + .ws =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift_ws), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_phase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#endif /* __MESON_AUDIO_H__ */ --=20 2.34.1