From nobody Sat Nov 23 12:36:42 2024 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36167205ABD; Tue, 12 Nov 2024 23:04:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.18.73.165 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731452693; cv=none; b=LFDLT5K3s0suD1w3x+0zJhXw8Xtv9BSliPyIJKiGgGlBDdtknv8nF27iOMjp2M1Za+R+KjaInB9mR4WEI7wFidi4peAirm7ZuRxdSghsuFZyZ+lEjFZhZkglWdNjYnQ0bQq0vfDZZFY9qtWncm8l2q7Z7BynGHRBVy13lDWMzMg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731452693; c=relaxed/simple; bh=/1nt4vdmI/2A6tTv7wnG63dLKS2s9qv1KhnYopqBRw8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PmWAGpf92qWxZdf5kT+Rm9EcYrSNWIduRtGjUe+CaOYGCznOwweRoJ6f3V4qohg0/Z7fHBOorwfHYtIQ+4l67Vn2gaRRc3NRVefsXiAlyF+RkzZJXJBJL7EaVxqwyDJvVGi5jyypTJSdHRTY6TT50mD0Xig6cmYZGax+YCbgFT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com; spf=pass smtp.mailfrom=sberdevices.ru; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b=UwgczBXa; arc=none smtp.client-ip=37.18.73.165 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sberdevices.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b="UwgczBXa" Received: from p-infra-ksmg-sc-msk01.sberdevices.ru (localhost [127.0.0.1]) by mx1.sberdevices.ru (Postfix) with ESMTP id 92807100011; Wed, 13 Nov 2024 02:04:49 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.sberdevices.ru 92807100011 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=salutedevices.com; s=mail; t=1731452689; bh=TTj1RmzlVnOO+4coRwrtQf70SLgxnfgPXQ0h1eNXtEM=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=UwgczBXawuwgNaqqPLfROm231dNZJvMTsUR0HYBoc93T9/fr/DJb9ZOxNHJ12aPyM HIF32nHHRrOxYGmE6ucWW0tA6lonzBg077thTybqWy0Z1B9Wl4Fwp/BgB33II2RzNC IR6GEc+Iki8jpPizjMtHJyDmI1+VAoGSTcAqhwHGenBFoMoIJIK8H6ys/a0x8NY0dd Mv5fC9IRvsq6SswurC4cU4PNT0+h6/Wo3NH873GUKxcDjhEgsIFTIxUpRct2i97qlA p0y23+4Z7pMVfROmZJ7MWg0wh5bJ5zLr9ge2VoAA/NmYFRZYsXUyCLBbPE3gH7fDno 8qZ7D6LnFqdtA== Received: from smtp.sberdevices.ru (p-i-exch-sc-m02.sberdevices.ru [172.16.192.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.sberdevices.ru (Postfix) with ESMTPS; Wed, 13 Nov 2024 02:04:49 +0300 (MSK) From: Jan Dakinevich To: Jan Dakinevich , Conor Dooley , , Jerome Brunet , Kevin Hilman , "Krzysztof Kozlowski" , , , , , Martin Blumenstingl , Michael Turquette , Neil Armstrong , "Rob Herring" , Stephen Boyd Subject: [PATCH v5 1/3] clk: meson: axg: share the set of audio helper macros Date: Wed, 13 Nov 2024 02:04:41 +0300 Message-ID: <20241112230443.1406460-2-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> References: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189131 [Nov 12 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_smtp_not_equal_from}, 127.0.0.199:7.1.2;salutedevices.com:7.1.1;smtp.sberdevices.ru:7.1.1,5.0.1;sberdevices.ru:7.1.1,5.0.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, FromAlignment: n X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/12 21:10:00 #26864167 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" - These macros will be used in upcoming audio clock controller for A1 SoC; - AUD_PCLK_GATE() macro got an extra parameter to be more flexible. Signed-off-by: Jan Dakinevich --- drivers/clk/meson/axg-audio.c | 215 ++++++-------------------------- drivers/clk/meson/meson-audio.h | 156 +++++++++++++++++++++++ 2 files changed, 191 insertions(+), 180 deletions(-) create mode 100644 drivers/clk/meson/meson-audio.h diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 7714bde5ffc0..df6e355d3cef 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -18,6 +18,7 @@ #include =20 #include "meson-clkc-utils.h" +#include "meson-audio.h" #include "axg-audio.h" #include "clk-regmap.h" #include "clk-phase.h" @@ -25,155 +26,9 @@ =20 #include =20 -#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ - .data =3D &(struct clk_regmap_mux_data){ \ - .offset =3D (_reg), \ - .mask =3D (_mask), \ - .shift =3D (_shift), \ - .flags =3D (_dflags), \ - }, \ - .hw.init =3D &(struct clk_init_data){ \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_mux_ops, \ - .parent_data =3D _pdata, \ - .num_parents =3D ARRAY_SIZE(_pdata), \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ - .data =3D &(struct clk_regmap_div_data){ \ - .offset =3D (_reg), \ - .shift =3D (_shift), \ - .width =3D (_width), \ - .flags =3D (_dflags), \ - }, \ - .hw.init =3D &(struct clk_init_data){ \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_divider_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_PCLK_GATE(_name, _reg, _bit) { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]){ "aud_top" }, \ - .num_parents =3D 1, \ - }, \ -} - -#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ - _hi_shift, _hi_width, _pname, _iflags) { \ - .data =3D &(struct meson_sclk_div_data) { \ - .div =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_div_shift), \ - .width =3D (_div_width), \ - }, \ - .hi =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_hi_shift), \ - .width =3D (_hi_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_sclk_div_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ - _pname, _iflags) { \ - .data =3D &(struct meson_clk_triphase_data) { \ - .ph0 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift0), \ - .width =3D (_width), \ - }, \ - .ph1 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift1), \ - .width =3D (_width), \ - }, \ - .ph2 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift2), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_triphase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ - .data =3D &(struct meson_clk_phase_data) { \ - .ph =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_phase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ - _iflags) { \ - .data =3D &(struct meson_sclk_ws_inv_data) { \ - .ph =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift_ph), \ - .width =3D (_width), \ - }, \ - .ws =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift_ws), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_phase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} +static const struct clk_parent_data pclk_parent_data[] =3D { + { .name =3D "aud_top" }, +}; =20 /* Audio Master Clocks */ static const struct clk_parent_data mst_mux_parent_data[] =3D { @@ -327,45 +182,45 @@ static const struct clk_parent_data lrclk_pad_ctrl_pa= rent_data[] =3D { =20 /* Common Clocks */ static struct clk_regmap ddr_arb =3D - AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0); + AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0, pclk_parent_data); static struct clk_regmap pdm =3D - AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1); + AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1, pclk_parent_data); static struct clk_regmap tdmin_a =3D - AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2); + AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2, pclk_parent_data); static struct clk_regmap tdmin_b =3D - AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3); + AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3, pclk_parent_data); static struct clk_regmap tdmin_c =3D - AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4); + AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4, pclk_parent_data); static struct clk_regmap tdmin_lb =3D - AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5); + AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5, pclk_parent_data); static struct clk_regmap tdmout_a =3D - AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6); + AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6, pclk_parent_data); static struct clk_regmap tdmout_b =3D - AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7); + AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7, pclk_parent_data); static struct clk_regmap tdmout_c =3D - AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8); + AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8, pclk_parent_data); static struct clk_regmap frddr_a =3D - AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9); + AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9, pclk_parent_data); static struct clk_regmap frddr_b =3D - AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10); + AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10, pclk_parent_data); static struct clk_regmap frddr_c =3D - AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11); + AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11, pclk_parent_data); static struct clk_regmap toddr_a =3D - AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12); + AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12, pclk_parent_data); static struct clk_regmap toddr_b =3D - AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13); + AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13, pclk_parent_data); static struct clk_regmap toddr_c =3D - AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14); + AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14, pclk_parent_data); static struct clk_regmap loopback =3D - AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15); + AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15, pclk_parent_data); static struct clk_regmap spdifin =3D - AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16); + AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16, pclk_parent_data); static struct clk_regmap spdifout =3D - AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17); + AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17, pclk_parent_data); static struct clk_regmap resample =3D - AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18); + AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18, pclk_parent_data); static struct clk_regmap power_detect =3D - AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19); + AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19, pclk_parent_data); =20 static struct clk_regmap spdifout_clk_sel =3D AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); @@ -633,11 +488,11 @@ static struct clk_regmap g12a_tdmout_c_sclk =3D AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL); =20 static struct clk_regmap toram =3D - AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20); + AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20, pclk_parent_data); static struct clk_regmap spdifout_b =3D - AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21); + AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21, pclk_parent_data); static struct clk_regmap eqdrc =3D - AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22); + AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22, pclk_parent_data); =20 /* SM1 Clocks */ static struct clk_regmap sm1_clk81_en =3D { @@ -742,21 +597,21 @@ static struct clk_regmap sm1_aud_top =3D { }; =20 static struct clk_regmap resample_b =3D - AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26); + AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26, pclk_parent_data); static struct clk_regmap tovad =3D - AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27); + AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27, pclk_parent_data); static struct clk_regmap locker =3D - AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28); + AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28, pclk_parent_data); static struct clk_regmap spdifin_lb =3D - AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29); + AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29, pclk_parent_data); static struct clk_regmap frddr_d =3D - AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0); + AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0, pclk_parent_data); static struct clk_regmap toddr_d =3D - AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1); + AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1, pclk_parent_data); static struct clk_regmap loopback_b =3D - AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2); + AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2, pclk_parent_data); static struct clk_regmap earcrx =3D - AUD_PCLK_GATE(earcrx, AUDIO_CLK_GATE_EN1, 6); + AUD_PCLK_GATE(earcrx, AUDIO_CLK_GATE_EN1, 6, pclk_parent_data); =20 =20 static struct clk_regmap sm1_mst_a_mclk_sel =3D diff --git a/drivers/clk/meson/meson-audio.h b/drivers/clk/meson/meson-audi= o.h new file mode 100644 index 000000000000..16dd044d52bd --- /dev/null +++ b/drivers/clk/meson/meson-audio.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef __MESON_AUDIO_H__ +#define __MESON_AUDIO_H__ + +#define AUD_PCLK_GATE(_name, _reg, _bit, _pdata) { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_data =3D (_pdata), \ + .num_parents =3D 1, \ + }, \ +} + +#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ + .data =3D &(struct clk_regmap_mux_data){ \ + .offset =3D (_reg), \ + .mask =3D (_mask), \ + .shift =3D (_shift), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _pdata, \ + .num_parents =3D ARRAY_SIZE(_pdata), \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ + .data =3D &(struct clk_regmap_div_data){ \ + .offset =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ + _hi_shift, _hi_width, _pname, _iflags) { \ + .data =3D &(struct meson_sclk_div_data) { \ + .div =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_div_shift), \ + .width =3D (_div_width), \ + }, \ + .hi =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_hi_shift), \ + .width =3D (_hi_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_sclk_div_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ + _pname, _iflags) { \ + .data =3D &(struct meson_clk_triphase_data) { \ + .ph0 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift0), \ + .width =3D (_width), \ + }, \ + .ph1 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift1), \ + .width =3D (_width), \ + }, \ + .ph2 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift2), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_triphase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ + .data =3D &(struct meson_clk_phase_data) { \ + .ph =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_phase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ + _iflags) { \ + .data =3D &(struct meson_sclk_ws_inv_data) { \ + .ph =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift_ph), \ + .width =3D (_width), \ + }, \ + .ws =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift_ws), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_phase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#endif /* __MESON_AUDIO_H__ */ --=20 2.34.1 From nobody Sat Nov 23 12:36:42 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C91C8219C8A; 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Wed, 13 Nov 2024 02:04:49 +0300 (MSK) From: Jan Dakinevich To: Jan Dakinevich , Conor Dooley , , Jerome Brunet , Kevin Hilman , "Krzysztof Kozlowski" , , , , , Martin Blumenstingl , Michael Turquette , Neil Armstrong , "Rob Herring" , Stephen Boyd Subject: [PATCH v5 2/3] dt-bindings: clock: axg-audio: document A1 SoC audio clock controller driver Date: Wed, 13 Nov 2024 02:04:42 +0300 Message-ID: <20241112230443.1406460-3-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> References: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189131 [Nov 12 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_smtp_not_equal_from}, salutedevices.com:7.1.1;127.0.0.199:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;sberdevices.ru:7.1.1,5.0.1, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, FromAlignment: n X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/12 21:10:00 #26864167 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" Add device tree bindings for A1 SoC audio clock and reset controllers. Signed-off-by: Jan Dakinevich Acked-by: Conor Dooley --- .../clock/amlogic,axg-audio-clkc.yaml | 4 + .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 139 ++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc= .yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml index fd7982dd4cea..10202b749001 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml @@ -18,6 +18,8 @@ description: properties: compatible: enum: + - amlogic,a1-audio-clkc + - amlogic,a1-audio-vad-clkc - amlogic,axg-audio-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc @@ -114,6 +116,8 @@ allOf: compatible: contains: enum: + - amlogic,a1-audio-clkc + - amlogic,a1-audio-vad-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc then: diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt= -bindings/clock/amlogic,a1-audio-clkc.h new file mode 100644 index 000000000000..78e7a432d439 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#ifndef __A1_AUDIO_CLKC_BINDINGS_H +#define __A1_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_DDR_ARB 1 +#define AUD_CLKID_TDMIN_A 2 +#define AUD_CLKID_TDMIN_B 3 +#define AUD_CLKID_TDMIN_LB 4 +#define AUD_CLKID_LOOPBACK 5 +#define AUD_CLKID_TDMOUT_A 6 +#define AUD_CLKID_TDMOUT_B 7 +#define AUD_CLKID_FRDDR_A 8 +#define AUD_CLKID_FRDDR_B 9 +#define AUD_CLKID_TODDR_A 10 +#define AUD_CLKID_TODDR_B 11 +#define AUD_CLKID_SPDIFIN 12 +#define AUD_CLKID_RESAMPLE 13 +#define AUD_CLKID_EQDRC 14 +#define AUD_CLKID_LOCKER 15 +#define AUD_CLKID_MST_A_MCLK_SEL 16 +#define AUD_CLKID_MST_A_MCLK_DIV 17 +#define AUD_CLKID_MST_A_MCLK 18 +#define AUD_CLKID_MST_B_MCLK_SEL 19 +#define AUD_CLKID_MST_B_MCLK_DIV 20 +#define AUD_CLKID_MST_B_MCLK 21 +#define AUD_CLKID_MST_C_MCLK_SEL 22 +#define AUD_CLKID_MST_C_MCLK_DIV 23 +#define AUD_CLKID_MST_C_MCLK 24 +#define AUD_CLKID_MST_D_MCLK_SEL 25 +#define AUD_CLKID_MST_D_MCLK_DIV 26 +#define AUD_CLKID_MST_D_MCLK 27 +#define AUD_CLKID_MST_A_SCLK_PRE_EN 28 +#define AUD_CLKID_MST_A_SCLK_DIV 29 +#define AUD_CLKID_MST_A_SCLK_POST_EN 30 +#define AUD_CLKID_MST_A_SCLK 31 +#define AUD_CLKID_MST_B_SCLK_PRE_EN 32 +#define AUD_CLKID_MST_B_SCLK_DIV 33 +#define AUD_CLKID_MST_B_SCLK_POST_EN 34 +#define AUD_CLKID_MST_B_SCLK 35 +#define AUD_CLKID_MST_C_SCLK_PRE_EN 36 +#define AUD_CLKID_MST_C_SCLK_DIV 37 +#define AUD_CLKID_MST_C_SCLK_POST_EN 38 +#define AUD_CLKID_MST_C_SCLK 39 +#define AUD_CLKID_MST_D_SCLK_PRE_EN 40 +#define AUD_CLKID_MST_D_SCLK_DIV 41 +#define AUD_CLKID_MST_D_SCLK_POST_EN 42 +#define AUD_CLKID_MST_D_SCLK 43 +#define AUD_CLKID_MST_A_LRCLK_DIV 44 +#define AUD_CLKID_MST_A_LRCLK 45 +#define AUD_CLKID_MST_B_LRCLK_DIV 46 +#define AUD_CLKID_MST_B_LRCLK 47 +#define AUD_CLKID_MST_C_LRCLK_DIV 48 +#define AUD_CLKID_MST_C_LRCLK 49 +#define AUD_CLKID_MST_D_LRCLK_DIV 50 +#define AUD_CLKID_MST_D_LRCLK 51 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 52 +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 53 +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 54 +#define AUD_CLKID_TDMIN_A_SCLK 55 +#define AUD_CLKID_TDMIN_A_LRCLK 56 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 57 +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 58 +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 59 +#define AUD_CLKID_TDMIN_B_SCLK 60 +#define AUD_CLKID_TDMIN_B_LRCLK 61 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 62 +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 63 +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 64 +#define AUD_CLKID_TDMIN_LB_SCLK 65 +#define AUD_CLKID_TDMIN_LB_LRCLK 66 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 67 +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 68 +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 69 +#define AUD_CLKID_TDMOUT_A_SCLK 70 +#define AUD_CLKID_TDMOUT_A_LRCLK 71 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 72 +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 73 +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 74 +#define AUD_CLKID_TDMOUT_B_SCLK 75 +#define AUD_CLKID_TDMOUT_B_LRCLK 76 +#define AUD_CLKID_SPDIFIN_CLK_SEL 77 +#define AUD_CLKID_SPDIFIN_CLK_DIV 78 +#define AUD_CLKID_SPDIFIN_CLK 79 +#define AUD_CLKID_RESAMPLE_CLK_SEL 80 +#define AUD_CLKID_RESAMPLE_CLK_DIV 81 +#define AUD_CLKID_RESAMPLE_CLK 82 +#define AUD_CLKID_EQDRC_CLK_SEL 83 +#define AUD_CLKID_EQDRC_CLK_DIV 84 +#define AUD_CLKID_EQDRC_CLK 85 +#define AUD_CLKID_LOCKER_IN_CLK_SEL 86 +#define AUD_CLKID_LOCKER_IN_CLK_DIV 87 +#define AUD_CLKID_LOCKER_IN_CLK 88 +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 89 +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 90 +#define AUD_CLKID_LOCKER_OUT_CLK 91 + +#define AUD_VAD_CLKID_CLK81 1 +#define AUD_VAD_CLKID_SYSCLK_A_DIV 2 +#define AUD_VAD_CLKID_SYSCLK_A 3 +#define AUD_VAD_CLKID_SYSCLK_B_DIV 4 +#define AUD_VAD_CLKID_SYSCLK_B 5 +#define AUD_VAD_CLKID_SYSCLK 6 +#define AUD_VAD_CLKID_DDR_ARB 7 +#define AUD_VAD_CLKID_PDM 8 +#define AUD_VAD_CLKID_TDMIN_VAD 9 +#define AUD_VAD_CLKID_TODDR_VAD 10 +#define AUD_VAD_CLKID_TOVAD 11 +#define AUD_VAD_CLKID_TOAUDIOTOP 12 +#define AUD_VAD_CLKID_MST_VAD_MCLK_SEL 13 +#define AUD_VAD_CLKID_MST_VAD_MCLK_DIV 14 +#define AUD_VAD_CLKID_MST_VAD_MCLK 15 +#define AUD_VAD_CLKID_MST_VAD_SCLK_PRE_EN 16 +#define AUD_VAD_CLKID_MST_VAD_SCLK_DIV 17 +#define AUD_VAD_CLKID_MST_VAD_SCLK_POST_EN 18 +#define AUD_VAD_CLKID_MST_VAD_SCLK 19 +#define AUD_VAD_CLKID_MST_VAD_LRCLK_DIV 20 +#define AUD_VAD_CLKID_MST_VAD_LRCLK 21 +#define AUD_VAD_CLKID_TDMIN_VAD_SCLK_SEL 22 +#define AUD_VAD_CLKID_TDMIN_VAD_SCLK_PRE_EN 23 +#define AUD_VAD_CLKID_TDMIN_VAD_SCLK_POST_EN 24 +#define AUD_VAD_CLKID_TDMIN_VAD_SCLK 25 +#define AUD_VAD_CLKID_TDMIN_VAD_LRCLK 26 +#define AUD_VAD_CLKID_PDM_DCLK_SEL 27 +#define AUD_VAD_CLKID_PDM_DCLK_DIV 28 +#define AUD_VAD_CLKID_PDM_DCLK 29 +#define AUD_VAD_CLKID_PDM_SYSCLK_SEL 30 +#define AUD_VAD_CLKID_PDM_SYSCLK_DIV 31 +#define AUD_VAD_CLKID_PDM_SYSCLK 32 +#define AUD_VAD_CLKID_VAD_CLK_SEL 33 +#define AUD_VAD_CLKID_VAD_CLK_DIV 34 +#define AUD_VAD_CLKID_VAD_CLK 35 + +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */ --=20 2.34.1 From nobody Sat Nov 23 12:36:42 2024 Received: from mx1.sberdevices.ru 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"Krzysztof Kozlowski" , , , , , Martin Blumenstingl , Michael Turquette , Neil Armstrong , "Rob Herring" , Stephen Boyd Subject: [PATCH v5 3/3] clk: meson: a1: add the audio clock controller driver Date: Wed, 13 Nov 2024 02:04:43 +0300 Message-ID: <20241112230443.1406460-4-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> References: <20241112230443.1406460-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189131 [Nov 12 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_smtp_not_equal_from}, salutedevices.com:7.1.1;127.0.0.199:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;sberdevices.ru:7.1.1,5.0.1, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, FromAlignment: n X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/12 21:10:00 #26864167 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" This controller provides clocks and reset functionality for audio peripherals on Amlogic A1 SoC family. The driver is almost identical to 'axg-audio', however it would be better to keep it separate to avoid a mess of new defines with A1_ prefixes (significant amount of bits has another definition comparing to AXG/SM1/G12A). Signed-off-by: Jan Dakinevich --- drivers/clk/meson/Kconfig | 14 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-audio.c | 841 +++++++++++++++++++++++++++++++++++ 3 files changed, 856 insertions(+) create mode 100644 drivers/clk/meson/a1-audio.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 7cb21fc223b0..49f2086bc773 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -133,6 +133,20 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_A1_AUDIO + tristate "Amlogic A1 SoC Audio clock controller support" + depends on ARM64 + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PHASE + select COMMON_CLK_MESON_SCLK_DIV + select COMMON_CLK_MESON_CLKC_UTILS + select REGMAP_MMIO + imply RESET_MESON_AUX + help + Support for the Audio clock controller on Amlogic A113L based + device, A1 SoC Family. Say Y if you want A1 Audio clock controller + to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index bc56a47931c1..f3d8f6545f59 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_A1_AUDIO) +=3D a1-audio.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a1-audio.c b/drivers/clk/meson/a1-audio.c new file mode 100644 index 000000000000..06ec7d4ed50e --- /dev/null +++ b/drivers/clk/meson/a1-audio.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "clk-phase.h" +#include "clk-regmap.h" +#include "meson-audio.h" +#include "meson-clkc-utils.h" +#include "sclk-div.h" + +#define AUDIO_CLK_GATE_EN0 0x000 +#define AUDIO_MCLK_A_CTRL 0x008 +#define AUDIO_MCLK_B_CTRL 0x00c +#define AUDIO_MCLK_C_CTRL 0x010 +#define AUDIO_MCLK_D_CTRL 0x014 +#define AUDIO_SW_RESET0 0x028 +#define AUDIO_MST_A_SCLK_CTRL0 0x040 +#define AUDIO_MST_A_SCLK_CTRL1 0x044 +#define AUDIO_MST_B_SCLK_CTRL0 0x048 +#define AUDIO_MST_B_SCLK_CTRL1 0x04c +#define AUDIO_MST_C_SCLK_CTRL0 0x050 +#define AUDIO_MST_C_SCLK_CTRL1 0x054 +#define AUDIO_MST_D_SCLK_CTRL0 0x058 +#define AUDIO_MST_D_SCLK_CTRL1 0x05c +#define AUDIO_CLK_TDMIN_A_CTRL 0x080 +#define AUDIO_CLK_TDMIN_B_CTRL 0x084 +#define AUDIO_CLK_TDMIN_LB_CTRL 0x08c +#define AUDIO_CLK_TDMOUT_A_CTRL 0x090 +#define AUDIO_CLK_TDMOUT_B_CTRL 0x094 +#define AUDIO_CLK_SPDIFIN_CTRL 0x09c +#define AUDIO_CLK_RESAMPLEA_CTRL 0x0a4 +#define AUDIO_CLK_LOCKER_CTRL 0x0a8 +#define AUDIO_CLK_EQDRC_CTRL 0x0c0 + +#define AUDIO2_CLK81_CTRL 0x000 +#define AUDIO2_CLK81_EN 0x004 +#define AUDIO2_CLK_GATE_EN0 0x00c +#define AUDIO2_MCLK_VAD_CTRL 0x040 +#define AUDIO2_CLK_VAD_CTRL 0x044 +#define AUDIO2_MST_VAD_SCLK_CTRL0 0x04c +#define AUDIO2_MST_VAD_SCLK_CTRL1 0x050 +#define AUDIO2_CLK_TDMIN_VAD_CTRL 0x054 +#define AUDIO2_CLK_PDMIN_CTRL0 0x058 +#define AUDIO2_CLK_PDMIN_CTRL1 0x05c + +#define AUD_MST_MCLK_MUX(_name, _reg) \ + AUD_MUX(_name##_sel, (_reg), 0x7, 24, CLK_MUX_ROUND_CLOSEST, \ + a1_mst_pdata, 0) +#define AUD_MST_MCLK_DIV(_name, _reg) \ + AUD_DIV(_name##_div, (_reg), 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \ + aud_##_name##_sel, CLK_SET_RATE_PARENT) +#define AUD_MST_MCLK_GATE(_name, _reg) \ + AUD_GATE(_name, (_reg), 31, \ + aud_##_name##_div, CLK_SET_RATE_PARENT) + +#define AUD_MST_SCLK_PRE_EN(_name, _reg, _pname) \ + AUD_GATE(_name##_pre_en, (_reg), 31, \ + aud_##_pname, 0) +#define AUD_MST_SCLK_DIV(_name, _reg) \ + AUD_SCLK_DIV(_name##_div, (_reg), 20, 10, 0, 0, \ + aud_##_name##_pre_en, CLK_SET_RATE_PARENT) +#define AUD_MST_SCLK_POST_EN(_name, _reg) \ + AUD_GATE(_name##_post_en, (_reg), 30, \ + aud_##_name##_div, CLK_SET_RATE_PARENT) +#define AUD_MST_SCLK(_name, _reg) \ + AUD_TRIPHASE(_name, (_reg), 1, 0, 2, 4, \ + aud_##_name##_post_en, CLK_SET_RATE_PARENT) + +#define AUD_MST_LRCLK_DIV(_name, _reg, _pname) \ + AUD_SCLK_DIV(_name##_div, (_reg), 0, 10, 10, 10, \ + aud_##_pname, 0) +#define AUD_MST_LRCLK(_name, _reg) \ + AUD_TRIPHASE(_name, (_reg), 1, 1, 3, 5, \ + aud_##_name##_div, CLK_SET_RATE_PARENT) + +#define AUD_TDM_SCLK_MUX(_name, _reg, _pdata) \ + AUD_MUX(_name##_sel, (_reg), 0xf, 24, CLK_MUX_ROUND_CLOSEST, \ + (_pdata), 0) +#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ + AUD_GATE(_name##_pre_en, (_reg), 31, \ + aud_##_name##_sel, CLK_SET_RATE_PARENT) +#define AUD_TDM_SCLK_POST_EN(_name, _reg) \ + AUD_GATE(_name##_post_en, (_reg), 30, \ + aud_##_name##_pre_en, CLK_SET_RATE_PARENT) +#define AUD_TDM_SCLK(_name, _reg) \ + AUD_PHASE(_name, (_reg), 1, 29, \ + aud_##_name##_post_en, \ + CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT) +#define AUD_TDM_SCLK_WS(_name, _reg) \ + AUD_SCLK_WS(_name, (_reg), 1, 29, 28, \ + aud_##_name##_post_en, \ + CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT) + +#define AUD_TDM_LRLCK(_name, _reg, _pdata) \ + AUD_MUX(_name, (_reg), 0xf, 20, CLK_MUX_ROUND_CLOSEST, \ + (_pdata), CLK_SET_RATE_PARENT) + +static const struct clk_parent_data a1_mst_pdata[] =3D { + { .fw_name =3D "mst_in0" }, + { .fw_name =3D "mst_in1" }, + { .fw_name =3D "mst_in2" }, + { .fw_name =3D "mst_in3" }, + { .fw_name =3D "mst_in4" }, +}; + +static const struct clk_parent_data aud_pclk_pdata[] =3D { + { .fw_name =3D "pclk" }, +}; + +struct clk_regmap aud_ddr_arb =3D + AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN0, 0, aud_pclk_pdata); +struct clk_regmap aud_tdmin_a =3D + AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN0, 1, aud_pclk_pdata); +struct clk_regmap aud_tdmin_b =3D + AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN0, 2, aud_pclk_pdata); +struct clk_regmap aud_tdmin_lb =3D + AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN0, 3, aud_pclk_pdata); +struct clk_regmap aud_loopback =3D + AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN0, 4, aud_pclk_pdata); +struct clk_regmap aud_tdmout_a =3D + AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN0, 5, aud_pclk_pdata); +struct clk_regmap aud_tdmout_b =3D + AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN0, 6, aud_pclk_pdata); +struct clk_regmap aud_frddr_a =3D + AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN0, 7, aud_pclk_pdata); +struct clk_regmap aud_frddr_b =3D + AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN0, 8, aud_pclk_pdata); +struct clk_regmap aud_toddr_a =3D + AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN0, 9, aud_pclk_pdata); +struct clk_regmap aud_toddr_b =3D + AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN0, 10, aud_pclk_pdata); +struct clk_regmap aud_spdifin =3D + AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN0, 11, aud_pclk_pdata); +struct clk_regmap aud_resample =3D + AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN0, 12, aud_pclk_pdata); +struct clk_regmap aud_eqdrc =3D + AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN0, 13, aud_pclk_pdata); +struct clk_regmap aud_audiolocker =3D + AUD_PCLK_GATE(audiolocker, AUDIO_CLK_GATE_EN0, 14, aud_pclk_pdata); + +struct clk_regmap aud_mst_a_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); +struct clk_regmap aud_mst_a_mclk_div =3D + AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); +struct clk_regmap aud_mst_a_mclk =3D + AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); + +struct clk_regmap aud_mst_b_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); +struct clk_regmap aud_mst_b_mclk_div =3D + AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); +struct clk_regmap aud_mst_b_mclk =3D + AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL); + +struct clk_regmap aud_mst_c_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); +struct clk_regmap aud_mst_c_mclk_div =3D + AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL); +struct clk_regmap aud_mst_c_mclk =3D + AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL); + +struct clk_regmap aud_mst_d_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); +struct clk_regmap aud_mst_d_mclk_div =3D + AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); +struct clk_regmap aud_mst_d_mclk =3D + AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL); + +struct clk_regmap aud_mst_a_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0, mst_a_mclk); +struct clk_regmap aud_mst_a_sclk_div =3D + AUD_MST_SCLK_DIV(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0); +struct clk_regmap aud_mst_a_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0); +struct clk_regmap aud_mst_a_sclk =3D + AUD_MST_SCLK(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL1); + +struct clk_regmap aud_mst_b_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0, mst_b_mclk); +struct clk_regmap aud_mst_b_sclk_div =3D + AUD_MST_SCLK_DIV(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0); +struct clk_regmap aud_mst_b_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0); +struct clk_regmap aud_mst_b_sclk =3D + AUD_MST_SCLK(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL1); + +struct clk_regmap aud_mst_c_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0, mst_c_mclk); +struct clk_regmap aud_mst_c_sclk_div =3D + AUD_MST_SCLK_DIV(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0); +struct clk_regmap aud_mst_c_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0); +struct clk_regmap aud_mst_c_sclk =3D + AUD_MST_SCLK(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL1); + +struct clk_regmap aud_mst_d_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0, mst_d_mclk); +struct clk_regmap aud_mst_d_sclk_div =3D + AUD_MST_SCLK_DIV(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0); +struct clk_regmap aud_mst_d_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0); +struct clk_regmap aud_mst_d_sclk =3D + AUD_MST_SCLK(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL1); + +struct clk_regmap aud_mst_a_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL0, + mst_a_sclk_post_en); +struct clk_regmap aud_mst_a_lrclk =3D + AUD_MST_LRCLK(mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL1); + +struct clk_regmap aud_mst_b_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL0, + mst_b_sclk_post_en); +struct clk_regmap aud_mst_b_lrclk =3D + AUD_MST_LRCLK(mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL1); + +struct clk_regmap aud_mst_c_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL0, + mst_c_sclk_post_en); +struct clk_regmap aud_mst_c_lrclk =3D + AUD_MST_LRCLK(mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL1); + +struct clk_regmap aud_mst_d_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL0, + mst_d_sclk_post_en); +struct clk_regmap aud_mst_d_lrclk =3D + AUD_MST_LRCLK(mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL1); + +static const struct clk_parent_data aud_mst_sclk_pdata[] =3D { + { .hw =3D &aud_mst_a_sclk.hw, .index =3D -1 }, + { .hw =3D &aud_mst_b_sclk.hw, .index =3D -1 }, + { .hw =3D &aud_mst_c_sclk.hw, .index =3D -1 }, + { .hw =3D &aud_mst_d_sclk.hw, .index =3D -1 }, + { }, + { }, + { .fw_name =3D "slv_sclk0" }, + { .fw_name =3D "slv_sclk1" }, + { .fw_name =3D "slv_sclk2" }, + { .fw_name =3D "slv_sclk3" }, + { .fw_name =3D "slv_sclk4" }, + { .fw_name =3D "slv_sclk5" }, + { .fw_name =3D "slv_sclk6" }, + { .fw_name =3D "slv_sclk7" }, + { .fw_name =3D "slv_sclk8" }, + { .fw_name =3D "slv_sclk9" }, +}; + +static const struct clk_parent_data aud_mst_lrclk_pdata[] =3D { + { .hw =3D &aud_mst_a_lrclk.hw, .index =3D -1 }, + { .hw =3D &aud_mst_b_lrclk.hw, .index =3D -1 }, + { .hw =3D &aud_mst_c_lrclk.hw, .index =3D -1 }, + { .hw =3D &aud_mst_d_lrclk.hw, .index =3D -1 }, + { }, + { }, + { .fw_name =3D "slv_lrclk0" }, + { .fw_name =3D "slv_lrclk1" }, + { .fw_name =3D "slv_lrclk2" }, + { .fw_name =3D "slv_lrclk3" }, + { .fw_name =3D "slv_lrclk4" }, + { .fw_name =3D "slv_lrclk5" }, + { .fw_name =3D "slv_lrclk6" }, + { .fw_name =3D "slv_lrclk7" }, + { .fw_name =3D "slv_lrclk8" }, + { .fw_name =3D "slv_lrclk9" }, +}; + +struct clk_regmap aud_tdmin_a_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL, + aud_mst_sclk_pdata); +struct clk_regmap aud_tdmin_a_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL); +struct clk_regmap aud_tdmin_a_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL); +struct clk_regmap aud_tdmin_a_sclk =3D + AUD_TDM_SCLK(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL); +struct clk_regmap aud_tdmin_a_lrclk =3D + AUD_TDM_LRLCK(tdmin_a_lrclk, AUDIO_CLK_TDMIN_A_CTRL, + aud_mst_lrclk_pdata); + +struct clk_regmap aud_tdmin_b_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL, + aud_mst_sclk_pdata); +struct clk_regmap aud_tdmin_b_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL); +struct clk_regmap aud_tdmin_b_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL); +struct clk_regmap aud_tdmin_b_sclk =3D + AUD_TDM_SCLK(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL); +struct clk_regmap aud_tdmin_b_lrclk =3D + AUD_TDM_LRLCK(tdmin_b_lrclk, AUDIO_CLK_TDMIN_B_CTRL, + aud_mst_lrclk_pdata); + +struct clk_regmap aud_tdmin_lb_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL, + aud_mst_sclk_pdata); +struct clk_regmap aud_tdmin_lb_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL); +struct clk_regmap aud_tdmin_lb_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL); +struct clk_regmap aud_tdmin_lb_sclk =3D + AUD_TDM_SCLK(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL); +struct clk_regmap aud_tdmin_lb_lrclk =3D + AUD_TDM_LRLCK(tdmin_lb_lrclk, AUDIO_CLK_TDMIN_LB_CTRL, + aud_mst_lrclk_pdata); + +struct clk_regmap aud_tdmout_a_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL, + aud_mst_sclk_pdata); +struct clk_regmap aud_tdmout_a_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL); +struct clk_regmap aud_tdmout_a_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL); +struct clk_regmap aud_tdmout_a_sclk =3D + AUD_TDM_SCLK_WS(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL); +struct clk_regmap aud_tdmout_a_lrclk =3D + AUD_TDM_LRLCK(tdmout_a_lrclk, AUDIO_CLK_TDMOUT_A_CTRL, + aud_mst_lrclk_pdata); + +struct clk_regmap aud_tdmout_b_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL, + aud_mst_sclk_pdata); +struct clk_regmap aud_tdmout_b_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL); +struct clk_regmap aud_tdmout_b_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL); +struct clk_regmap aud_tdmout_b_sclk =3D + AUD_TDM_SCLK_WS(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL); +struct clk_regmap aud_tdmout_b_lrclk =3D + AUD_TDM_LRLCK(tdmout_b_lrclk, AUDIO_CLK_TDMOUT_B_CTRL, + aud_mst_lrclk_pdata); + +struct clk_regmap aud_spdifin_clk_sel =3D + AUD_MST_MCLK_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); +struct clk_regmap aud_spdifin_clk_div =3D + AUD_MST_MCLK_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); +struct clk_regmap aud_spdifin_clk =3D + AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); + +struct clk_regmap aud_resample_clk_sel =3D + AUD_MUX(resample_clk_sel, AUDIO_CLK_RESAMPLEA_CTRL, 0xf, 24, + CLK_MUX_ROUND_CLOSEST, a1_mst_pdata, 0); +struct clk_regmap aud_resample_clk_div =3D + AUD_DIV(resample_clk_div, AUDIO_CLK_RESAMPLEA_CTRL, 0, 8, + CLK_DIVIDER_ROUND_CLOSEST, aud_resample_clk_sel, + CLK_SET_RATE_PARENT); +struct clk_regmap aud_resample_clk =3D + AUD_GATE(resample_clk, AUDIO_CLK_RESAMPLEA_CTRL, 31, + aud_resample_clk_div, CLK_SET_RATE_PARENT); + +struct clk_regmap aud_eqdrc_clk_sel =3D + AUD_MST_MCLK_MUX(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL); +struct clk_regmap aud_eqdrc_clk_div =3D + AUD_MST_MCLK_DIV(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL); +struct clk_regmap aud_eqdrc_clk =3D + AUD_MST_MCLK_GATE(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL); + +struct clk_regmap aud_locker_in_clk_sel =3D + AUD_MUX(locker_in_clk_sel, AUDIO_CLK_LOCKER_CTRL, 0xf, 8, + CLK_MUX_ROUND_CLOSEST, a1_mst_pdata, 0); +struct clk_regmap aud_locker_in_clk_div =3D + AUD_DIV(locker_in_clk_div, AUDIO_CLK_LOCKER_CTRL, 0, 8, + CLK_DIVIDER_ROUND_CLOSEST, aud_locker_in_clk_sel, + CLK_SET_RATE_PARENT); +struct clk_regmap aud_locker_in_clk =3D + AUD_GATE(locker_in_clk, AUDIO_CLK_LOCKER_CTRL, 15, + aud_locker_in_clk_div, CLK_SET_RATE_PARENT); + +struct clk_regmap aud_locker_out_clk_sel =3D + AUD_MUX(locker_out_clk_sel, AUDIO_CLK_LOCKER_CTRL, 0xf, 24, + CLK_MUX_ROUND_CLOSEST, a1_mst_pdata, 0); +struct clk_regmap aud_locker_out_clk_div =3D + AUD_DIV(locker_out_clk_div, AUDIO_CLK_LOCKER_CTRL, 16, 8, + CLK_DIVIDER_ROUND_CLOSEST, aud_locker_out_clk_sel, + CLK_SET_RATE_PARENT); +struct clk_regmap aud_locker_out_clk =3D + AUD_GATE(locker_out_clk, AUDIO_CLK_LOCKER_CTRL, 31, + aud_locker_out_clk_div, CLK_SET_RATE_PARENT); + +static struct clk_hw *a1_audio_clkc_hws[] =3D { + [AUD_CLKID_DDR_ARB] =3D &aud_ddr_arb.hw, + [AUD_CLKID_TDMIN_A] =3D &aud_tdmin_a.hw, + [AUD_CLKID_TDMIN_B] =3D &aud_tdmin_b.hw, + [AUD_CLKID_TDMIN_LB] =3D &aud_tdmin_lb.hw, + [AUD_CLKID_LOOPBACK] =3D &aud_loopback.hw, + [AUD_CLKID_TDMOUT_A] =3D &aud_tdmout_a.hw, + [AUD_CLKID_TDMOUT_B] =3D &aud_tdmout_b.hw, + [AUD_CLKID_FRDDR_A] =3D &aud_frddr_a.hw, + [AUD_CLKID_FRDDR_B] =3D &aud_frddr_b.hw, + [AUD_CLKID_TODDR_A] =3D &aud_toddr_a.hw, + [AUD_CLKID_TODDR_B] =3D &aud_toddr_b.hw, + [AUD_CLKID_SPDIFIN] =3D &aud_spdifin.hw, + [AUD_CLKID_RESAMPLE] =3D &aud_resample.hw, + [AUD_CLKID_EQDRC] =3D &aud_eqdrc.hw, + [AUD_CLKID_LOCKER] =3D &aud_audiolocker.hw, + [AUD_CLKID_MST_A_MCLK_SEL] =3D &aud_mst_a_mclk_sel.hw, + [AUD_CLKID_MST_A_MCLK_DIV] =3D &aud_mst_a_mclk_div.hw, + [AUD_CLKID_MST_A_MCLK] =3D &aud_mst_a_mclk.hw, + [AUD_CLKID_MST_B_MCLK_SEL] =3D &aud_mst_b_mclk_sel.hw, + [AUD_CLKID_MST_B_MCLK_DIV] =3D &aud_mst_b_mclk_div.hw, + [AUD_CLKID_MST_B_MCLK] =3D &aud_mst_b_mclk.hw, + [AUD_CLKID_MST_C_MCLK_SEL] =3D &aud_mst_c_mclk_sel.hw, + [AUD_CLKID_MST_C_MCLK_DIV] =3D &aud_mst_c_mclk_div.hw, + [AUD_CLKID_MST_C_MCLK] =3D &aud_mst_c_mclk.hw, + [AUD_CLKID_MST_D_MCLK_SEL] =3D &aud_mst_d_mclk_sel.hw, + [AUD_CLKID_MST_D_MCLK_DIV] =3D &aud_mst_d_mclk_div.hw, + [AUD_CLKID_MST_D_MCLK] =3D &aud_mst_d_mclk.hw, + [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &aud_mst_a_sclk_pre_en.hw, + [AUD_CLKID_MST_A_SCLK_DIV] =3D &aud_mst_a_sclk_div.hw, + [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &aud_mst_a_sclk_post_en.hw, + [AUD_CLKID_MST_A_SCLK] =3D &aud_mst_a_sclk.hw, + [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &aud_mst_b_sclk_pre_en.hw, + [AUD_CLKID_MST_B_SCLK_DIV] =3D &aud_mst_b_sclk_div.hw, + [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &aud_mst_b_sclk_post_en.hw, + [AUD_CLKID_MST_B_SCLK] =3D &aud_mst_b_sclk.hw, + [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &aud_mst_c_sclk_pre_en.hw, + [AUD_CLKID_MST_C_SCLK_DIV] =3D &aud_mst_c_sclk_div.hw, + [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &aud_mst_c_sclk_post_en.hw, + [AUD_CLKID_MST_C_SCLK] =3D &aud_mst_c_sclk.hw, + [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &aud_mst_d_sclk_pre_en.hw, + [AUD_CLKID_MST_D_SCLK_DIV] =3D &aud_mst_d_sclk_div.hw, + [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &aud_mst_d_sclk_post_en.hw, + [AUD_CLKID_MST_D_SCLK] =3D &aud_mst_d_sclk.hw, + [AUD_CLKID_MST_A_LRCLK_DIV] =3D &aud_mst_a_lrclk_div.hw, + [AUD_CLKID_MST_A_LRCLK] =3D &aud_mst_a_lrclk.hw, + [AUD_CLKID_MST_B_LRCLK_DIV] =3D &aud_mst_b_lrclk_div.hw, + [AUD_CLKID_MST_B_LRCLK] =3D &aud_mst_b_lrclk.hw, + [AUD_CLKID_MST_C_LRCLK_DIV] =3D &aud_mst_c_lrclk_div.hw, + [AUD_CLKID_MST_C_LRCLK] =3D &aud_mst_c_lrclk.hw, + [AUD_CLKID_MST_D_LRCLK_DIV] =3D &aud_mst_d_lrclk_div.hw, + [AUD_CLKID_MST_D_LRCLK] =3D &aud_mst_d_lrclk.hw, + [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &aud_tdmin_a_sclk_sel.hw, + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &aud_tdmin_a_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &aud_tdmin_a_sclk_post_en.hw, + [AUD_CLKID_TDMIN_A_SCLK] =3D &aud_tdmin_a_sclk.hw, + [AUD_CLKID_TDMIN_A_LRCLK] =3D &aud_tdmin_a_lrclk.hw, + [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &aud_tdmin_b_sclk_sel.hw, + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &aud_tdmin_b_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &aud_tdmin_b_sclk_post_en.hw, + [AUD_CLKID_TDMIN_B_SCLK] =3D &aud_tdmin_b_sclk.hw, + [AUD_CLKID_TDMIN_B_LRCLK] =3D &aud_tdmin_b_lrclk.hw, + [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &aud_tdmin_lb_sclk_sel.hw, + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &aud_tdmin_lb_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &aud_tdmin_lb_sclk_post_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK] =3D &aud_tdmin_lb_sclk.hw, + [AUD_CLKID_TDMIN_LB_LRCLK] =3D &aud_tdmin_lb_lrclk.hw, + [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &aud_tdmout_a_sclk_sel.hw, + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &aud_tdmout_a_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &aud_tdmout_a_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK] =3D &aud_tdmout_a_sclk.hw, + [AUD_CLKID_TDMOUT_A_LRCLK] =3D &aud_tdmout_a_lrclk.hw, + [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &aud_tdmout_b_sclk_sel.hw, + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &aud_tdmout_b_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &aud_tdmout_b_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK] =3D &aud_tdmout_b_sclk.hw, + [AUD_CLKID_TDMOUT_B_LRCLK] =3D &aud_tdmout_b_lrclk.hw, + [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &aud_spdifin_clk_sel.hw, + [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &aud_spdifin_clk_div.hw, + [AUD_CLKID_SPDIFIN_CLK] =3D &aud_spdifin_clk.hw, + [AUD_CLKID_RESAMPLE_CLK_SEL] =3D &aud_resample_clk_sel.hw, + [AUD_CLKID_RESAMPLE_CLK_DIV] =3D &aud_resample_clk_div.hw, + [AUD_CLKID_RESAMPLE_CLK] =3D &aud_resample_clk.hw, + [AUD_CLKID_EQDRC_CLK_SEL] =3D &aud_eqdrc_clk_sel.hw, + [AUD_CLKID_EQDRC_CLK_DIV] =3D &aud_eqdrc_clk_div.hw, + [AUD_CLKID_EQDRC_CLK] =3D &aud_eqdrc_clk.hw, + [AUD_CLKID_LOCKER_IN_CLK_SEL] =3D &aud_locker_in_clk_sel.hw, + [AUD_CLKID_LOCKER_IN_CLK_DIV] =3D &aud_locker_in_clk_div.hw, + [AUD_CLKID_LOCKER_IN_CLK] =3D &aud_locker_in_clk.hw, + [AUD_CLKID_LOCKER_OUT_CLK_SEL] =3D &aud_locker_out_clk_sel.hw, + [AUD_CLKID_LOCKER_OUT_CLK_DIV] =3D &aud_locker_out_clk_div.hw, + [AUD_CLKID_LOCKER_OUT_CLK] =3D &aud_locker_out_clk.hw, +}; + +static struct clk_regmap aud_vad_clk81 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D AUDIO2_CLK81_EN, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "aud_vad_clk81", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "pclk", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap aud_vad_sysclk_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D AUDIO2_CLK81_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "aud_vad_sysclk_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &aud_vad_clk81.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap aud_vad_sysclk_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D AUDIO2_CLK81_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "aud_vad_sysclk_a", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &aud_vad_sysclk_a_div.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap aud_vad_sysclk_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D AUDIO2_CLK81_CTRL, + .shift =3D 16, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "aud_vad_sysclk_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &aud_vad_clk81.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap aud_vad_sysclk_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D AUDIO2_CLK81_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "aud_vad_sysclk_b", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &aud_vad_sysclk_b_div.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data aud_vad_sysclk_pdata[] =3D { + { .hw =3D &aud_vad_sysclk_a.hw }, + { .hw =3D &aud_vad_sysclk_b.hw }, +}; + +static struct clk_regmap aud_vad_sysclk =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D AUDIO2_CLK81_CTRL, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "aud_vad_sysclk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D aud_vad_sysclk_pdata, + .num_parents =3D ARRAY_SIZE(aud_vad_sysclk_pdata), + .flags =3D CLK_SET_RATE_NO_REPARENT, + }, +}; + +static const struct clk_parent_data aud_vad_pclk_pdata[] =3D { + { .hw =3D &aud_vad_sysclk.hw }, +}; + +struct clk_regmap aud_vad_ddr_arb =3D + AUD_PCLK_GATE(vad_ddr_arb, AUDIO2_CLK_GATE_EN0, 0, aud_vad_pclk_pdata); +struct clk_regmap aud_vad_pdm =3D + AUD_PCLK_GATE(vad_pdm, AUDIO2_CLK_GATE_EN0, 1, aud_vad_pclk_pdata); +struct clk_regmap aud_vad_tdmin_vad =3D + AUD_PCLK_GATE(vad_tdmin_vad, AUDIO2_CLK_GATE_EN0, 2, aud_vad_pclk_pdata); +struct clk_regmap aud_vad_toddr_vad =3D + AUD_PCLK_GATE(vad_toddr_vad, AUDIO2_CLK_GATE_EN0, 3, aud_vad_pclk_pdata); +struct clk_regmap aud_vad_tovad =3D + AUD_PCLK_GATE(tovad, AUDIO2_CLK_GATE_EN0, 4, aud_vad_pclk_pdata); +struct clk_regmap aud_vad_toaudiotop =3D + AUD_PCLK_GATE(vad_toaudiotop, AUDIO2_CLK_GATE_EN0, 7, aud_vad_pclk_pdata); + +struct clk_regmap aud_vad_mst_vad_mclk_sel =3D + AUD_MST_MCLK_MUX(vad_mst_vad_mclk, AUDIO2_MCLK_VAD_CTRL); +struct clk_regmap aud_vad_mst_vad_mclk_div =3D + AUD_MST_MCLK_DIV(vad_mst_vad_mclk, AUDIO2_MCLK_VAD_CTRL); +struct clk_regmap aud_vad_mst_vad_mclk =3D + AUD_MST_MCLK_GATE(vad_mst_vad_mclk, AUDIO2_MCLK_VAD_CTRL); + +struct clk_regmap aud_vad_mst_vad_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(vad_mst_vad_sclk, AUDIO2_MST_VAD_SCLK_CTRL0, + vad_mst_vad_mclk); +struct clk_regmap aud_vad_mst_vad_sclk_div =3D + AUD_MST_SCLK_DIV(vad_mst_vad_sclk, AUDIO2_MST_VAD_SCLK_CTRL0); +struct clk_regmap aud_vad_mst_vad_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(vad_mst_vad_sclk, AUDIO2_MST_VAD_SCLK_CTRL0); +struct clk_regmap aud_vad_mst_vad_sclk =3D + AUD_MST_SCLK(vad_mst_vad_sclk, AUDIO2_MST_VAD_SCLK_CTRL1); + +struct clk_regmap aud_vad_mst_vad_lrclk_div =3D + AUD_MST_LRCLK_DIV(vad_mst_vad_lrclk, AUDIO2_MST_VAD_SCLK_CTRL0, + vad_mst_vad_sclk_post_en); +struct clk_regmap aud_vad_mst_vad_lrclk =3D + AUD_MST_LRCLK(vad_mst_vad_lrclk, AUDIO2_MST_VAD_SCLK_CTRL1); + +struct clk_regmap aud_vad_pdm_dclk_sel =3D + AUD_MST_MCLK_MUX(vad_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0); +struct clk_regmap aud_vad_pdm_dclk_div =3D + AUD_MST_MCLK_DIV(vad_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0); +struct clk_regmap aud_vad_pdm_dclk =3D + AUD_MST_MCLK_GATE(vad_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0); + +struct clk_regmap aud_vad_pdm_sysclk_sel =3D + AUD_MST_MCLK_MUX(vad_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1); +struct clk_regmap aud_vad_pdm_sysclk_div =3D + AUD_MST_MCLK_DIV(vad_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1); +struct clk_regmap aud_vad_pdm_sysclk =3D + AUD_MST_MCLK_GATE(vad_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1); + +struct clk_regmap aud_vad_vad_clk_sel =3D + AUD_MST_MCLK_MUX(vad_vad_clk, AUDIO2_CLK_VAD_CTRL); +struct clk_regmap aud_vad_vad_clk_div =3D + AUD_MST_MCLK_DIV(vad_vad_clk, AUDIO2_CLK_VAD_CTRL); +struct clk_regmap aud_vad_vad_clk =3D + AUD_MST_MCLK_GATE(vad_vad_clk, AUDIO2_CLK_VAD_CTRL); + +static const struct clk_parent_data aud_vad_mst_sclk_pdata[] =3D { + { .hw =3D &aud_vad_mst_vad_sclk.hw, .index =3D -1 }, + { }, + { }, + { }, + { }, + { }, + { .fw_name =3D "slv_sclk0" }, + { .fw_name =3D "slv_sclk1" }, + { .fw_name =3D "slv_sclk2" }, + { .fw_name =3D "slv_sclk3" }, + { .fw_name =3D "slv_sclk4" }, + { .fw_name =3D "slv_sclk5" }, + { .fw_name =3D "slv_sclk6" }, + { .fw_name =3D "slv_sclk7" }, + { .fw_name =3D "slv_sclk8" }, + { .fw_name =3D "slv_sclk9" }, + }; + +static const struct clk_parent_data aud_vad_mst_lrclk_pdata[] =3D { + { .hw =3D &aud_vad_mst_vad_lrclk.hw, .index =3D -1 }, + { }, + { }, + { }, + { }, + { }, + { .fw_name =3D "slv_lrclk0" }, + { .fw_name =3D "slv_lrclk1" }, + { .fw_name =3D "slv_lrclk2" }, + { .fw_name =3D "slv_lrclk3" }, + { .fw_name =3D "slv_lrclk4" }, + { .fw_name =3D "slv_lrclk5" }, + { .fw_name =3D "slv_lrclk6" }, + { .fw_name =3D "slv_lrclk7" }, + { .fw_name =3D "slv_lrclk8" }, + { .fw_name =3D "slv_lrclk9" }, +}; + +struct clk_regmap aud_vad_tdmin_vad_sclk_sel =3D + AUD_TDM_SCLK_MUX(vad_tdmin_vad_a_sclk, AUDIO2_CLK_TDMIN_VAD_CTRL, + aud_vad_mst_sclk_pdata); +struct clk_regmap aud_vad_tdmin_vad_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmin_vad_sclk, AUDIO2_CLK_TDMIN_VAD_CTRL); +struct clk_regmap aud_vad_tdmin_vad_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmin_vad_sclk, AUDIO2_CLK_TDMIN_VAD_CTRL); +struct clk_regmap aud_vad_tdmin_vad_sclk =3D + AUD_TDM_SCLK(tdmin_vad_sclk, AUDIO2_CLK_TDMIN_VAD_CTRL); +struct clk_regmap aud_vad_tdmin_vad_lrclk =3D + AUD_TDM_LRLCK(tdmin_vad_lrclk, AUDIO2_CLK_TDMIN_VAD_CTRL, + aud_vad_mst_lrclk_pdata); + +static struct clk_hw *a1_audio_vad_clkc_hws[] =3D { + [AUD_VAD_CLKID_CLK81] =3D &aud_vad_clk81.hw, + [AUD_VAD_CLKID_SYSCLK_A_DIV] =3D &aud_vad_sysclk_a_div.hw, + [AUD_VAD_CLKID_SYSCLK_A] =3D &aud_vad_sysclk_a.hw, + [AUD_VAD_CLKID_SYSCLK_B_DIV] =3D &aud_vad_sysclk_b_div.hw, + [AUD_VAD_CLKID_SYSCLK_B] =3D &aud_vad_sysclk_b.hw, + [AUD_VAD_CLKID_SYSCLK] =3D &aud_vad_sysclk.hw, + [AUD_VAD_CLKID_DDR_ARB] =3D &aud_vad_ddr_arb.hw, + [AUD_VAD_CLKID_PDM] =3D &aud_vad_pdm.hw, + [AUD_VAD_CLKID_TDMIN_VAD] =3D &aud_vad_tdmin_vad.hw, + [AUD_VAD_CLKID_TODDR_VAD] =3D &aud_vad_toddr_vad.hw, + [AUD_VAD_CLKID_TOVAD] =3D &aud_vad_tovad.hw, + [AUD_VAD_CLKID_TOAUDIOTOP] =3D &aud_vad_toaudiotop.hw, + [AUD_VAD_CLKID_MST_VAD_MCLK_SEL] =3D &aud_vad_mst_vad_mclk_sel.hw, + [AUD_VAD_CLKID_MST_VAD_MCLK_DIV] =3D &aud_vad_mst_vad_mclk_div.hw, + [AUD_VAD_CLKID_MST_VAD_MCLK] =3D &aud_vad_mst_vad_mclk.hw, + [AUD_VAD_CLKID_MST_VAD_SCLK_PRE_EN] =3D &aud_vad_mst_vad_sclk_pre_en.hw, + [AUD_VAD_CLKID_MST_VAD_SCLK_DIV] =3D &aud_vad_mst_vad_sclk_div.hw, + [AUD_VAD_CLKID_MST_VAD_SCLK_POST_EN] =3D &aud_vad_mst_vad_sclk_post_en.hw, + [AUD_VAD_CLKID_MST_VAD_SCLK] =3D &aud_vad_mst_vad_sclk.hw, + [AUD_VAD_CLKID_MST_VAD_LRCLK_DIV] =3D &aud_vad_mst_vad_lrclk_div.hw, + [AUD_VAD_CLKID_MST_VAD_LRCLK] =3D &aud_vad_mst_vad_lrclk.hw, + [AUD_VAD_CLKID_TDMIN_VAD_SCLK_SEL] =3D &aud_vad_tdmin_vad_sclk_sel.hw, + [AUD_VAD_CLKID_TDMIN_VAD_SCLK_PRE_EN] =3D &aud_vad_tdmin_vad_sclk_pre_en.= hw, + [AUD_VAD_CLKID_TDMIN_VAD_SCLK_POST_EN] =3D &aud_vad_tdmin_vad_sclk_post_e= n.hw, + [AUD_VAD_CLKID_TDMIN_VAD_SCLK] =3D &aud_vad_tdmin_vad_sclk.hw, + [AUD_VAD_CLKID_TDMIN_VAD_LRCLK] =3D &aud_vad_tdmin_vad_lrclk.hw, + [AUD_VAD_CLKID_PDM_DCLK_SEL] =3D &aud_vad_pdm_dclk_sel.hw, + [AUD_VAD_CLKID_PDM_DCLK_DIV] =3D &aud_vad_pdm_dclk_div.hw, + [AUD_VAD_CLKID_PDM_DCLK] =3D &aud_vad_pdm_dclk.hw, + [AUD_VAD_CLKID_PDM_SYSCLK_SEL] =3D &aud_vad_pdm_sysclk_sel.hw, + [AUD_VAD_CLKID_PDM_SYSCLK_DIV] =3D &aud_vad_pdm_sysclk_div.hw, + [AUD_VAD_CLKID_PDM_SYSCLK] =3D &aud_vad_pdm_sysclk.hw, + [AUD_VAD_CLKID_VAD_CLK_SEL] =3D &aud_vad_vad_clk_sel.hw, + [AUD_VAD_CLKID_VAD_CLK_DIV] =3D &aud_vad_vad_clk_div.hw, + [AUD_VAD_CLKID_VAD_CLK] =3D &aud_vad_vad_clk.hw, +}; + +struct a1_audio_data { + struct meson_clk_hw_data hw_clks; + const char *rst_drvname; +}; + +static const struct regmap_config a1_audio_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int a1_audio_clkc_probe(struct platform_device *pdev) +{ + const struct a1_audio_data *data; + struct regmap *map; + void __iomem *base; + struct clk *clk; + unsigned int i; + int ret; + + data =3D device_get_match_data(&pdev->dev); + if (!data) + return -EINVAL; + + clk =3D devm_clk_get_enabled(&pdev->dev, "pclk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map =3D devm_regmap_init_mmio(&pdev->dev, base, &a1_audio_regmap_cfg); + if (IS_ERR(map)) + return PTR_ERR(map); + + ret =3D device_reset(&pdev->dev); + if (ret) + return ret; + + for (i =3D 0; i < data->hw_clks.num; i++) { + struct clk_hw *hw =3D data->hw_clks.hws[i]; + struct clk_regmap *clk_regmap =3D to_clk_regmap(hw); + + if (!hw) + continue; + + clk_regmap->map =3D map; + + ret =3D devm_clk_hw_register(&pdev->dev, hw); + if (ret) + return ret; + } + + ret =3D devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get, + (void *)&data->hw_clks); + if (ret) + return ret; + + return devm_meson_rst_aux_register(&pdev->dev, map, data->rst_drvname); +} + +struct a1_audio_data a1_audio_clkc =3D { + .hw_clks =3D { + .hws =3D a1_audio_clkc_hws, + .num =3D ARRAY_SIZE(a1_audio_clkc_hws), + }, + .rst_drvname =3D "rst-a1", +}; + +struct a1_audio_data a1_audio_vad_clkc =3D { + .hw_clks =3D { + .hws =3D a1_audio_vad_clkc_hws, + .num =3D ARRAY_SIZE(a1_audio_vad_clkc_hws), + }, + .rst_drvname =3D "rst-a1-vad", +}; + +static const struct of_device_id a1_audio_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a1-audio-clkc", + .data =3D &a1_audio_clkc, + }, + { + .compatible =3D "amlogic,a1-audio-vad-clkc", + .data =3D &a1_audio_vad_clkc, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a1_audio_clkc_match_table); + +static struct platform_driver a1_audio_clkc_driver =3D { + .probe =3D a1_audio_clkc_probe, + .driver =3D { + .name =3D "a1-audio-clkc", + .of_match_table =3D a1_audio_clkc_match_table, + }, +}; +module_platform_driver(a1_audio_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A1 Audio Clock driver"); +MODULE_AUTHOR("Jan Dakinevich "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(CLK_MESON); --=20 2.34.1