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([145.224.90.214]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432bbf436ffsm142270955e9.44.2024.11.12.02.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 02:38:26 -0800 (PST) From: James Clark To: suzuki.poulose@arm.com, oliver.upton@linux.dev, coresight@lists.linaro.org, kvmarm@lists.linux.dev Cc: James Clark , Marc Zyngier , Joey Gouly , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Alexander Shishkin , Mark Rutland , Anshuman Khandual , Fuad Tabba , James Morse , Shiqi Liu , Mark Brown , Raghavendra Rao Ananta , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 07/12] KVM: arm64: arm_spe: Give SPE enabled state to KVM Date: Tue, 12 Nov 2024 10:37:06 +0000 Message-Id: <20241112103717.589952-8-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112103717.589952-1-james.clark@linaro.org> References: <20241112103717.589952-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently in nVHE, KVM has to check if SPE is enabled on every guest switch even if it was never used. Because it's a debug feature and is more likely to not be used than used, give KVM the SPE buffer status to allow a much simpler and faster do-nothing path in the hyp. This is always called with preemption disabled except for probe/hotplug which gets wrapped with preempt_disable(). Signed-off-by: James Clark --- arch/arm64/include/asm/kvm_host.h | 6 ++++++ arch/arm64/kvm/debug.c | 29 +++++++++++++++++++++++++++++ drivers/perf/arm_spe_pmu.c | 13 +++++++++++-- 3 files changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 5dfc3f4f74b2..7f1e32d40f0c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -641,6 +641,8 @@ struct kvm_host_data { struct { /* Host CPU features, set at init */ u8 feats; + /* Host CPU state */ + u8 state; } flags; =20 /* @@ -941,6 +943,8 @@ struct kvm_vcpu_arch { #define HOST_FEAT_HAS_TRBE __kvm_single_flag(feats, BIT(1)) /* CPU has Feat_TRF */ #define HOST_FEAT_HAS_TRF __kvm_single_flag(feats, BIT(2)) +/* PMBLIMITR_EL1_E is set (SPE profiling buffer enabled) */ +#define HOST_STATE_SPE_EN __kvm_single_flag(state, BIT(0)) =20 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ @@ -1382,6 +1386,7 @@ static inline bool kvm_pmu_counter_deferred(struct pe= rf_event_attr *attr) void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); void kvm_clr_pmu_events(u64 clr); bool kvm_set_pmuserenr(u64 val); +void kvm_set_pmblimitr(u64 pmblimitr); #else static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *att= r) {} static inline void kvm_clr_pmu_events(u64 clr) {} @@ -1389,6 +1394,7 @@ static inline bool kvm_set_pmuserenr(u64 val) { return false; } +static inline void kvm_set_pmblimitr(u64 pmblimitr) {} #endif =20 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index fb41ef5d9db9..ed3b4d057c52 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -335,3 +335,32 @@ void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) } } } + +static bool kvm_arm_skip_trace_state(void) +{ + /* pKVM hyp finds out the state for itself */ + if (is_protected_kvm_enabled()) + return true; + + /* Make sure state gets there in one piece */ + if (WARN_ON_ONCE(preemptible())) + return true; + + return false; +} + +void kvm_set_pmblimitr(u64 pmblimitr) +{ + /* Only read in nVHE */ + if (has_vhe()) + return; + + if (kvm_arm_skip_trace_state()) + return; + + if (pmblimitr & PMBLIMITR_EL1_E) + host_data_set_flag(HOST_STATE_SPE_EN); + else + host_data_clear_flag(HOST_STATE_SPE_EN); +} +EXPORT_SYMBOL_GPL(kvm_set_pmblimitr); diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 3569050f9cf3..6a79df363aa6 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -496,6 +497,12 @@ static u64 arm_spe_pmu_next_off(struct perf_output_han= dle *handle) return limit; } =20 +static void arm_spe_write_pmblimitr(u64 val) +{ + write_sysreg_s(val, SYS_PMBLIMITR_EL1); + kvm_set_pmblimitr(val); +} + static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handl= e, struct perf_event *event) { @@ -524,7 +531,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_o= utput_handle *handle, write_sysreg_s(base, SYS_PMBPTR_EL1); =20 out_write_limit: - write_sysreg_s(limit, SYS_PMBLIMITR_EL1); + arm_spe_write_pmblimitr(limit); } =20 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle) @@ -552,7 +559,7 @@ static void arm_spe_pmu_disable_and_drain_local(void) dsb(nsh); =20 /* Disable the profiling buffer */ - write_sysreg_s(0, SYS_PMBLIMITR_EL1); + arm_spe_write_pmblimitr(0); isb(); } =20 @@ -1095,7 +1102,9 @@ static void __arm_spe_pmu_reset_local(void) * This is probably overkill, as we have no idea where we're * draining any buffered data to... */ + preempt_disable(); arm_spe_pmu_disable_and_drain_local(); + preempt_enable(); =20 /* Reset the buffer base pointer */ write_sysreg_s(0, SYS_PMBPTR_EL1); --=20 2.34.1