From nobody Sat Nov 23 17:52:54 2024 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9A26433BE; Tue, 12 Nov 2024 01:38:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=85.214.62.61 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731375503; cv=none; b=pXk5/jsyTySgrwKFLBOiiAf2vYABCGDc7LL2ek8ADD7iWREA4/wi9IXmMW0aCrRrKbi5Lm6PBjQaTHL+1uRMUu9+KxSrFF62A9rwffwndyE2nJKCh9m4I6qkZ+hEjtUbB3VU4aZhneCwPR74TuuqDIviyZIDGb6a5OiMhC5hK+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731375503; c=relaxed/simple; bh=ZDDBiEwZKcz0TKEWOQ1unCUxEsAeVpqC0oOABmKlJAs=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=e+hHtUJdPFX6bum2D67w7H3unR/86K5sD/wsI8n96KpxaEV4jKBX7pfXKokiilSFFyuOUa37uH72mwgrzCAxyYwGj+ziiFd1rVc+UDginCSqwE0MdXIWDNHezifCfIjjdlNUJhhRk5E4HjVM2neMA4QRaj9nsBsri7sgSclPW+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=jtCNPgxh; arc=none smtp.client-ip=85.214.62.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="jtCNPgxh" Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 8F51389366; Tue, 12 Nov 2024 02:38:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1731375499; bh=4JRFsd20+VO7ZETXG4aTiKC3hxrIudSAdNFYyXGhdFM=; h=From:To:Cc:Subject:Date:From; b=jtCNPgxhaS3vINI4X/LoOQGYJCW6CH49qmC7Fg9RjssW9ItXQHKiyzurb4gQcdWJv 9q9/rqwtSMZSXJaYePQeOlaouNY+bUjzP2X9OlXOW/nYRsGEDkxfBT9FMibMzGn8cs IaQQYqZ1DTBi8AIAVnqYoGeArmSwOst5NcgK0/fk+huzCpx/Xvmxj3VJlV1wEb0oXa u4T29MGhJwXSq27xE6dQ0MPHAOUUKxRTWPl2qs76MzwTkYiUQyTcCuTofk/HSydCJP aRPd4CIKnUJK0l5/uqKcejT7PqRI1laNQbHvAbGO90fRKxcz8T+Zuj7mG/5fsST59C 36AwLJLICD6zw== From: Marek Vasut To: linux-clk@vger.kernel.org Cc: Marek Vasut , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x Date: Tue, 12 Nov 2024 02:37:35 +0100 Message-ID: <20241112013805.333798-1-marex@denx.de> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Content-Type: text/plain; charset="utf-8" The PLL1416x is used to implement SYS_PLL3 on i.MX8MP and can be used to drive CLKOUTn clock. Add 208 MHz and 416 MHz entries to the PLL so they can be generated by the PLL and used to produce e.g. 13 MHz or 26 MHz on CLKOUTn output. Signed-off-by: Marek Vasut --- Cc: Abel Vesa Cc: Fabio Estevam Cc: Michael Turquette Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Sascha Hauer Cc: Shawn Guo Cc: Stephen Boyd Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/clk/imx/clk-pll14xx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 19b9f764a0015..a69dd34431b03 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -56,7 +56,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_t= bl[] =3D { PLL_1416X_RATE(700000000U, 350, 3, 2), PLL_1416X_RATE(640000000U, 320, 3, 2), PLL_1416X_RATE(600000000U, 300, 3, 2), + PLL_1416X_RATE(416000000U, 208, 3, 2), PLL_1416X_RATE(320000000U, 160, 3, 2), + PLL_1416X_RATE(208000000U, 208, 3, 3), }; =20 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] =3D { --=20 2.45.2