From nobody Sat Nov 23 20:54:54 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 627401F6674; Tue, 12 Nov 2024 00:29:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731371370; cv=none; b=brrSIuTyvv9Y6rWDvAoTtmAwt3PAEPR62SGIA+bLmMGh9IasvhzHStclJCNyAB6nAXTp06M0gCvtHHNgchknUPefr3XYs+uXcdryDrzh2iVlzh4RA6Q3iNkYbvACrXo384fHagVuJ8ZaPQid0clL2CjHCLylRYk4sGhf1oxKgtA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731371370; c=relaxed/simple; bh=RWwE5GM3+TZvUaLJcnYJ4N8uv7721qGcvvJfCe8bv74=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V58gOiNUp/i4rX5MEQNrB60rLVpO+01HgcsDKv/efEJMSrRNxEZ08xmkj/tIba3zp1NIlqhmPGUxBb/2jLd4EedeuMXwQ3w/2XVPCpTy3ur16+BCj5XcUHQ5q8QERzuNNyd5zbXryIVSUcQFObxcU5QB3KLVEqJ6nS7OX+MYXHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=I52khEYU; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="I52khEYU" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ABDUSRJ025482; Tue, 12 Nov 2024 00:29:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UFD672WQ52z66FrdmYLNErZsw54I07dqwzoOaAS4SqU=; b=I52khEYUf4LLJI71 bOwX1mi78lzJthyJMuZR6GBXNZn1QAg2sm8Vk+gTukSM1WkiPkEAuU842w44hYTA y9mtP8AAWJBEpkyC4rG8gWeYyDlxh811bY/UYGzbOEtIWHeQHgq98IZxobv6K/x8 5ucx3dOR6RcZRNsyH5jfoIn0tub44jgDRWk+CS+BFn6Z9iSyCMZp2PEiPwK5+C7/ Cl0qfH6d8HLyLbSETyrmiCMHtMckn8JIBhGnsuStKjaHQ4dAKXKBBrjFZjmgcO2a P+/bfdjJ1lxVNjq/pRKis2MhR7Rjhq9hpgbD6/Gad7oCZt35ayk8klSyOmKNPsxA P+RQOw== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42sytsnnn0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 00:29:22 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AC0TLVi025660 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 00:29:21 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 11 Nov 2024 16:29:21 -0800 From: Melody Olvera To: Bjorn Andersson , Linus Walleij , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Melody Olvera" , Trilok Soni , Satya Durga Srinivasu Prabhala CC: , , , , "Krzysztof Kozlowski" Subject: [PATCH v2 1/2] dt-bindings: pinctrl: qcom: Add sm8750 pinctrl Date: Mon, 11 Nov 2024 16:28:42 -0800 Message-ID: <20241112002843.2804490-2-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20241112002843.2804490-1-quic_molvera@quicinc.com> References: <20241112002843.2804490-1-quic_molvera@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TlMi3djI50wLucRjFts1avGcSf5IA5Mm X-Proofpoint-ORIG-GUID: TlMi3djI50wLucRjFts1avGcSf5IA5Mm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411120002 Content-Type: text/plain; charset="utf-8" Add documentation for the Qualcomm sm8750 tlmm. Signed-off-by: Melody Olvera Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,sm8750-tlmm.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8750-t= lmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yam= l b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml new file mode 100644 index 000000000000..7aecc97745a8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8750-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8750 TLMM block + +maintainers: + - Melody Olvera + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8750 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8750-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 108 + + gpio-line-names: + maxItems: 215 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8750-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8750-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8750-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4]= )$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mcl= k4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_time= r, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fa= il, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi= 2, + ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_a= dc0, + gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_= se3, + i2chub0_se4, i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub= 0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter= _bist, + mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5= _out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qsp= i3, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, + sd_write_protect, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, tmess_prng0, tmess_p= rng1, + tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, tsense= _pwm3, + tsense_pwm4, uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, usb1_hs, us= b_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@f100000 { + compatible =3D "qcom,sm8750-tlmm"; + reg =3D <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 216>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + gpio-wo-state { + pins =3D "gpio1"; + function =3D "gpio"; + }; + + uart-w-state { + rx-pins { + pins =3D "gpio60"; + function =3D "qup1_se7"; + bias-pull-up; + }; + + tx-pins { + pins =3D "gpio61"; + function =3D "qup1_se7"; + bias-disable; + }; + }; + }; +... --=20 2.46.1