From nobody Sat Nov 23 20:35:08 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 200EB1EBFFD; Tue, 12 Nov 2024 00:28:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731371305; cv=none; b=rLDqnHqsTBhwxcI9UZqzfo9w0lSgrYf3HUj4MZq99C2kIDRk7cW2GwgM91rqj7expKqHp5emELBhm4dxLMRO5GTjQ560qKYQBxLL0oLLgdTtu/SdFocJyPfesOur+BJ/kf51sx12LntBGxROfKLnG4j7mZ/n1s6HyEoZPbOzxgY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731371305; c=relaxed/simple; bh=LR6E+004aFeNsAuKpi91L3Bty+FVgv7XXuMhQgw2Qls=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kDOFGvN84d3FuvAVlO9ZCVDQxC/vwW3v2pl5LLUYlIYQtPZgYYtEB1xjmX15u+bNoAjKAgvkK/aUbF+xSUUXH7AGSctaqT609C2csVdVEYKOBD40JpB57sk0Zk6aJEvQNpVcKZ4DQKGKANylSVBcgogGcDT4qrOsS5/1wyenfW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Jx0pvKZV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Jx0pvKZV" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ABI6dZG022539; Tue, 12 Nov 2024 00:28:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= SbSYseMj0ij5mouERzQC0nOm0AV724RMGH0FiM0Hq6g=; b=Jx0pvKZVZe4frcec mPzdRl6yvAlvk0AZCTetEiz+wclPcAgz3wZEvZ2Vvs+BPfo/PVxVXw4LZNiWauzd UMGKgik5dtzvktTxTILLfwmLzqLDfju3HhQLCeqf8Za4cVR5cKkU72VrVp/SwbI6 u2w5bLuXva+Y6o+xD4c5Rk6Jv8kuZ6C80+61Ra+mlsI40tDUawnEkXsNmK6aE7wz YLMkYbBGvCI+5RM9BOJXXli0bJ/7Lso4wJDiT+62hjNawERMMbXT+O41g5VK2FPf SYoaWs9yRFMmofahG5fP19LfgMwriEb8lWMlytU9lSoF9fqTNT7YiEdl+p7S545+ 6fp9GA== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42uc60a9pd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 00:28:19 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AC0SIlV024783 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 00:28:19 GMT Received: from hu-molvera-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 11 Nov 2024 16:28:18 -0800 From: Melody Olvera To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Trilok Soni , Satya Durga Srinivasu Prabhala CC: , , , , Melody Olvera Subject: [PATCH v2 3/7] clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs Date: Mon, 11 Nov 2024 16:28:03 -0800 Message-ID: <20241112002807.2804021-4-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20241112002807.2804021-1-quic_molvera@quicinc.com> References: <20241112002807.2804021-1-quic_molvera@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Gr093vwmze-oJjTSHYNPBmbDo1rcP0zs X-Proofpoint-ORIG-GUID: Gr093vwmze-oJjTSHYNPBmbDo1rcP0zs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411120002 Content-Type: text/plain; charset="utf-8" From: Taniya Das Add clock ops for Taycan PLL, add the register offsets for supporting the PLL. Signed-off-by: Taniya Das Signed-off-by: Melody Olvera Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-alpha-pll.c | 14 ++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index b8351f8c0b84..5e9217ea3760 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -197,6 +197,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] =3D { [PLL_OFF_TEST_CTL_U1] =3D 0x34, [PLL_OFF_TEST_CTL_U2] =3D 0x38, }, + [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] =3D { + [PLL_OFF_OPMODE] =3D 0x04, + [PLL_OFF_STATE] =3D 0x08, + [PLL_OFF_STATUS] =3D 0x0c, + [PLL_OFF_L_VAL] =3D 0x10, + [PLL_OFF_ALPHA_VAL] =3D 0x14, + [PLL_OFF_USER_CTL] =3D 0x18, + [PLL_OFF_USER_CTL_U] =3D 0x1c, + [PLL_OFF_CONFIG_CTL] =3D 0x20, + [PLL_OFF_CONFIG_CTL_U] =3D 0x24, + [PLL_OFF_CONFIG_CTL_U1] =3D 0x28, + [PLL_OFF_TEST_CTL] =3D 0x2c, + [PLL_OFF_TEST_CTL_U] =3D 0x30, + }, [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] =3D { [PLL_OFF_OPMODE] =3D 0x04, [PLL_OFF_STATUS] =3D 0x0c, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index c6d1b8429f95..87bd469d9c2c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -27,6 +27,7 @@ enum { CLK_ALPHA_PLL_TYPE_ZONDA_OLE, CLK_ALPHA_PLL_TYPE_LUCID_EVO, CLK_ALPHA_PLL_TYPE_LUCID_OLE, + CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, @@ -185,12 +186,15 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops =20 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; +#define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops +#define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_o= ps extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_ev= o_ops +#define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_e= vo_ops =20 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_o= ps @@ -218,6 +222,9 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *= pll, struct regmap *regma const struct alpha_pll_config *config); void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap = *regmap, const struct alpha_pll_config *config); +#define clk_taycan_elu_pll_configure(pll, regmap, config) \ + clk_lucid_evo_pll_configure(pll, regmap, config) + void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap= *regmap, const struct alpha_pll_config *config); void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *r= egmap, --=20 2.46.1