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Tue, 12 Nov 2024 11:01:58 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ACB1wAB027366 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 11:01:58 GMT Received: from hu-mkshah-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 12 Nov 2024 03:01:55 -0800 From: Maulik Shah Date: Tue, 12 Nov 2024 16:31:51 +0530 Subject: [PATCH] arm64: dts: qcom: sa8775p: Add CPUs to psci power domain Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241112-sa8775p_cpuidle-v1-1-66ff3ba72464@quicinc.com> X-B4-Tracking: v=1; b=H4sIAJ41M2cC/x3M0QpAMBSA4VfRubZyDhpeRdJwximxtkhp7265/ C7+/4XAXjhAl73g+ZYg55GAeQbzZo6VlSzJQAVViEgqmEbr2o2zu2TZWdW2nCyZVhO2kCrn2cr zH/shxg/IlJPBYQAAAA== To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski CC: , , , , Maulik Shah X-Mailer: b4 0.12.5-dev-2aabd X-Developer-Signature: v=1; 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Add CPUs to psci power domain. Fixes: 4f79d0deae37 ("arm64: dts: qcom: sa8775p: add CPU idle states") Signed-off-by: Maulik Shah Reviewed-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 9f315a51a7c1..26290feb768f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -44,6 +44,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x0>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <1024>; @@ -66,6 +68,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x100>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; @@ -83,6 +87,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x200>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; next-level-cache =3D <&l2_2>; capacity-dmips-mhz =3D <1024>; @@ -100,6 +106,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x300>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; next-level-cache =3D <&l2_3>; capacity-dmips-mhz =3D <1024>; @@ -117,6 +125,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x10000>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; next-level-cache =3D <&l2_4>; capacity-dmips-mhz =3D <1024>; @@ -140,6 +150,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x10100>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; next-level-cache =3D <&l2_5>; capacity-dmips-mhz =3D <1024>; @@ -157,6 +169,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x10200>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; next-level-cache =3D <&l2_6>; capacity-dmips-mhz =3D <1024>; @@ -174,6 +188,8 @@ compatible =3D "qcom,kryo"; reg =3D <0x0 0x10300>; enable-method =3D "psci"; + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; next-level-cache =3D <&l2_7>; capacity-dmips-mhz =3D <1024>; --- base-commit: 6d59cab07b8d74d0f0422b750038123334f6ecc2 change-id: 20241112-sa8775p_cpuidle-5f3bf2a97219 Best regards, --=20 Maulik Shah