From nobody Sat Nov 23 15:22:54 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE2AC143736; Tue, 12 Nov 2024 13:08:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731416910; cv=none; b=ES+JYeVafm66C7DasDkBgf5NP28/og/0lJ8+gs7GcJiPZEYO/7DrjeCokwvO4WZPD8EDibGWn1sdwK0TiUteTh2FYtHtdpdIgjzAxw8hjVdgwSVC2GJW3oOtsviJS26Mrmkml5IZa0geii2tKPPSSknRE06gO6bUPiF2Vk+p5Ik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731416910; c=relaxed/simple; bh=Po9pxFWk2HFHIhixUOhSXupXUnhxhB+nhL5Y2znWJoI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BFZfnHfW9iAnIxDq96CZX2tN5QaWXaz7QnaPlE+lQh9DWFGT1dhfK1p56W20JPx5apv0lHoEhM1/L/8LKL6VuMkFojJw7yY0RxrI4dZ/ufS7XsHXu2uPogxyTGlUqp09M1k5krhj1gVanWWXRy6+ipif3UdgCfUzXjAXoMm91Lg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UVayi9D3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UVayi9D3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CF23BC4CED0; Tue, 12 Nov 2024 13:08:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731416910; bh=Po9pxFWk2HFHIhixUOhSXupXUnhxhB+nhL5Y2znWJoI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UVayi9D3PDmZldTVrKzIKrmL5g3qgpbmFV0igy1C1DktP9zQwVvHRzqjSI7/V5m9w LRfDN9/Z9PbcnjRxOfUVDFmQkMW0bzNILZuL+a0B26aqZvv2c+1s1qTbllH08XJKky 4lt0iFASUgBO0AfXo5jMwa/wZkYZm1cnNupKOl4xVJPUOf8k3g02kY0ZPzqZcf+J+x 9mCMI1E336P6EdjjV2wgo9GzsQ3OTjhSOg8PpE95sXM/cGJpdNFvwFM+Y2GUOM3G9X aWg15WLtYSDETW8aCZOjnKqz9tdbzRuMBy/IQRiBfL96MFHUDTgjmtCxc1g0yLGmnY iMWAZf5hTPq5Q== From: Mark Brown Date: Tue, 12 Nov 2024 13:08:14 +0000 Subject: [PATCH v2 1/3] kselftets/arm64: Use flag bits for features in fp-ptrace assembler code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241112-arm64-fp-ptrace-fpmr-v2-1-250b57c61254@kernel.org> References: <20241112-arm64-fp-ptrace-fpmr-v2-0-250b57c61254@kernel.org> In-Reply-To: <20241112-arm64-fp-ptrace-fpmr-v2-0-250b57c61254@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-355e8 X-Developer-Signature: v=1; a=openpgp-sha256; l=5038; i=broonie@kernel.org; h=from:subject:message-id; bh=Po9pxFWk2HFHIhixUOhSXupXUnhxhB+nhL5Y2znWJoI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnM1NHEx61YFzQeBViB8PBNV/DuW81eT68euXuL LPjTZzScAyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZzNTRwAKCRAk1otyXVSH 0Kw3B/0cm9pPUWblWpgD4vVtCbfQxkB+arVRZY7rzgDu1NfwVtUS7XzcAKZ9iHnv0bWz39RR3yU 0DRV6x+16Yq6i8JEdgHUZYXmpRq08c4gCrJ7A+tWIR9LCnAh9o27uqOVuzgNmEfRRc5cBTvJ21V Bi89JYhXojX3V065MdXDpQDEUVlNEGVMFwjzMLiDv5BElZS+N9fEcZrmAwl1YgKQgT6Nq77lQXB +2QZVm/UCvfuyqfWi/S8UCELG6+ElQw3SFHMPKBrdM/cn7nxeIq4cOSrNzssbn5Kz5xX4KGIIs/ /Dp6Kov0TwlyExGUacF1puaQE0j3yC7MNWDE5RFlkpQucsZA X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The assembler portions of fp-ptrace are passed feature flags by the C code indicating which architectural features are supported. Currently these use an entire register for each flag which is wasteful and gets cumbersome as new flags are added. Switch to using flag bits in a single register to make things easier to maintain. No functional change. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/fp-ptrace-asm.S | 32 +++++++++++++-------= ---- tools/testing/selftests/arm64/fp/fp-ptrace.c | 17 ++++++++++--- tools/testing/selftests/arm64/fp/fp-ptrace.h | 10 ++++++++ 3 files changed, 41 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S b/tools/testi= ng/selftests/arm64/fp/fp-ptrace-asm.S index 7ad59d92d02b28e4a6b328fde96039329ea8862a..5e7e9c878f2ce797e3ba5f4033a= 42526830393e6 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S +++ b/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S @@ -15,10 +15,7 @@ =20 // Load and save register values with pauses for ptrace // -// x0 - SVE in use -// x1 - SME in use -// x2 - SME2 in use -// x3 - FA64 supported +// x0 - HAVE_ flags indicating which features are in use =20 .globl load_and_save load_and_save: @@ -44,7 +41,7 @@ load_and_save: ldp q30, q31, [x7, #16 * 30] =20 // SME? - cbz x1, check_sve_in + tbz x0, #HAVE_SME_SHIFT, check_sve_in =20 adrp x7, svcr_in ldr x7, [x7, :lo12:svcr_in] @@ -64,7 +61,7 @@ load_and_save: bne 1b =20 // ZT? - cbz x2, check_sm_in + tbz x0, #HAVE_SME2_SHIFT, check_sm_in adrp x6, zt_in add x6, x6, :lo12:zt_in _ldr_zt 6 @@ -72,12 +69,16 @@ load_and_save: // In streaming mode? check_sm_in: tbz x7, #SVCR_SM_SHIFT, check_sve_in - mov x4, x3 // Load FFR if we have FA64 + + // Load FFR if we have FA64 + mov x4, #0 + tbz x0, #HAVE_FA64_SHIFT, load_sve + mov x4, #1 b load_sve =20 // SVE? check_sve_in: - cbz x0, wait_for_writes + tbz x0, #HAVE_SVE_SHIFT, wait_for_writes mov x4, #1 =20 load_sve: @@ -165,8 +166,7 @@ wait_for_writes: stp q28, q29, [x7, #16 * 28] stp q30, q31, [x7, #16 * 30] =20 - // SME? - cbz x1, check_sve_out + tbz x0, #HAVE_SME_SHIFT, check_sve_out =20 rdsvl 11, 1 adrp x6, sme_vl_out @@ -187,7 +187,7 @@ wait_for_writes: bne 1b =20 // ZT? - cbz x2, check_sm_out + tbz x0, #HAVE_SME2_SHIFT, check_sm_out adrp x6, zt_out add x6, x6, :lo12:zt_out _str_zt 6 @@ -195,12 +195,16 @@ wait_for_writes: // In streaming mode? check_sm_out: tbz x7, #SVCR_SM_SHIFT, check_sve_out - mov x4, x3 // FFR? + + // Do we have FA64 and FFR? + mov x4, #0 + tbz x0, #HAVE_FA64_SHIFT, read_sve + mov x4, #1 b read_sve =20 // SVE? check_sve_out: - cbz x0, wait_for_reads + tbz x0, #HAVE_SVE_SHIFT, wait_for_reads mov x4, #1 =20 rdvl x7, #1 @@ -271,7 +275,7 @@ wait_for_reads: brk #0 =20 // Ensure we don't leave ourselves in streaming mode - cbz x1, out + tbz x0, #HAVE_SME_SHIFT, out msr S3_3_C4_C2_2, xzr =20 out: diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index c7ceafe5f4712b2c93823c1025f3a23ac0594325..d96af27487fa642e94ecc971f53= cb78c233e7b44 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -82,7 +82,7 @@ uint64_t sve_vl_out; uint64_t sme_vl_out; uint64_t svcr_in, svcr_expected, svcr_out; =20 -void load_and_save(int sve, int sme, int sme2, int fa64); +void load_and_save(int flags); =20 static bool got_alarm; =20 @@ -198,7 +198,7 @@ static int vl_expected(struct test_config *config) =20 static void run_child(struct test_config *config) { - int ret; + int ret, flags; =20 /* Let the parent attach to us */ ret =3D ptrace(PTRACE_TRACEME, 0, 0, 0); @@ -224,8 +224,17 @@ static void run_child(struct test_config *config) } =20 /* Load values and wait for the parent */ - load_and_save(sve_supported(), sme_supported(), - sme2_supported(), fa64_supported()); + flags =3D 0; + if (sve_supported()) + flags |=3D HAVE_SVE; + if (sme_supported()) + flags |=3D HAVE_SME; + if (sme2_supported()) + flags |=3D HAVE_SME2; + if (fa64_supported()) + flags |=3D HAVE_FA64; + + load_and_save(flags); =20 exit(0); } diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.h b/tools/testing/s= elftests/arm64/fp/fp-ptrace.h index db4f2c4d750c5c04e3d257e37a1966296ca74956..36ca627e1980f6a384d9ed0f2e9= d4bd32d90f893 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.h +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.h @@ -10,4 +10,14 @@ #define SVCR_SM (1 << SVCR_SM_SHIFT) #define SVCR_ZA (1 << SVCR_ZA_SHIFT) =20 +#define HAVE_SVE_SHIFT 0 +#define HAVE_SME_SHIFT 1 +#define HAVE_SME2_SHIFT 2 +#define HAVE_FA64_SHIFT 3 + +#define HAVE_SVE (1 << HAVE_SVE_SHIFT) +#define HAVE_SME (1 << HAVE_SME_SHIFT) +#define HAVE_SME2 (1 << HAVE_SME2_SHIFT) +#define HAVE_FA64 (1 << HAVE_FA64_SHIFT) + #endif --=20 2.39.5 From nobody Sat Nov 23 15:22:54 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DAA613C807; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NQqlaOzC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A504C4CED6; Tue, 12 Nov 2024 13:08:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731416912; bh=ADBvwCUOO5PzFobBknix6AUoJgfpspN/bImmNrGH1RY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NQqlaOzCcHY7WQnszum5TrNB1XKd11DNYw8lxjVX2bkVXTwa1MxeOQ30LCC5xXg2c eJtVPufkZD5Ipzf6l0DgZkog+o9V2KhiuebgoCjE24t9XPZpRcQiAiMX0ja5eDX9S+ C/NvKBsSfM3kCOHsCPDb0MVjXZMRmQZEj005nfLi5OBwZQrQymw0ShgeLk6+Z9sOOm ReWVDSSKZ5q/rgMyhj93ag7iPDzPXuetJZ2t9AKNrgCTQrdSm3QCAuqaQJ6pVAHVDe 4IPtOFe452Al4iIz2669VQmvp9UJ9z9edsBOW7zOpQLChljcilOYrZqvJwrpE2a9zo 899RfQ08oxU1g== From: Mark Brown Date: Tue, 12 Nov 2024 13:08:15 +0000 Subject: [PATCH v2 2/3] kselftest/arm64: Expand the set of ZA writes fp-ptrace does Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241112-arm64-fp-ptrace-fpmr-v2-2-250b57c61254@kernel.org> References: <20241112-arm64-fp-ptrace-fpmr-v2-0-250b57c61254@kernel.org> In-Reply-To: <20241112-arm64-fp-ptrace-fpmr-v2-0-250b57c61254@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-355e8 X-Developer-Signature: v=1; a=openpgp-sha256; l=1674; i=broonie@kernel.org; h=from:subject:message-id; bh=ADBvwCUOO5PzFobBknix6AUoJgfpspN/bImmNrGH1RY=; b=owGbwMvMwMWocq27KDak/QLjabUkhnTjYI/TscnsGw4p6T8rFpu/Z8a21dEC7N07L6+d3B7jz L1qaUZTJ6MxCwMjF4OsmCLL2mcZq9LDJbbOfzT/FcwgViaQKQxcnAIwkfKV7P/s2vhbJ01ISNP5 06LS6M3UzK+XfPbu2SeLLl98J8HxTkfCNlO/ylMrrvhRqu2MqDpDM9+q6CSOyfri60tK/nLUN1y z8clfrcDl/ceroyv97g/tbeLLAxZ1c6dM+LJ2ztm+JIZ1YcL1Sy5yTtn3MKDy5O5d608xVO6YGH mHb2a2RqtX3FaFE1zHHx4q/+ha98v5896SB2l1/ukZ8SwXJ5zWCzNS353de9W/tHpZtey09apcY apeipXa7+uLfYQZgpQr5tW2Tfe+ftKoe5FukWXtnU/f2f6c9DB2eeUpvLGjUmCq187zqob6y5jK +7OX1GlNa2RdLcFy0vnzqiSdPNfwm2vmGp9azv9czqsAAA== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Currently our test for implementable ZA writes is written in a bit of a convoluted fashion which excludes all changes where we clear SVCR.SM even though we can actually support that since changing the vector length resets SVCR. Make the logic more direct, enabling us to actually run these cases. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/fp-ptrace.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index d96af27487fa642e94ecc971f53cb78c233e7b44..56cf6e02c535b5c1cf1134c5b19= 73605c96024ee 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -1078,21 +1078,19 @@ static void sve_write(pid_t child, struct test_conf= ig *config) =20 static bool za_write_supported(struct test_config *config) { - if (config->svcr_expected & SVCR_SM) { - if (!(config->svcr_in & SVCR_SM)) + if (config->sme_vl_in !=3D config->sme_vl_expected) { + /* Changing the SME VL exits streaming mode. */ + if (config->svcr_expected & SVCR_SM) { return false; - - /* Changing the SME VL exits streaming mode */ - if (config->sme_vl_in !=3D config->sme_vl_expected) { + } + } else { + /* Otherwise we can't change streaming mode */ + if ((config->svcr_in & SVCR_SM) !=3D + (config->svcr_expected & SVCR_SM)) { return false; } } =20 - /* Can't disable SM outside a VL change */ - if ((config->svcr_in & SVCR_SM) && - !(config->svcr_expected & SVCR_SM)) - return false; - return true; } =20 --=20 2.39.5 From nobody Sat Nov 23 15:22:54 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6919E15688C; Tue, 12 Nov 2024 13:08:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731416915; cv=none; b=HkH8odAqiwdWnh7ZNnW12t8t4MOtGA8SXf7TT4ora704miK6hU78lqThbXybaUc3xDU+heKt8RZfVjvbRZtHYOEEr/zuieGmfpibQWGquFTQSZEALxnD8FgjECJnODs4P9e625KdjtL0XajFn2lsiD+wrc/H80T7te/Gav7hoPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731416915; c=relaxed/simple; bh=2gOyKvJrNoYV0gN7FdPkeZjJPBPgvem/G1SB7ge5K6k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LQG2b8spmyKdciGR0CBYhriadY86WQByhh2P6eTQDxt/2l15wgPyweaz3G6bNLf59N6wQD3w5ptdSEoJowGpKpyl9XzXpPo4EBsGYj/OdlRA9iNlBooWEOTcUi7Ea4nANnZkayAc65QcsWALcNPO0NBFkcZADlE5nZvqUvbDCtU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ajKAAbaG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ajKAAbaG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5660CC4CED5; Tue, 12 Nov 2024 13:08:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731416915; bh=2gOyKvJrNoYV0gN7FdPkeZjJPBPgvem/G1SB7ge5K6k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ajKAAbaGACkuXbjxxM/BfBLYXC5Tp5e6wBb7l5bnUvefFXCy4TYc6cweeCOi/yFX+ 8XW3JveVgQS2/tpg2VFon/Aj2KuXiVQGrrvcEsF7dcb6JXbNJewBl/QF3zIfD3pRY9 IE/eMVE9bdYRAmgr7UeT2BdGCa0wc2uOea0rZlrCE4ufNpxl8EleqUUAh5CENxAV6P urMCauDxqWEL8EWEeWZug2vqZ9XCFPpmfQkoL+yNHxiNLUsclIVrDmOyFFxqhaMtLu Km1nj1qJOXz8L3BDaTNcMSaV2RHdRkTuPu4nimOpufA4h/gkZcvOK/lzAhAbNxRmXt jiDquzO6wd+Qg== From: Mark Brown Date: Tue, 12 Nov 2024 13:08:16 +0000 Subject: [PATCH v2 3/3] kselftest/arm64: Add FPMR coverage to fp-ptrace Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241112-arm64-fp-ptrace-fpmr-v2-3-250b57c61254@kernel.org> References: <20241112-arm64-fp-ptrace-fpmr-v2-0-250b57c61254@kernel.org> In-Reply-To: <20241112-arm64-fp-ptrace-fpmr-v2-0-250b57c61254@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-355e8 X-Developer-Signature: v=1; a=openpgp-sha256; l=10366; i=broonie@kernel.org; h=from:subject:message-id; bh=2gOyKvJrNoYV0gN7FdPkeZjJPBPgvem/G1SB7ge5K6k=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnM1NJ7n/1qslnTpDexD783I3N0/3CJa25iJGYW ivh4g53yOKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZzNTSQAKCRAk1otyXVSH 0HdOB/9a1iojXt1HYxTYJI2eZB+j1/TYSVtduAxbeAEpZlyjooXtVleKcpGe0gNbXyb1qTCch+o Asgi8impochJFSc7sntVXsxQDNREmvRvtDoY2MibLJ6QPVkHOEYiAc/Z4/N07SFkfyUthm4pQIs 5i8NhEcj3pdDldhpPQejcASa3wgwlvZ4MUhU4uQpCk7hPhjUUeQMwVoNFiNVYWFwuSNjLXY4BIV e/SRVzvUP+DSXymmEMRcvXVirUgINpnYGNXQPnlCn9HRtc9Xx/cH/clh8ZpPrm/ush5M+/GcwPW rkhBvuNbzd4W89JWI/TpfMBzmSau+TcF4xg4ATyTaAsS5QCD X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add coverage for FPMR to fp-ptrace. FPMR can be available independently of SVE and SME, if SME is supported then FPMR is cleared by entering and exiting streaming mode. As with other registers we generate random values to load into the register, we restrict these to bitfields which are always defined. We also leave bitfields where the valid values are affected by the set of supported FP8 formats zero to reduce complexity, it is unlikely that specific bitfields will be affected by ptrace issues. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/fp-ptrace-asm.S | 23 +++-- tools/testing/selftests/arm64/fp/fp-ptrace.c | 126 +++++++++++++++++++= ++++ tools/testing/selftests/arm64/fp/fp-ptrace.h | 2 + tools/testing/selftests/arm64/fp/sme-inst.h | 2 + 4 files changed, 146 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S b/tools/testi= ng/selftests/arm64/fp/fp-ptrace-asm.S index 5e7e9c878f2ce797e3ba5f4033a42526830393e6..6195b9969d67e15d46ca71f1d27= 3b2d43ef4ae7a 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S +++ b/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S @@ -71,14 +71,12 @@ check_sm_in: tbz x7, #SVCR_SM_SHIFT, check_sve_in =20 // Load FFR if we have FA64 - mov x4, #0 - tbz x0, #HAVE_FA64_SHIFT, load_sve - mov x4, #1 + ubfx x4, x0, #HAVE_FA64_SHIFT, #1 b load_sve =20 // SVE? check_sve_in: - tbz x0, #HAVE_SVE_SHIFT, wait_for_writes + tbz x0, #HAVE_SVE_SHIFT, check_fpmr_in mov x4, #1 =20 load_sve: @@ -143,6 +141,13 @@ load_sve: ldr p14, [x7, #14, MUL VL] ldr p15, [x7, #15, MUL VL] =20 + // This has to come after we set PSTATE.SM +check_fpmr_in: + tbz x0, #HAVE_FPMR_SHIFT, wait_for_writes + adrp x7, fpmr_in + ldr x7, [x7, :lo12:fpmr_in] + msr FPMR, x7 + wait_for_writes: // Wait for the parent brk #0 @@ -166,6 +171,12 @@ wait_for_writes: stp q28, q29, [x7, #16 * 28] stp q30, q31, [x7, #16 * 30] =20 + tbz x0, #HAVE_FPMR_SHIFT, check_sme_out + mrs x7, REG_FPMR + adrp x6, fpmr_out + str x7, [x6, :lo12:fpmr_out] + +check_sme_out: tbz x0, #HAVE_SME_SHIFT, check_sve_out =20 rdsvl 11, 1 @@ -197,9 +208,7 @@ check_sm_out: tbz x7, #SVCR_SM_SHIFT, check_sve_out =20 // Do we have FA64 and FFR? - mov x4, #0 - tbz x0, #HAVE_FA64_SHIFT, read_sve - mov x4, #1 + ubfx x4, x0, #HAVE_FA64_SHIFT, #1 b read_sve =20 // SVE? diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index 56cf6e02c535b5c1cf1134c5b1973605c96024ee..4930e03a7b9903eab85a1e00435= 4939f6a9fe9d4 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -31,6 +31,14 @@ =20 #include "fp-ptrace.h" =20 +#include + +#define FPMR_LSCALE2_MASK GENMASK(37, 32) +#define FPMR_NSCALE_MASK GENMASK(31, 24) +#define FPMR_LSCALE_MASK GENMASK(22, 16) +#define FPMR_OSC_MASK GENMASK(15, 15) +#define FPMR_OSM_MASK GENMASK(14, 14) + /* and don't like each other, so: */ #ifndef NT_ARM_SVE #define NT_ARM_SVE 0x405 @@ -48,11 +56,22 @@ #define NT_ARM_ZT 0x40d #endif =20 +#ifndef NT_ARM_FPMR +#define NT_ARM_FPMR 0x40e +#endif + #define ARCH_VQ_MAX 256 =20 /* VL 128..2048 in powers of 2 */ #define MAX_NUM_VLS 5 =20 +/* + * FPMR bits we can set without doing feature checks to see if values + * are valid. + */ +#define FPMR_SAFE_BITS (FPMR_LSCALE2_MASK | FPMR_NSCALE_MASK | \ + FPMR_LSCALE_MASK | FPMR_OSC_MASK | FPMR_OSM_MASK) + #define NUM_FPR 32 __uint128_t v_in[NUM_FPR]; __uint128_t v_expected[NUM_FPR]; @@ -78,6 +97,8 @@ char zt_in[ZT_SIG_REG_BYTES]; char zt_expected[ZT_SIG_REG_BYTES]; char zt_out[ZT_SIG_REG_BYTES]; =20 +uint64_t fpmr_in, fpmr_expected, fpmr_out; + uint64_t sve_vl_out; uint64_t sme_vl_out; uint64_t svcr_in, svcr_expected, svcr_out; @@ -128,6 +149,11 @@ static bool fa64_supported(void) return getauxval(AT_HWCAP2) & HWCAP2_SME_FA64; } =20 +static bool fpmr_supported(void) +{ + return getauxval(AT_HWCAP2) & HWCAP2_FPMR; +} + static bool compare_buffer(const char *name, void *out, void *expected, size_t size) { @@ -233,6 +259,8 @@ static void run_child(struct test_config *config) flags |=3D HAVE_SME2; if (fa64_supported()) flags |=3D HAVE_FA64; + if (fpmr_supported()) + flags |=3D HAVE_FPMR; =20 load_and_save(flags); =20 @@ -321,6 +349,14 @@ static void read_child_regs(pid_t child) iov_child.iov_len =3D sizeof(zt_out); read_one_child_regs(child, "ZT", &iov_parent, &iov_child); } + + if (fpmr_supported()) { + iov_parent.iov_base =3D &fpmr_out; + iov_parent.iov_len =3D sizeof(fpmr_out); + iov_child.iov_base =3D &fpmr_out; + iov_child.iov_len =3D sizeof(fpmr_out); + read_one_child_regs(child, "FPMR", &iov_parent, &iov_child); + } } =20 static bool continue_breakpoint(pid_t child, @@ -595,6 +631,26 @@ static bool check_ptrace_values_zt(pid_t child, struct= test_config *config) return compare_buffer("initial ZT", buf, zt_in, ZT_SIG_REG_BYTES); } =20 +static bool check_ptrace_values_fpmr(pid_t child, struct test_config *conf= ig) +{ + uint64_t val; + struct iovec iov; + int ret; + + if (!fpmr_supported()) + return true; + + iov.iov_base =3D &val; + iov.iov_len =3D sizeof(val); + ret =3D ptrace(PTRACE_GETREGSET, child, NT_ARM_FPMR, &iov); + if (ret !=3D 0) { + ksft_print_msg("Failed to read initial FPMR: %s (%d)\n", + strerror(errno), errno); + return false; + } + + return compare_buffer("initial FPMR", &val, &fpmr_in, sizeof(val)); +} =20 static bool check_ptrace_values(pid_t child, struct test_config *config) { @@ -629,6 +685,9 @@ static bool check_ptrace_values(pid_t child, struct tes= t_config *config) if (!check_ptrace_values_zt(child, config)) pass =3D false; =20 + if (!check_ptrace_values_fpmr(child, config)) + pass =3D false; + return pass; } =20 @@ -832,11 +891,18 @@ static void set_initial_values(struct test_config *co= nfig) { int vq =3D __sve_vq_from_vl(vl_in(config)); int sme_vq =3D __sve_vq_from_vl(config->sme_vl_in); + bool sm_change; =20 svcr_in =3D config->svcr_in; svcr_expected =3D config->svcr_expected; svcr_out =3D 0; =20 + if (sme_supported() && + (svcr_in & SVCR_SM) !=3D (svcr_expected & SVCR_SM)) + sm_change =3D true; + else + sm_change =3D false; + fill_random(&v_in, sizeof(v_in)); memcpy(v_expected, v_in, sizeof(v_in)); memset(v_out, 0, sizeof(v_out)); @@ -883,6 +949,21 @@ static void set_initial_values(struct test_config *con= fig) memset(zt_expected, 0, ZT_SIG_REG_BYTES); memset(zt_out, 0, sizeof(zt_out)); } + + if (fpmr_supported()) { + fill_random(&fpmr_in, sizeof(fpmr_in)); + fpmr_in &=3D FPMR_SAFE_BITS; + + /* Entering or exiting streaming mode clears FPMR */ + if (sm_change) + fpmr_expected =3D 0; + else + fpmr_expected =3D fpmr_in; + } else { + fpmr_in =3D 0; + fpmr_expected =3D 0; + fpmr_out =3D 0; + } } =20 static bool check_memory_values(struct test_config *config) @@ -933,6 +1014,12 @@ static bool check_memory_values(struct test_config *c= onfig) if (!compare_buffer("saved ZT", zt_out, zt_expected, ZT_SIG_REG_BYTES)) pass =3D false; =20 + if (fpmr_out !=3D fpmr_expected) { + ksft_print_msg("Mismatch in saved FPMR: %lx !=3D %lx\n", + fpmr_out, fpmr_expected); + pass =3D false; + } + return pass; } =20 @@ -1010,6 +1097,36 @@ static void fpsimd_write(pid_t child, struct test_co= nfig *test_config) strerror(errno), errno); } =20 +static bool fpmr_write_supported(struct test_config *config) +{ + if (!fpmr_supported()) + return false; + + if (!sve_sme_same(config)) + return false; + + return true; +} + +static void fpmr_write_expected(struct test_config *config) +{ + fill_random(&fpmr_expected, sizeof(fpmr_expected)); + fpmr_expected &=3D FPMR_SAFE_BITS; +} + +static void fpmr_write(pid_t child, struct test_config *config) +{ + struct iovec iov; + int ret; + + iov.iov_len =3D sizeof(fpmr_expected); + iov.iov_base =3D &fpmr_expected; + ret =3D ptrace(PTRACE_SETREGSET, child, NT_ARM_FPMR, &iov); + if (ret !=3D 0) + ksft_print_msg("Failed to write FPMR: %s (%d)\n", + strerror(errno), errno); +} + static void sve_write_expected(struct test_config *config) { int vl =3D vl_expected(config); @@ -1266,6 +1383,12 @@ static struct test_definition base_test_defs[] =3D { .set_expected_values =3D fpsimd_write_expected, .modify_values =3D fpsimd_write, }, + { + .name =3D "FPMR write", + .supported =3D fpmr_write_supported, + .set_expected_values =3D fpmr_write_expected, + .modify_values =3D fpmr_write, + }, }; =20 static struct test_definition sve_test_defs[] =3D { @@ -1475,6 +1598,9 @@ int main(void) if (fa64_supported()) ksft_print_msg("FA64 supported\n"); =20 + if (fpmr_supported()) + ksft_print_msg("FPMR supported\n"); + ksft_set_plan(tests); =20 /* Get signal handers ready before we start any children */ diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.h b/tools/testing/s= elftests/arm64/fp/fp-ptrace.h index 36ca627e1980f6a384d9ed0f2e9d4bd32d90f893..c06919aaf1f70bee4b607f71e32= 13ef2ddf8b97d 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.h +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.h @@ -14,10 +14,12 @@ #define HAVE_SME_SHIFT 1 #define HAVE_SME2_SHIFT 2 #define HAVE_FA64_SHIFT 3 +#define HAVE_FPMR_SHIFT 4 =20 #define HAVE_SVE (1 << HAVE_SVE_SHIFT) #define HAVE_SME (1 << HAVE_SME_SHIFT) #define HAVE_SME2 (1 << HAVE_SME2_SHIFT) #define HAVE_FA64 (1 << HAVE_FA64_SHIFT) +#define HAVE_FPMR (1 << HAVE_FPMR_SHIFT) =20 #endif diff --git a/tools/testing/selftests/arm64/fp/sme-inst.h b/tools/testing/se= lftests/arm64/fp/sme-inst.h index 9292bba5400bb81b8e34769fa3eb70811746d8b8..85b9184e0835c59dbd5674b0210= e6b9a43c1be4c 100644 --- a/tools/testing/selftests/arm64/fp/sme-inst.h +++ b/tools/testing/selftests/arm64/fp/sme-inst.h @@ -5,6 +5,8 @@ #ifndef SME_INST_H #define SME_INST_H =20 +#define REG_FPMR S3_3_C4_C4_2 + /* * RDSVL X\nx, #\imm */ --=20 2.39.5