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Tue, 12 Nov 2024 11:49:00 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ACBn0we028725 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Nov 2024 11:49:00 GMT Received: from hu-renjiang-sha.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 12 Nov 2024 03:48:56 -0800 From: Renjiang Han Date: Tue, 12 Nov 2024 17:17:57 +0530 Subject: [PATCH v2 1/4] dt-bindings: qcom,qcs615-venus: document QCS615 venus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241112-add-venus-for-qcs615-v2-1-e67947f957af@quicinc.com> References: <20241112-add-venus-for-qcs615-v2-0-e67947f957af@quicinc.com> In-Reply-To: <20241112-add-venus-for-qcs615-v2-0-e67947f957af@quicinc.com> To: Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: , , , , Renjiang Han X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Renjiang Han --- .../bindings/media/qcom,qcs615-venus.yaml | 181 +++++++++++++++++= ++++ 1 file changed, 181 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,qcs615-venus.yaml= b/Documentation/devicetree/bindings/media/qcom,qcs615-venus.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a807f4c7e94c635ef1662971b68= 7db9bdce1b74a --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcs615-venus.yaml @@ -0,0 +1,181 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcs615-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS615 Venus video encode and decode accelerators + +maintainers: + - Stanimir Varbanov + - Vikash Garodia + +description: | + The Venus IP is a video encode and decode accelerator present + on Qualcomm platforms + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + const: qcom,qcs615-venus + + power-domains: + minItems: 2 + maxItems: 3 + + power-domain-names: + minItems: 2 + items: + - const: venus + - const: vcodec0 + - const: cx + + clocks: + maxItems: 5 + + clock-names: + items: + - const: core + - const: iface + - const: bus + - const: vcodec0_core + - const: vcodec0_bus + + iommus: + maxItems: 1 + + memory-region: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: video-mem + - const: cpu-cfg + + operating-points-v2: true + opp-table: + type: object + + video-decoder: + type: object + + properties: + compatible: + const: venus-decoder + + required: + - compatible + + additionalProperties: false + + video-encoder: + type: object + + properties: + compatible: + const: venus-encoder + + required: + - compatible + + additionalProperties: false + +required: + - compatible + - power-domain-names + - iommus + - video-decoder + - video-encoder + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + venus: video-codec@aa00000 { + compatible =3D "qcom,qcs615-venus"; + reg =3D <0xaa00000 0x100000>; + interrupts =3D ; + + clocks =3D <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; + clock-names =3D "core", + "iface", + "bus", + "vcodec0_core", + "vcodec0_bus"; + + power-domains =3D <&videocc VENUS_GDSC>, + <&videocc VCODEC0_GDSC>, + <&rpmhpd RPMHPD_CX>; + power-domain-names =3D "venus", + "vcodec0", + "cx"; + + operating-points-v2 =3D <&venus_opp_table>; + + interconnects =3D <&mmss_noc MASTER_VIDEO_P0 0 + &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_VENUS_CFG 0>; + interconnect-names =3D "video-mem", + "cpu-cfg"; + + iommus =3D <&apps_smmu 0xe40 0x20>; + + memory-region =3D <&pil_video_mem>; + + video-decoder { + compatible =3D "venus-decoder"; + }; + + video-encoder { + compatible =3D "venus-encoder"; + }; + + venus_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-133330000 { + opp-hz =3D /bits/ 64 <133330000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-380000000 { + opp-hz =3D /bits/ 64 <380000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-410000000 { + opp-hz =3D /bits/ 64 <410000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; --=20 2.34.1 From nobody Sat Nov 23 15:57:01 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 596341F77BF; Tue, 12 Nov 2024 11:49:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Renjiang Han Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/venus/core.c | 50 ++++++++++++++++++++++++++++= ++++ 1 file changed, 50 insertions(+) diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platf= orm/qcom/venus/core.c index 423deb5e94dcb193974da23f9bd2d905bfeab2d9..39d8bcf62fe4f72674746b75994= cce6cbaee94eb 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -630,6 +630,55 @@ static const struct venus_resources msm8998_res =3D { .fwname =3D "qcom/venus-4.4/venus.mbn", }; =20 +static const struct freq_tbl qcs615_freq_table[] =3D { + { 0, 460000000 }, + { 0, 410000000 }, + { 0, 380000000 }, + { 0, 300000000 }, + { 0, 240000000 }, + { 0, 133333333 }, +}; + +static const struct bw_tbl qcs615_bw_table_enc[] =3D { + { 972000, 951000, 0, 1434000, 0 }, /* 3840x2160@30 */ + { 489600, 723000, 0, 973000, 0 }, /* 1920x1080@60 */ + { 244800, 370000, 0, 495000, 0 }, /* 1920x1080@30 */ +}; + +static const struct bw_tbl qcs615_bw_table_dec[] =3D { + { 1036800, 1987000, 0, 2797000, 0 }, /* 4096x2160@30 */ + { 489600, 1040000, 0, 1298000, 0 }, /* 1920x1080@60 */ + { 244800, 530000, 0, 659000, 0 }, /* 1920x1080@30 */ +}; + +static const struct venus_resources qcs615_res =3D { + .freq_tbl =3D qcs615_freq_table, + .freq_tbl_size =3D ARRAY_SIZE(qcs615_freq_table), + .bw_tbl_enc =3D qcs615_bw_table_enc, + .bw_tbl_enc_size =3D ARRAY_SIZE(qcs615_bw_table_enc), + .bw_tbl_dec =3D qcs615_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(qcs615_bw_table_dec), + .clks =3D {"core", "iface", "bus" }, + .clks_num =3D 3, + .vcodec0_clks =3D { "vcodec0_core", "vcodec0_bus" }, + .vcodec_clks_num =3D 2, + .vcodec_pmdomains =3D (const char *[]) { "venus", "vcodec0" }, + .vcodec_pmdomains_num =3D 2, + .opp_pmdomain =3D (const char *[]) { "cx" }, + .vcodec_num =3D 1, + .hfi_version =3D HFI_VERSION_4XX, + .vpu_version =3D VPU_VERSION_AR50, + .vmem_id =3D VIDC_RESOURCE_NONE, + .vmem_size =3D 0, + .vmem_addr =3D 0, + .dma_mask =3D 0xe0000000 - 1, + .cp_start =3D 0, + .cp_size =3D 0x70800000, + .cp_nonpixel_start =3D 0x1000000, + .cp_nonpixel_size =3D 0x24800000, + .fwname =3D "qcom/venus-5.4/venus_s6.mbn", +}; + static const struct freq_tbl sdm660_freq_table[] =3D { { 979200, 518400000 }, { 489600, 441600000 }, @@ -937,6 +986,7 @@ static const struct of_device_id venus_dt_match[] =3D { { .compatible =3D "qcom,msm8916-venus", .data =3D &msm8916_res, }, { .compatible =3D "qcom,msm8996-venus", .data =3D &msm8996_res, }, { .compatible =3D "qcom,msm8998-venus", .data =3D &msm8998_res, }, + { .compatible =3D "qcom,qcs615-venus", .data =3D &qcs615_res, }, { .compatible =3D "qcom,sdm660-venus", .data =3D &sdm660_res, }, { .compatible =3D "qcom,sdm845-venus", .data =3D &sdm845_res, }, { .compatible =3D "qcom,sdm845-venus-v2", .data =3D &sdm845_res_v2, }, --=20 2.34.1 From nobody Sat Nov 23 15:57:01 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFFDC230989; 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Signed-off-by: Renjiang Han Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 06deb5c499fe83f0eb20d7957ca14948de7aab34..18ad4da5ed194458aded424560f= 45a3a9f3163dc 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -394,6 +394,11 @@ smem_region: smem@86000000 { no-map; hwlocks =3D <&tcsr_mutex 3>; }; + + pil_video_mem: pil-video@93400000 { + reg =3D <0x0 0x93400000 0x0 0x500000>; + no-map; + }; }; =20 soc: soc@0 { @@ -530,6 +535,87 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + venus: video-codec@aa00000 { + compatible =3D "qcom,qcs615-venus"; + reg =3D <0x0 0xaa00000 0x0 0x100000>; + interrupts =3D ; + + clocks =3D <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; + clock-names =3D "core", + "iface", + "bus", + "vcodec0_core", + "vcodec0_bus"; + + power-domains =3D <&videocc VENUS_GDSC>, + <&videocc VCODEC0_GDSC>, + <&rpmhpd RPMHPD_CX>; + power-domain-names =3D "venus", + "vcodec0", + "cx"; + + operating-points-v2 =3D <&venus_opp_table>; + + interconnects =3D <&mmss_noc MASTER_VIDEO_P0 0 + &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_VENUS_CFG 0>; + interconnect-names =3D "video-mem", + "cpu-cfg"; + + iommus =3D <&apps_smmu 0xe40 0x20>; + + memory-region =3D <&pil_video_mem>; + + status =3D "disabled"; + + video-decoder { + compatible =3D "venus-decoder"; + }; + + video-encoder { + compatible =3D "venus-encoder"; + }; + + venus_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-133330000 { + opp-hz =3D /bits/ 64 <133330000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; 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Signed-off-by: Renjiang Han Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index 4ef969a6af150933c72a7a83374a5a2657eebc1b..4a7bfffb7b86b21c412b1642601= 9c9063368ca19 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -217,6 +217,10 @@ &uart0 { status =3D "okay"; }; =20 +&venus { + status =3D "okay"; +}; + &watchdog { clocks =3D <&sleep_clk>; }; --=20 2.34.1