From nobody Sat Nov 23 17:20:34 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23D742141CC; Tue, 12 Nov 2024 10:27:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731407222; cv=none; b=DDxd9HalBaun5874N8YThC6di30cG70fshn8AL2yr/HTP+6L1dUhsb7R+j79RoPkYeEPGQTBngIc0VNb9nKPdUrF2iXyC6lgqmmtUr4gxF47PId3oo08MtRsBWN9Nkfb1R+psrhx5ejZN3sI5a6xRjCGKgBcmYn5JK3TimmG0MA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731407222; c=relaxed/simple; bh=D/M0/A3lpkOUWkgP+FbRFsJh3b6bYgyAz3r/L66iK5U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nUiErf8lzGP0DiEvIJ9gNJWiNZOeWnwKeByQjgCvnXvxRhW8QylY2726FDSkaZzkDnaVve/GOB6QRBt3KNk6CgaQCUVAG+05K1P4NWgM2p239d+OQz/H/f5SxOYkknrSlAun5aP06InW9bKkReDBAaSgKlXlDlHl4Osg4rNZCHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UbRW3gYF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UbRW3gYF" Received: by smtp.kernel.org (Postfix) with ESMTPS id B4D6BC4CED7; Tue, 12 Nov 2024 10:27:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731407221; bh=D/M0/A3lpkOUWkgP+FbRFsJh3b6bYgyAz3r/L66iK5U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UbRW3gYFoPzhsSp3AddNltboro3niP6XarNVfTo7qzo0rxWWgUm2wyPh7xNaVgYBQ BakM7gWrmvdydq7y/sP5GeXyA9iv8O50NP98YEwnY8ZHAJ2NXxpx5NirF9jP4+0pZm CvyQFUA4FNTh3WSUPkN4/zlBpJojhsBDzbZ4zWsiZVsHZIlZbCWQ0eZqcrbuiIPoTT Irme0CbWI5M/3Wm5cJy/upyvN7V9EwVyPP9YpLNbU+H/ZUl7e+4pbYLPSv6ScAKRVP 35oqcl36rUnFoM2cVXv9QLmFb7KdlQ5uRaEspvUhX0Hrjk1TUMP8mfxfhwpq3qG9md sQXXdWl4vgpFA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A56E0D32D8D; Tue, 12 Nov 2024 10:27:01 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 12 Nov 2024 18:26:56 +0800 Subject: [PATCH v5 2/5] dt-bindings: pinctrl: Add support for Amlogic A4 SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241112-a4_pinctrl-v5-2-3460ce10c480@amlogic.com> References: <20241112-a4_pinctrl-v5-0-3460ce10c480@amlogic.com> In-Reply-To: <20241112-a4_pinctrl-v5-0-3460ce10c480@amlogic.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731407219; l=2582; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=uO4TJ2ja77acTbAqMRXIRWimmcaql9Ax5+y2igpzZwU=; b=kgdeyuL6lEctCLbfExo6Bnu7GSA/W0Nx4PY3zuhgWy9uBoBeFBleplnEKVhzLbq66GFX832GU 2HuIu4MfGemAK18lIX0Fz1eLT8rVSh1nwpQWMw0LLj0LdO0J22AOGZP X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Add the new compatible name for Amlogic A4 pin controller, and add a new dt-binding header file which document the GPIO bank names of all Amlogic subsequent SoCs. Acked-by: Rob Herring (Arm) Signed-off-by: Xianwei Zhao --- .../bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml | 2 + include/dt-bindings/gpio/amlogic-gpio.h | 45 ++++++++++++++++++= ++++ 2 files changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctr= l-a1.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl= -a1.yaml index d9e0b2c48e84..f5eefa0fab5b 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.ya= ml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.ya= ml @@ -15,6 +15,8 @@ allOf: properties: compatible: enum: + - amlogic,a4-aobus-pinctrl + - amlogic,a4-periphs-pinctrl - amlogic,c3-periphs-pinctrl - amlogic,t7-periphs-pinctrl - amlogic,meson-a1-periphs-pinctrl diff --git a/include/dt-bindings/gpio/amlogic-gpio.h b/include/dt-bindings/= gpio/amlogic-gpio.h new file mode 100644 index 000000000000..5bfdb39eeda8 --- /dev/null +++ b/include/dt-bindings/gpio/amlogic-gpio.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Xianwei Zhao + */ + +#ifndef _DT_BINDINGS_AMLOGIC_GPIO_H +#define _DT_BINDINGS_AMLOGIC_GPIO_H + +#include + +/* Normal GPIO bank */ +#define AMLOGIC_GPIO_A 0 +#define AMLOGIC_GPIO_B 1 +#define AMLOGIC_GPIO_C 2 +#define AMLOGIC_GPIO_D 3 +#define AMLOGIC_GPIO_E 4 +#define AMLOGIC_GPIO_F 5 +#define AMLOGIC_GPIO_G 6 +#define AMLOGIC_GPIO_H 7 +#define AMLOGIC_GPIO_I 8 +#define AMLOGIC_GPIO_J 9 +#define AMLOGIC_GPIO_K 10 +#define AMLOGIC_GPIO_L 11 +#define AMLOGIC_GPIO_M 12 +#define AMLOGIC_GPIO_N 13 +#define AMLOGIC_GPIO_O 14 +#define AMLOGIC_GPIO_P 15 +#define AMLOGIC_GPIO_Q 16 +#define AMLOGIC_GPIO_R 17 +#define AMLOGIC_GPIO_S 18 +#define AMLOGIC_GPIO_T 19 +#define AMLOGIC_GPIO_U 20 +#define AMLOGIC_GPIO_V 21 +#define AMLOGIC_GPIO_W 22 +#define AMLOGIC_GPIO_X 23 +#define AMLOGIC_GPIO_Y 24 +#define AMLOGIC_GPIO_Z 25 +/* Special GPIO bank */ +#define AMLOGIC_GPIO_DV 26 +#define AMLOGIC_GPIO_AO 27 +#define AMLOGIC_GPIO_CC 28 +#define AMLOGIC_GPIO_TEST_N 29 + +#endif /* _DT_BINDINGS_AMLOGIC_GPIO_H */ --=20 2.37.1