From nobody Sat Nov 23 22:59:15 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 686AF1A01C6; Mon, 11 Nov 2024 14:03:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731333810; cv=none; b=r9TnC0mzvxDUAIC9/xjj1/3Up1Wf8X/mEcGYqP2caUb1gKOqpLmYOddWnwUzQIB721Q1xFWZYiwQHmnC8uahkd1vYlzgwl9pvV1+/fH3t0qYJRWLATOxxOtnb1KW0NN7XcKqNkmtBRbDey5Tj3GFDYvhjlKVMweFLF/kw7wMOUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731333810; c=relaxed/simple; bh=gQcFxx3pnBO/GO+JGIlO3BkTnnRua6rqfLo2BlWyXv8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rcyZ06pXwE/4TwXZV4TeMLT7Yh2KEAUgUh5SZYuVVYAXr5RK7SwZmMohM6TykI2GUJKLzdsOqY8UKfei6M1vlk0HbgupZExyLDz5es6iOWo+I3H7WQiAqFGIjl2YrdHEEtBN703svUYI+D+5HKO9eKTe39IpiXVzMXCjZegG/Jw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Etm1keFl; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Etm1keFl" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ABC9fwC002327; Mon, 11 Nov 2024 14:03:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=taSydBJMBWIg5c2/q1Rx92ov l65hfz0H1XM2bzk0f5g=; b=Etm1keFlLNdGztjgxrc/Saz8huWlgnx5Qxk7MJqn QUW/WWwFak5JdRI60yMEE+JtLp3OUKCDtbof7weR8Tim/AGoVFc6aLrTAMgJH/Vm 5/bmj8ym4edadIyc6t9JgEAmZnR3NP8UJqlXA63lB+sYtyrLMp55ftqIOPt4nXbC 90owSlVf3z0d9JleUX0VEjvCxxmyeYEE58kfLDUAFPSbbjC5UVUxJT5ZEAcsEAS4 LkrdARI5yc479s5BTiw1tzj6aw1bTLi6GKlsLQMaCMmrQpdrURm1b1T5jzia7MAp aIwMD3XptU/+OTRPMh+Tk0pIPEQcplB/vfbkAMV/0H0soQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42syy24bqe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Nov 2024 14:03:23 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ABE3M0W017579 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Nov 2024 14:03:22 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 11 Nov 2024 06:03:18 -0800 From: Jyothi Kumar Seerapu To: Vinod Koul , Andi Shyti , "Sumit Semwal" , =?UTF-8?q?Christian=20K=C3=B6nig?= CC: , , , , , , , , Subject: [PATCH v2 RESEND 3/3] i2c: i2c-qcom-geni: Add Block event interrupt support Date: Mon, 11 Nov 2024 19:32:44 +0530 Message-ID: <20241111140244.13474-4-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241111140244.13474-1-quic_jseerapu@quicinc.com> References: <20241111140244.13474-1-quic_jseerapu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: NVmfUTTbEXxU1PrVVYwetQOpmPzdxBVc X-Proofpoint-ORIG-GUID: NVmfUTTbEXxU1PrVVYwetQOpmPzdxBVc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411110116 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The I2C driver gets an interrupt upon transfer completion. For multiple messages in a single transfer, N interrupts will be received for N messages, leading to significant software interrupt latency. To mitigate this latency, utilize Block Event Interrupt (BEI) only when an interrupt is necessary. This means large transfers can be split into multiple chunks of 8 messages internally, without expecting interrupts for the first 7 message completions, only the last one will trigger an interrupt indicating 8 messages completed. By implementing BEI, multi-message transfers can be divided into chunks of 8 messages, improving overall transfer time. This optimization reduces transfer time from 168 ms to 48 ms for a series of 200 I2C write messages in a single transfer, with a clock frequency support of 100 kHz. BEI optimizations are currently implemented for I2C write transfers only, as there is no use case for multiple I2C read messages in a single transfer at this time. Signed-off-by: Jyothi Kumar Seerapu --- v1 -> v2: - Moved gi2c_gpi_xfer->msg_idx_cnt to separate local variable. - Updated goto labels for error scenarios in geni_i2c_gpi function - memset tx_multi_xfer to 0. - Removed passing current msg index to geni_i2c_gpi. - Fixed kernel test robot reported compilation issues. =20 drivers/i2c/busses/i2c-qcom-geni.c | 203 +++++++++++++++++++++++++---- 1 file changed, 178 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 7a22e1f46e60..04a7d926dadc 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -100,6 +100,10 @@ struct geni_i2c_dev { struct dma_chan *rx_c; bool gpi_mode; bool abort_done; + bool is_tx_multi_xfer; + u32 num_msgs; + u32 tx_irq_cnt; + struct gpi_i2c_config *gpi_config; }; =20 struct geni_i2c_desc { @@ -500,6 +504,7 @@ static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2= c, struct i2c_msg *msg, static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *res= ult) { struct geni_i2c_dev *gi2c =3D cb; + struct gpi_multi_xfer *tx_multi_xfer; =20 if (result->result !=3D DMA_TRANS_NOERROR) { dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); @@ -508,7 +513,21 @@ static void i2c_gpi_cb_result(void *cb, const struct d= maengine_result *result) dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); } =20 - complete(&gi2c->done); + if (gi2c->is_tx_multi_xfer) { + tx_multi_xfer =3D &gi2c->gpi_config->multi_xfer; + + /* + * Send Completion for last message or multiple of NUM_MSGS_PER_IRQ. + */ + if ((tx_multi_xfer->irq_msg_cnt =3D=3D gi2c->num_msgs - 1) || + (!((tx_multi_xfer->irq_msg_cnt + 1) % NUM_MSGS_PER_IRQ))) { + tx_multi_xfer->irq_cnt++; + complete(&gi2c->done); + } + tx_multi_xfer->irq_msg_cnt++; + } else { + complete(&gi2c->done); + } } =20 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *= msg, @@ -526,7 +545,42 @@ static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi= 2c, struct i2c_msg *msg, } } =20 -static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, +/** + * gpi_i2c_multi_desc_unmap() - unmaps the buffers post multi message TX t= ransfers + * @dev: pointer to the corresponding dev node + * @gi2c: i2c dev handle + * @msgs: i2c messages array + * @peripheral: pointer to the gpi_i2c_config + */ +static void gpi_i2c_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c= _msg msgs[], + struct gpi_i2c_config *peripheral) +{ + u32 msg_xfer_cnt, wr_idx =3D 0; + struct gpi_multi_xfer *tx_multi_xfer =3D &peripheral->multi_xfer; + + /* + * In error case, need to unmap all messages based on the msg_idx_cnt. + * Non-error case unmap all the processed messages. + */ + if (gi2c->err) + msg_xfer_cnt =3D tx_multi_xfer->msg_idx_cnt; + else + msg_xfer_cnt =3D tx_multi_xfer->irq_cnt * NUM_MSGS_PER_IRQ; + + /* Unmap the processed DMA buffers based on the received interrupt count = */ + for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_= msg_cnt++) { + if (tx_multi_xfer->unmap_msg_cnt =3D=3D gi2c->num_msgs) + break; + wr_idx =3D tx_multi_xfer->unmap_msg_cnt % QCOM_GPI_MAX_NUM_MSGS; + geni_i2c_gpi_unmap(gi2c, &msgs[tx_multi_xfer->unmap_msg_cnt], + tx_multi_xfer->dma_buf[wr_idx], + tx_multi_xfer->dma_addr[wr_idx], + NULL, (dma_addr_t)NULL); + tx_multi_xfer->freed_msg_cnt++; + } +} + +static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], struct dma_slave_config *config, dma_addr_t *dma_addr_p, void **buf, unsigned int op, struct dma_chan *dma_chan) { @@ -538,26 +592,48 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, st= ruct i2c_msg *msg, enum dma_transfer_direction dma_dirn; struct dma_async_tx_descriptor *desc; int ret; + struct gpi_multi_xfer *gi2c_gpi_xfer; + dma_cookie_t cookie; + u32 msg_idx; =20 peripheral =3D config->peripheral_config; - - dma_buf =3D i2c_get_dma_safe_msg_buf(msg, 1); - if (!dma_buf) - return -ENOMEM; + gi2c_gpi_xfer =3D &peripheral->multi_xfer; + dma_buf =3D gi2c_gpi_xfer->dma_buf[gi2c_gpi_xfer->buf_idx]; + addr =3D gi2c_gpi_xfer->dma_addr[gi2c_gpi_xfer->buf_idx]; + msg_idx =3D gi2c_gpi_xfer->msg_idx_cnt; + + dma_buf =3D i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1); + if (!dma_buf) { + ret =3D -ENOMEM; + goto out; + } =20 if (op =3D=3D I2C_WRITE) map_dirn =3D DMA_TO_DEVICE; else map_dirn =3D DMA_FROM_DEVICE; =20 - addr =3D dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn= ); + addr =3D dma_map_single(gi2c->se.dev->parent, dma_buf, + msgs[msg_idx].len, map_dirn); if (dma_mapping_error(gi2c->se.dev->parent, addr)) { - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - return -ENOMEM; + i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); + ret =3D -ENOMEM; + goto out; + } + + if (gi2c->is_tx_multi_xfer) { + if (((msg_idx + 1) % NUM_MSGS_PER_IRQ)) + peripheral->flags |=3D QCOM_GPI_BLOCK_EVENT_IRQ; + else + peripheral->flags &=3D ~QCOM_GPI_BLOCK_EVENT_IRQ; + + /* BEI bit to be cleared for last TRE */ + if (msg_idx =3D=3D gi2c->num_msgs - 1) + peripheral->flags &=3D ~QCOM_GPI_BLOCK_EVENT_IRQ; } =20 /* set the length as message for rx txn */ - peripheral->rx_len =3D msg->len; + peripheral->rx_len =3D msgs[msg_idx].len; peripheral->op =3D op; =20 ret =3D dmaengine_slave_config(dma_chan, config); @@ -575,7 +651,8 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, stru= ct i2c_msg *msg, else dma_dirn =3D DMA_DEV_TO_MEM; =20 - desc =3D dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, = flags); + desc =3D dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, + dma_dirn, flags); if (!desc) { dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); ret =3D -EIO; @@ -585,15 +662,48 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, st= ruct i2c_msg *msg, desc->callback_result =3D i2c_gpi_cb_result; desc->callback_param =3D gi2c; =20 - dmaengine_submit(desc); - *buf =3D dma_buf; - *dma_addr_p =3D addr; + if (!((msgs[msg_idx].flags & I2C_M_RD) && op =3D=3D I2C_WRITE)) { + gi2c_gpi_xfer->msg_idx_cnt++; + gi2c_gpi_xfer->buf_idx =3D (msg_idx + 1) % QCOM_GPI_MAX_NUM_MSGS; + } + cookie =3D dmaengine_submit(desc); + if (dma_submit_error(cookie)) { + dev_err(gi2c->se.dev, + "%s: dmaengine_submit failed (%d)\n", __func__, cookie); + ret =3D -EINVAL; + goto err_config; + } =20 + if (gi2c->is_tx_multi_xfer) { + dma_async_issue_pending(gi2c->tx_c); + if ((msg_idx =3D=3D (gi2c->num_msgs - 1)) || + (gi2c_gpi_xfer->msg_idx_cnt >=3D + QCOM_GPI_MAX_NUM_MSGS + gi2c_gpi_xfer->freed_msg_cnt)) { + ret =3D gpi_multi_desc_process(gi2c->se.dev, gi2c_gpi_xfer, + gi2c->num_msgs, XFER_TIMEOUT, + &gi2c->done); + if (ret) { + dev_err(gi2c->se.dev, + "I2C multi write msg transfer timeout: %d\n", + ret); + gi2c->err =3D ret; + goto err_config; + } + } + } else { + /* Non multi descriptor message transfer */ + *buf =3D dma_buf; + *dma_addr_p =3D addr; + } return 0; =20 err_config: - dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn); - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); + dma_unmap_single(gi2c->se.dev->parent, addr, + msgs[msg_idx].len, map_dirn); + i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); + +out: + gi2c->err =3D ret; return ret; } =20 @@ -605,6 +715,7 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c,= struct i2c_msg msgs[], i unsigned long time_left; dma_addr_t tx_addr, rx_addr; void *tx_buf =3D NULL, *rx_buf =3D NULL; + struct gpi_multi_xfer *tx_multi_xfer; const struct geni_i2c_clk_fld *itr =3D gi2c->clk_fld; =20 config.peripheral_config =3D &peripheral; @@ -618,6 +729,34 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c= , struct i2c_msg msgs[], i peripheral.set_config =3D 1; peripheral.multi_msg =3D false; =20 + gi2c->gpi_config =3D &peripheral; + gi2c->num_msgs =3D num; + gi2c->is_tx_multi_xfer =3D false; + gi2c->tx_irq_cnt =3D 0; + + tx_multi_xfer =3D &peripheral.multi_xfer; + memset(tx_multi_xfer, 0, sizeof(struct gpi_multi_xfer)); + + /* + * If number of write messages are four and higher then + * configure hardware for multi descriptor transfers with BEI. + */ + if (num >=3D MIN_NUM_OF_MSGS_MULTI_DESC) { + gi2c->is_tx_multi_xfer =3D true; + for (i =3D 0; i < num; i++) { + if (msgs[i].flags & I2C_M_RD) { + /* + * Multi descriptor transfer with BEI + * support is enabled for write transfers. + * Add BEI optimization support for read + * transfers later. + */ + gi2c->is_tx_multi_xfer =3D false; + break; + } + } + } + for (i =3D 0; i < num; i++) { gi2c->cur =3D &msgs[i]; gi2c->err =3D 0; @@ -628,14 +767,16 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2= c, struct i2c_msg msgs[], i peripheral.stretch =3D 1; =20 peripheral.addr =3D msgs[i].addr; + if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) + peripheral.multi_msg =3D false; =20 - ret =3D geni_i2c_gpi(gi2c, &msgs[i], &config, + ret =3D geni_i2c_gpi(gi2c, msgs, &config, &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); if (ret) goto err; =20 if (msgs[i].flags & I2C_M_RD) { - ret =3D geni_i2c_gpi(gi2c, &msgs[i], &config, + ret =3D geni_i2c_gpi(gi2c, msgs, &config, &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); if (ret) goto err; @@ -643,18 +784,26 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2= c, struct i2c_msg msgs[], i dma_async_issue_pending(gi2c->rx_c); } =20 - dma_async_issue_pending(gi2c->tx_c); - - time_left =3D wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); - if (!time_left) - gi2c->err =3D -ETIMEDOUT; + if (!gi2c->is_tx_multi_xfer) { + dma_async_issue_pending(gi2c->tx_c); + time_left =3D wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); + if (!time_left) { + dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__); + gi2c->err =3D -ETIMEDOUT; + } + } =20 if (gi2c->err) { ret =3D gi2c->err; goto err; } =20 - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); + if (!gi2c->is_tx_multi_xfer) { + geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); + } else if (gi2c->tx_irq_cnt !=3D tx_multi_xfer->irq_cnt) { + gi2c->tx_irq_cnt =3D tx_multi_xfer->irq_cnt; + gpi_i2c_multi_desc_unmap(gi2c, msgs, &peripheral); + } } =20 return num; @@ -663,7 +812,11 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c= , struct i2c_msg msgs[], i dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); dmaengine_terminate_sync(gi2c->rx_c); dmaengine_terminate_sync(gi2c->tx_c); - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); + if (gi2c->is_tx_multi_xfer) + gpi_i2c_multi_desc_unmap(gi2c, msgs, &peripheral); + else + geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); + return ret; } =20 --=20 2.17.1