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Mon, 11 Nov 2024 12:09:57 +0000 From: Bhavin Sharma To: alexander.deucher@amd.com Cc: tarang.raval@siliconsignals.io, Bhavin Sharma , Chaitanya Dhere , Jun Lei , Harry Wentland , Leo Li , Rodrigo Siqueira , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Kenneth Feng , Wenjing Liu , Roman Li , Alex Hung , Leo Ma , Jose Fernandez , Aurabindo Pillai , Ilya Bakoulin , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] drm/amd/display: Remove redundant check Date: Mon, 11 Nov 2024 17:38:28 +0530 Message-ID: <20241111120900.63869-2-bhavin.sharma@siliconsignals.io> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241111120900.63869-1-bhavin.sharma@siliconsignals.io> References: <20241111120900.63869-1-bhavin.sharma@siliconsignals.io> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: PN3PR01CA0096.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:9b::13) To PN3P287MB1171.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:1a1::5) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PN3P287MB1171:EE_|PN2P287MB0675:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a0c3c7e-ca7d-4245-b36b-08dd0249c276 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|52116014|7416014|366016|38350700014; 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charset="utf-8" The mode_422 variable is initialized to zero, making mode_422 ? 2 : 1 always false. Since is_dsc_possible is already checked just above, there's no need to check it again before filling out the DSC settings. Removing this redundant check simplifies the code without affecting functionality. Signed-off-by: Bhavin Sharma --- .../amd/display/dc/dml/dml1_display_rq_dlg_calc.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 13 +++++-------- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c = b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c index d8bfc85e5dcd..705ddabb5024 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c @@ -564,7 +564,7 @@ static void get_surf_rq_param( unsigned int vp_height =3D 0; unsigned int data_pitch =3D 0; unsigned int meta_pitch =3D 0; - unsigned int ppe =3D mode_422 ? 2 : 1; + unsigned int ppe =3D 1; bool surf_linear; bool surf_vert; unsigned int bytes_per_element; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/= amd/display/dc/dsc/dc_dsc.c index ebd5df1a36e8..85f6f8e43947 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -1093,14 +1093,11 @@ static bool setup_dsc_config( if (!is_dsc_possible) goto done; =20 - // Final decission: can we do DSC or not? - if (is_dsc_possible) { - // Fill out the rest of DSC settings - dsc_cfg->block_pred_enable =3D dsc_common_caps.is_block_pred_supported; - dsc_cfg->linebuf_depth =3D dsc_common_caps.lb_bit_depth; - dsc_cfg->version_minor =3D (dsc_common_caps.dsc_version & 0xf0) >> 4; - dsc_cfg->is_dp =3D dsc_sink_caps->is_dp; - } + // Fill out the rest of DSC settings + dsc_cfg->block_pred_enable =3D dsc_common_caps.is_block_pred_supported; + dsc_cfg->linebuf_depth =3D dsc_common_caps.lb_bit_depth; + dsc_cfg->version_minor =3D (dsc_common_caps.dsc_version & 0xf0) >> 4; + dsc_cfg->is_dp =3D dsc_sink_caps->is_dp; =20 done: if (!is_dsc_possible) --=20 2.43.0