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charset="utf-8" Add DT support for QUPv3 Serial Engines. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- Build Dependencies: Base: https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_q= cs615-v3-5-e37617e91c62@quicinc.com/ https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_q= cs615-v3-6-e37617e91c62@quicinc.com/ Clock: https://lore.kernel.org/linux-devicetree/20240920-qcs615-clock-drive= r-v2-3-2f6de44eb2aa@quicinc.com/ ICC: https://lore.kernel.org/linux-devicetree/20240924143958.25-2-quic_rlag= gysh@quicinc.com/ Apps SMMU: https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@q= uicinc.com/=20 GPI documentation: https://lore.kernel.org/all/w66ki7lwrqol24iptikn7ccna25u= jqoywjena5ulekf6vynxny@dylbj2r34h7l/T/ v2 -> v3: - Modify GPI DMA node name and compatible string. - Drop buses aliases from SOC DTSI. - Add GPI compatible for QCS615 in seperate patch. v2 Link: https://lore.kernel.org/all/20241028112049.30734-1-quic_vdadhani@q= uicinc.com/ v1 -> v2: - Add opp-shared property. - Use QCOM_ICC_TAG_ALWAYS flag in interconnect property. v1 Link: https://lore.kernel.org/all/20241011103346.22925-1-quic_vdadhani@q= uicinc.com/ --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 627 ++++++++++++++++++++++++++- 1 file changed, 623 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 865ead601f85..cd61db2b6fce 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -296,6 +297,26 @@ mc_virt: interconnect-2 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + qup_opp_table: opp-table-qup { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; @@ -392,6 +413,24 @@ qfprom: efuse@780000 { #size-cells =3D <1>; }; =20 + gpi_dma0: dma-controller@800000 { + compatible =3D "qcom,qcs615-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x800000 0x0 0x60000>; + #dma-cells =3D <3>; + interrupts =3D , + , + , + , + , + , + , + ; + dma-channels =3D <8>; + dma-channel-mask =3D <0xf>; + iommus =3D <&apps_smmu 0xd6 0x0>; + status =3D "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x8c0000 0x0 0x6000>; @@ -400,6 +439,7 @@ qupv3_id_0: geniqup@8c0000 { <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0xc3 0x0>; #address-cells =3D <2>; #size-cells =3D <2>; status =3D "disabled"; @@ -412,13 +452,416 @@ uart0: serial@880000 { pinctrl-0 =3D <&qup_uart0_tx>, <&qup_uart0_rx>; pinctrl-names =3D "default"; interrupts =3D ; - interconnects =3D <&aggre1_noc MASTER_QUP_0 0 - &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_0 0>; + interconnects =3D <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + status =3D "disabled"; + }; + + i2c1: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x884000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + interconnects =3D <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + i2c2: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x888000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c2_data_clk>; + pinctrl-names =3D "default"; + interconnects =3D <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi2: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names =3D "default"; + interconnects =3D <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart2: serial@888000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart2_cts>, <&qup_uart2_rts>, + <&qup_uart2_tx>, <&qup_uart2_rx>; + pinctrl-names =3D "default"; + interconnects =3D <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + status =3D "disabled"; + }; + + i2c3: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x88c000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + interconnects =3D <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,qcs615-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0xa00000 0x0 0x60000>; + #dma-cells =3D <3>; + interrupts =3D , + , + , + , + , + , + , + ; + dma-channels =3D <8>; + dma-channel-mask =3D <0xf>; + iommus =3D <&apps_smmu 0x376 0x0>; + status =3D "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0xac0000 0x0 0x2000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + iommus =3D <&apps_smmu 0x363 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + i2c4: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi4: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart4: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart4_cts>, <&qup_uart4_rts>, + <&qup_uart4_tx>, <&qup_uart4_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c5: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa84000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c5_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + i2c6: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c6_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi6: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart6: serial@a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart6_cts>, <&qup_uart6_rts>, + <&qup_uart6_tx>, <&qup_uart6_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c7: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c7_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi7: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart7: serial@a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart7_cts>, <&qup_uart7_rts>, + <&qup_uart7_tx>, <&qup_uart7_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; status =3D "disabled"; }; }; @@ -478,6 +921,102 @@ tlmm: pinctrl@3100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins =3D "gpio4", "gpio5"; + function =3D "qup0"; + + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins =3D "gpio0", "gpio1"; + function =3D "qup0"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins =3D "gpio18", "gpio19"; + function =3D "qup0"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins =3D "gpio20", "gpio21"; + function =3D "qup1"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins =3D "gpio14", "gpio15"; + function =3D "qup1"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins =3D "gpio6", "gpio7"; + function =3D "qup1"; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + pins =3D "gpio10", "gpio11"; + function =3D "qup1"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup0"; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio3"; + function =3D "qup0"; + }; + + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { + pins =3D "gpio3"; + function =3D "gpio"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins =3D "gpio20", "gpio21", "gpio22"; + function =3D "qup1"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins =3D "gpio23"; + function =3D "qup1"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { + pins =3D "gpio23"; + function =3D "gpio"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + pins =3D "gpio6", "gpio7", "gpio8"; + function =3D "qup1"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio9"; + function =3D "qup1"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { + pins =3D "gpio9"; + function =3D "gpio"; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + pins =3D "gpio10", "gpio11", "gpio12"; + function =3D "qup1"; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins =3D "gpio13"; + function =3D "qup1"; + }; + + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { + pins =3D "gpio13"; + function =3D "gpio"; + }; + qup_uart0_tx: qup-uart0-tx-state { pins =3D "gpio16"; function =3D "qup0"; @@ -487,6 +1026,86 @@ qup_uart0_rx: qup-uart0-rx-state { pins =3D "gpio17"; function =3D "qup0"; }; + + qup_uart2_cts: qup-uart2-cts-state { + pins =3D "gpio0"; + function =3D "qup0"; + }; + + qup_uart2_rts: qup-uart2-rts-state { + pins =3D "gpio1"; + function =3D "qup0"; + }; + + qup_uart2_tx: qup-uart2-tx-state { + pins =3D "gpio2"; + function =3D "qup0"; + }; + + qup_uart2_rx: qup-uart2-rx-state { + pins =3D "gpio3"; + function =3D "qup0"; + }; + + qup_uart4_cts: qup-uart4-cts-state { + pins =3D "gpio20"; + function =3D "qup1"; + }; + + qup_uart4_rts: qup-uart4-rts-state { + pins =3D "gpio21"; + function =3D "qup1"; + }; + + qup_uart4_tx: qup-uart4-tx-state { + pins =3D "gpio22"; + function =3D "qup1"; + }; + + qup_uart4_rx: qup-uart4-rx-state { + pins =3D "gpio23"; + function =3D "qup1"; + }; + + qup_uart6_cts: qup-uart6-cts-state { + pins =3D "gpio6"; + function =3D "qup1"; + }; + + qup_uart6_rts: qup-uart6-rts-state { + pins =3D "gpio7"; + function =3D "qup1"; + }; + + qup_uart6_tx: qup-uart6-tx-state { + pins =3D "gpio8"; + function =3D "qup1"; + }; + + qup_uart6_rx: qup-uart6-rx-state { + pins =3D "gpio9"; + function =3D "qup1"; + }; + + qup_uart7_cts: qup-uart7-cts-state { + pins =3D "gpio10"; + function =3D "qup1"; + }; + + qup_uart7_rts: qup-uart7-rts-state { + pins =3D "gpio11"; + function =3D "qup1"; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins =3D "gpio12"; + function =3D "qup1"; + }; + + qup_uart7_rx: qup-uart7-rx-state { + pins =3D "gpio13"; + function =3D "qup1"; + }; }; =20 dc_noc: interconnect@9160000 { --=20 2.34.1