From nobody Sat Nov 23 19:41:09 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6ED91537CB; Mon, 11 Nov 2024 06:32:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731306738; cv=none; b=h8WaL4ogdUxNVln89+SOuG5Q0Hm95IUdDi9Ma7Mq4D53LvzU0Tjd/vm5h2Mrxz9Y3owo97udyjgj9gtCnVltXeuHU2r3imLcHnJOYJkucLE+BD6KnzKTOFpuQE4/YTRHD5ukfvZQ0+wbm3ArW3hVplsI5yAB0TmlFrIfOcdS3L4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731306738; c=relaxed/simple; bh=+Ro3N2XP9AXkM6gaxt2uPjLl28aKbPKKJsQ+Ib431rY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=mu99PXQYjc32ej7Ws7Tk1H2YOPHzSOllefWMp2JxE65t20/QcoZa8E5lEJtD2lT4zxpvClFItUIEgfDtWhyG/5fcj0tChMftbqeEmHguKrjP8Q5EUs6DLDX8S5fRnzKz8HyQ+sTPiO9JCvJv2gJO4LKb8la9E/mlO7WZm5WgLxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FZvWQhiU; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FZvWQhiU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731306737; x=1762842737; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+Ro3N2XP9AXkM6gaxt2uPjLl28aKbPKKJsQ+Ib431rY=; b=FZvWQhiUpIYn6IZFYxgVHwwuSwj2qHPEGZsaEYGbM4+/8RfOiukmXkJ/ 6NW9CkDyv4U9Qm4zP/hJF4icF1HTWQVCSSII7tFyl0lHCbKzmBp1Fct+V 8f8ZQHYdHMa1B5O1vW4FSUodfxGRq4TzU3nqyIWIgWrGZEVHTDLVWWzet XgBwE9p26K/nKR3rioa1GMIDYU8+pYdY/5SJUdU5UCOEPXTXU/MWtX/gU 2msR/oDqhHffjql2PSlRL6lI4wGX2TAIHdVgpIAI9HqbnKL+rtP81NzZL yMWPBUaw1/lMAl/Dztz9km7B8rrsj8mOh46KAC3OaTw2Re6rXcyIOQCGS Q==; X-CSE-ConnectionGUID: MXfQB+IMTTaI76xLEZbUWw== X-CSE-MsgGUID: RlrGiLz0SMak5wDsVk54mw== X-IronPort-AV: E=McAfee;i="6700,10204,11252"; a="41715479" X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="41715479" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:32:16 -0800 X-CSE-ConnectionGUID: JjVqnH7ZRfyQYMj8HF3gzA== X-CSE-MsgGUID: mrtgLAN+S4O0SgjE8sf4iA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="117684504" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:32:13 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v4 1/8] x86/mce: Make several functions return bool Date: Mon, 11 Nov 2024 14:04:21 +0800 Message-Id: <20241111060428.44258-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241111060428.44258-1-qiuxu.zhuo@intel.com> References: <20241025024602.24318-1-qiuxu.zhuo@intel.com> <20241111060428.44258-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make several functions that return 0 or 1 return a boolean value for better readability. No functional changes are intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v4: - Don't rename mce_notify_irq() (Boris). Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. - Rename mce_notify_irq() to mce_notify_user() (Sohil). Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/include/asm/mce.h | 4 ++-- arch/x86/kernel/cpu/mce/amd.c | 10 +++++----- arch/x86/kernel/cpu/mce/core.c | 22 +++++++++++----------- arch/x86/kernel/cpu/mce/intel.c | 9 +++++---- 4 files changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 4543cf2eb5e8..ea9ca7689f6b 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -276,7 +276,7 @@ static inline void cmci_rediscover(void) {} static inline void cmci_recheck(void) {} #endif =20 -int mce_available(struct cpuinfo_x86 *c); +bool mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); bool mce_usable_address(struct mce *m); @@ -296,7 +296,7 @@ enum mcp_flags { =20 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); =20 -int mce_notify_irq(void); +bool mce_notify_irq(void); =20 DECLARE_PER_CPU(struct mce, injectm); =20 diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6ca80fff1fea..018874b554cb 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -381,7 +381,7 @@ static bool lvt_interrupt_supported(unsigned int bank, = u32 msr_high_bits) return msr_high_bits & BIT(28); } =20 -static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 = hi) +static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32= hi) { int msr =3D (hi & MASK_LVTOFF_HI) >> 20; =20 @@ -389,7 +389,7 @@ static int lvt_off_valid(struct threshold_block *b, int= apic, u32 lo, u32 hi) pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=3D0x%x%08x)\n", b->cpu, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } =20 if (apic !=3D msr) { @@ -399,15 +399,15 @@ static int lvt_off_valid(struct threshold_block *b, i= nt apic, u32 lo, u32 hi) * was set is reserved. Return early here: */ if (mce_flags.smca) - return 0; + return false; =20 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=3D0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } =20 - return 1; + return true; }; =20 /* Reprogram MCx_MISC MSR behind this threshold bank. */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7fb5556a0b53..167965bd2ac0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -492,10 +492,10 @@ static noinstr void mce_gather_info(struct mce_hw_err= *err, struct pt_regs *regs } } =20 -int mce_available(struct cpuinfo_x86 *c) +bool mce_available(struct cpuinfo_x86 *c) { if (mca_cfg.disabled) - return 0; + return false; return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); } =20 @@ -1778,7 +1778,7 @@ static void mce_timer_delete_all(void) * Can be called from interrupt context, but not from machine check/NMI * context. */ -int mce_notify_irq(void) +bool mce_notify_irq(void) { /* Not more than two messages every minute */ static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); @@ -1789,9 +1789,9 @@ int mce_notify_irq(void) if (__ratelimit(&ratelimit)) pr_info(HW_ERR "Machine check events logged\n"); =20 - return 1; + return true; } - return 0; + return false; } EXPORT_SYMBOL_GPL(mce_notify_irq); =20 @@ -2015,25 +2015,25 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo= _x86 *c) return 0; } =20 -static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) { if (c->x86 !=3D 5) - return 0; + return false; =20 switch (c->x86_vendor) { case X86_VENDOR_INTEL: intel_p5_mcheck_init(c); mce_flags.p5 =3D 1; - return 1; + return true; case X86_VENDOR_CENTAUR: winchip_mcheck_init(c); mce_flags.winchip =3D 1; - return 1; + return true; default: - return 0; + return false; } =20 - return 0; + return false; } =20 /* diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index b3cd2c61b11d..f863df0ff42c 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -75,12 +75,12 @@ static u16 cmci_threshold[MAX_NR_BANKS]; */ #define CMCI_STORM_THRESHOLD 32749 =20 -static int cmci_supported(int *banks) +static bool cmci_supported(int *banks) { u64 cap; =20 if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce) - return 0; + return false; =20 /* * Vendor check is not strictly needed, but the initial @@ -89,10 +89,11 @@ static int cmci_supported(int *banks) */ if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL && boot_cpu_data.x86_vendor !=3D X86_VENDOR_ZHAOXIN) - return 0; + return false; =20 if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) - return 0; + return false; + rdmsrl(MSR_IA32_MCG_CAP, cap); *banks =3D min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); --=20 2.17.1 From nobody Sat Nov 23 19:41:09 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12B001537CB; Mon, 11 Nov 2024 06:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="41715498" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:32:47 -0800 X-CSE-ConnectionGUID: /l+O6dDfSVCIv0h2AbEFew== X-CSE-MsgGUID: 2W6kR94ZSeeQX1sFlkRIng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="117684566" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:32:44 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v4 2/8] x86/mce/threshold: Remove the redundant this_cpu_dec_return() Date: Mon, 11 Nov 2024 14:04:22 +0800 Message-Id: <20241111060428.44258-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241111060428.44258-1-qiuxu.zhuo@intel.com> References: <20241025024602.24318-1-qiuxu.zhuo@intel.com> <20241111060428.44258-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 'storm' variable points to this_cpu_ptr(&storm_desc). Access the 'stormy_bank_count' field through the 'storm' to avoid calling this_cpu_*() on the same per-CPU variable twice. This minor optimization reduces the text size by 16 bytes. $ size threshold.o.* text data bss dec hex filename 1395 1664 0 3059 bf3 threshold.o.old 1379 1664 0 3043 be3 threshold.o.new No functional changes intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v4: - No changes. Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/threshold.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/= threshold.c index 89e31e1e5c9c..f4a007616468 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -90,7 +90,7 @@ void cmci_storm_end(unsigned int bank) storm->banks[bank].in_storm_mode =3D false; =20 /* If no banks left in storm mode, stop polling. */ - if (!this_cpu_dec_return(storm_desc.stormy_bank_count)) + if (!--storm->stormy_bank_count) mce_timer_kick(false); } =20 --=20 2.17.1 From nobody Sat Nov 23 19:41:09 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D895154C04; Mon, 11 Nov 2024 06:33:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731306800; cv=none; b=nCkwzGVxz8fsKrnKiCz9fCWYhhbRg9qmmOTzSXBOufpEqp/abWO2YsNOZWwy8AaSrAam5C6hSN3b+khbuDHgfBi/Osvd0M0OQxDWhLfg2eSGNA2z41lYQhrWZ5hqpTb32IbaOvb2pGgsHw/MpuF967ALHpZy0qtkXTaCR1S5uYA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731306800; c=relaxed/simple; bh=fQ1REpPVnxbGxt0F0k8GS43rEvIgAVP3kRKZoGubAUk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=C+WvOafCx3JtvXtj6XQsKhQy9AqoQVG1EQO21CypQHhPK/hiC65Yot+cJD3lbirqXVAiICtvdp3FX/RVjygjqGi4JhLipGhrytwcWJknss3iNRxOdeeBOqo8S7BhlFC+cxeEAi6jNtqqBrJbactQZ11hoZA7c0JnGUpBcJD/olY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mOTg8iSe; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mOTg8iSe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731306799; x=1762842799; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=fQ1REpPVnxbGxt0F0k8GS43rEvIgAVP3kRKZoGubAUk=; b=mOTg8iSe/8DjUqBtW1x+S5lNfJslVEafwOIAgtr7EiS4NiK8jbYrSxnU fJWN1ohJ27qmdP+0ijZTWWgDfx6FDO/BKUpIqucm6EIgD0iHOHmzo4wN1 1fFkrESnisdI7VwiMmKzBE3NNDCIBGORT3FKQ7CqoVaGgA77Rf2/CeyL9 vtiCIRAErrzs6ngPEwOs3l7mEIm7FgTkHuEJgeBPEyUE6PghDzhSBqAJ0 lbSlN2PLRxPisUwsxo8UWoBZ+VyW0O4XHSlQQW3Xuz+U8QlWcAP3JXS+3 UZQ7hhVAbu5ubyYbdyq3yygyE5f63wE/8TAJLM8yROIjwmWTVK0GLskVy Q==; X-CSE-ConnectionGUID: qmETxzUyTmuEmSyZhvUz2Q== X-CSE-MsgGUID: oVN7FEJ4RRyoL+owvEal/Q== X-IronPort-AV: E=McAfee;i="6700,10204,11252"; a="41715534" X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="41715534" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:33:18 -0800 X-CSE-ConnectionGUID: /uZihFakSx+3y8FRD1XhhA== X-CSE-MsgGUID: Lc2DZRnDSm6ShDFmF1hkdg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="117684633" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:33:15 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v4 3/8] x86/mce: Make four functions return bool Date: Mon, 11 Nov 2024 14:04:23 +0800 Message-Id: <20241111060428.44258-4-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241111060428.44258-1-qiuxu.zhuo@intel.com> References: <20241025024602.24318-1-qiuxu.zhuo@intel.com> <20241111060428.44258-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make those functions whose callers only care about success or failure return a boolean value for better readability. Also, update the call sites accordingly. No functional changes. Suggested-by: Thomas Gleixner Signed-off-by: Qiuxu Zhuo Reviewed-by: Sohil Mehta --- Changes in v4: - New patch. arch/x86/kernel/cpu/mce/core.c | 12 ++++++------ arch/x86/kernel/cpu/mce/genpool.c | 29 ++++++++++++++--------------- arch/x86/kernel/cpu/mce/internal.h | 4 ++-- 3 files changed, 22 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 167965bd2ac0..ce6fe5e20805 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -151,7 +151,7 @@ EXPORT_PER_CPU_SYMBOL_GPL(injectm); =20 void mce_log(struct mce_hw_err *err) { - if (!mce_gen_pool_add(err)) + if (mce_gen_pool_add(err)) irq_work_queue(&mce_irq_work); } EXPORT_SYMBOL_GPL(mce_log); @@ -1911,14 +1911,14 @@ static void __mcheck_cpu_check_banks(void) } =20 /* Add per CPU specific workarounds here */ -static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); struct mca_config *cfg =3D &mca_cfg; =20 if (c->x86_vendor =3D=3D X86_VENDOR_UNKNOWN) { pr_info("unknown CPU type - not enabling MCE support\n"); - return -EOPNOTSUPP; + return false; } =20 /* This should be disabled by the BIOS, but isn't always */ @@ -2012,7 +2012,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x= 86 *c) if (cfg->bootlog !=3D 0) cfg->panic_timeout =3D 30; =20 - return 0; + return true; } =20 static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) @@ -2279,12 +2279,12 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) =20 __mcheck_cpu_cap_init(); =20 - if (__mcheck_cpu_apply_quirks(c) < 0) { + if (!__mcheck_cpu_apply_quirks(c)) { mca_cfg.disabled =3D 1; return; } =20 - if (mce_gen_pool_init()) { + if (!mce_gen_pool_init()) { mca_cfg.disabled =3D 1; pr_emerg("Couldn't allocate MCE records pool!\n"); return; diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/ge= npool.c index d0be6dda0c14..3ca9c007a666 100644 --- a/arch/x86/kernel/cpu/mce/genpool.c +++ b/arch/x86/kernel/cpu/mce/genpool.c @@ -94,64 +94,63 @@ bool mce_gen_pool_empty(void) return llist_empty(&mce_event_llist); } =20 -int mce_gen_pool_add(struct mce_hw_err *err) +bool mce_gen_pool_add(struct mce_hw_err *err) { struct mce_evt_llist *node; =20 if (filter_mce(&err->m)) - return -EINVAL; + return false; =20 if (!mce_evt_pool) - return -EINVAL; + return false; =20 node =3D (void *)gen_pool_alloc(mce_evt_pool, sizeof(*node)); if (!node) { pr_warn_ratelimited("MCE records pool full!\n"); - return -ENOMEM; + return false; } =20 memcpy(&node->err, err, sizeof(*err)); llist_add(&node->llnode, &mce_event_llist); =20 - return 0; + return true; } =20 -static int mce_gen_pool_create(void) +static bool mce_gen_pool_create(void) { int mce_numrecords, mce_poolsz, order; struct gen_pool *gpool; - int ret =3D -ENOMEM; void *mce_pool; =20 order =3D order_base_2(sizeof(struct mce_evt_llist)); gpool =3D gen_pool_create(order, -1); if (!gpool) - return ret; + return false; =20 mce_numrecords =3D max(MCE_MIN_ENTRIES, num_possible_cpus() * MCE_PER_CPU= ); mce_poolsz =3D mce_numrecords * (1 << order); mce_pool =3D kmalloc(mce_poolsz, GFP_KERNEL); if (!mce_pool) { gen_pool_destroy(gpool); - return ret; + return false; } - ret =3D gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1); - if (ret) { + + if (gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1)) { gen_pool_destroy(gpool); kfree(mce_pool); - return ret; + return false; } =20 mce_evt_pool =3D gpool; =20 - return ret; + return true; } =20 -int mce_gen_pool_init(void) +bool mce_gen_pool_init(void) { /* Just init mce_gen_pool once. */ if (mce_evt_pool) - return 0; + return true; =20 return mce_gen_pool_create(); } diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index 84f810598231..95a504ece43e 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -31,8 +31,8 @@ struct mce_evt_llist { =20 void mce_gen_pool_process(struct work_struct *__unused); bool mce_gen_pool_empty(void); -int mce_gen_pool_add(struct mce_hw_err *err); -int mce_gen_pool_init(void); +bool mce_gen_pool_add(struct mce_hw_err *err); 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10 Nov 2024 22:33:38 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v4 4/8] x86/mce: Break up __mcheck_cpu_apply_quirks() Date: Mon, 11 Nov 2024 14:04:24 +0800 Message-Id: <20241111060428.44258-5-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241111060428.44258-1-qiuxu.zhuo@intel.com> References: <20241025024602.24318-1-qiuxu.zhuo@intel.com> <20241111060428.44258-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tony Luck Split each vendor specific part into its own helper function. Tested-by: Qiuxu Zhuo Signed-off-by: Tony Luck Signed-off-by: Qiuxu Zhuo Reviewed-by: Sohil Mehta --- Changes in v4: - Add necessary blank lines in apply_quirks_amd() (Yazen). - Use 'mca_cfg' instead of 'cfg' in apply_quirks_*(). (Yazen). Changes in v3: - New patch. arch/x86/kernel/cpu/mce/core.c | 192 ++++++++++++++++++--------------- 1 file changed, 104 insertions(+), 88 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ce6fe5e20805..3855ec2ed0e0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1910,101 +1910,117 @@ static void __mcheck_cpu_check_banks(void) } } =20 +static void apply_quirks_amd(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); + + /* This should be disabled by the BIOS, but isn't always */ + if (c->x86 =3D=3D 15 && this_cpu_read(mce_num_banks) > 4) { + /* + * disable GART TBL walk error reporting, which + * trips off incorrectly with the IOMMU & 3ware + * & Cerberus: + */ + clear_bit(10, (unsigned long *)&mce_banks[4].ctl); + } + + if (c->x86 < 0x11 && mca_cfg.bootlog < 0) { + /* + * Lots of broken BIOS around that don't clear them + * by default and leave crap in there. Don't log: + */ + mca_cfg.bootlog =3D 0; + } + + /* + * Various K7s with broken bank 0 around. Always disable + * by default. + */ + if (c->x86 =3D=3D 6 && this_cpu_read(mce_num_banks) > 0) + mce_banks[0].ctl =3D 0; + + /* + * overflow_recov is supported for F15h Models 00h-0fh + * even though we don't have a CPUID bit for it. + */ + if (c->x86 =3D=3D 0x15 && c->x86_model <=3D 0xf) + mce_flags.overflow_recov =3D 1; + + if (c->x86 >=3D 0x17 && c->x86 <=3D 0x1A) + mce_flags.zen_ifu_quirk =3D 1; +} + +static void apply_quirks_intel(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); + + /* + * SDM documents that on family 6 bank 0 should not be written + * because it aliases to another special BIOS controlled + * register. + * But it's not aliased anymore on model 0x1a+ + * Don't ignore bank 0 completely because there could be a + * valid event later, merely don't write CTL0. + */ + if (c->x86 =3D=3D 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks= ) > 0) + mce_banks[0].init =3D false; + + /* + * All newer Intel systems support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if ((c->x86 > 6 || (c->x86 =3D=3D 6 && c->x86_model >=3D 0xe)) && + mca_cfg.monarch_timeout < 0) + mca_cfg.monarch_timeout =3D USEC_PER_SEC; + + /* + * There are also broken BIOSes on some Pentium M and + * earlier systems: + */ + if (c->x86 =3D=3D 6 && c->x86_model <=3D 13 && mca_cfg.bootlog < 0) + mca_cfg.bootlog =3D 0; + + if (c->x86_vfm =3D=3D INTEL_SANDYBRIDGE_X) + mce_flags.snb_ifu_quirk =3D 1; + + /* + * Skylake, Cascacde Lake and Cooper Lake require a quirk on + * rep movs. + */ + if (c->x86_vfm =3D=3D INTEL_SKYLAKE_X) + mce_flags.skx_repmov_quirk =3D 1; +} + +static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c) +{ + /* + * All newer Zhaoxin CPUs support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if (c->x86 > 6 || (c->x86_model =3D=3D 0x19 || c->x86_model =3D=3D 0x1f))= { + if (mca_cfg.monarch_timeout < 0) + mca_cfg.monarch_timeout =3D USEC_PER_SEC; + } +} + /* Add per CPU specific workarounds here */ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { - struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); struct mca_config *cfg =3D &mca_cfg; =20 - if (c->x86_vendor =3D=3D X86_VENDOR_UNKNOWN) { + switch (c->x86_vendor) { + case X86_VENDOR_UNKNOWN: pr_info("unknown CPU type - not enabling MCE support\n"); return false; - } - - /* This should be disabled by the BIOS, but isn't always */ - if (c->x86_vendor =3D=3D X86_VENDOR_AMD) { - if (c->x86 =3D=3D 15 && this_cpu_read(mce_num_banks) > 4) { - /* - * disable GART TBL walk error reporting, which - * trips off incorrectly with the IOMMU & 3ware - * & Cerberus: - */ - clear_bit(10, (unsigned long *)&mce_banks[4].ctl); - } - if (c->x86 < 0x11 && cfg->bootlog < 0) { - /* - * Lots of broken BIOS around that don't clear them - * by default and leave crap in there. Don't log: - */ - cfg->bootlog =3D 0; - } - /* - * Various K7s with broken bank 0 around. Always disable - * by default. - */ - if (c->x86 =3D=3D 6 && this_cpu_read(mce_num_banks) > 0) - mce_banks[0].ctl =3D 0; - - /* - * overflow_recov is supported for F15h Models 00h-0fh - * even though we don't have a CPUID bit for it. - */ - if (c->x86 =3D=3D 0x15 && c->x86_model <=3D 0xf) - mce_flags.overflow_recov =3D 1; - - if (c->x86 >=3D 0x17 && c->x86 <=3D 0x1A) - mce_flags.zen_ifu_quirk =3D 1; - - } - - if (c->x86_vendor =3D=3D X86_VENDOR_INTEL) { - /* - * SDM documents that on family 6 bank 0 should not be written - * because it aliases to another special BIOS controlled - * register. - * But it's not aliased anymore on model 0x1a+ - * Don't ignore bank 0 completely because there could be a - * valid event later, merely don't write CTL0. - */ - - if (c->x86 =3D=3D 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_bank= s) > 0) - mce_banks[0].init =3D false; - - /* - * All newer Intel systems support MCE broadcasting. Enable - * synchronization with a one second timeout. - */ - if ((c->x86 > 6 || (c->x86 =3D=3D 6 && c->x86_model >=3D 0xe)) && - cfg->monarch_timeout < 0) - cfg->monarch_timeout =3D USEC_PER_SEC; - - /* - * There are also broken BIOSes on some Pentium M and - * earlier systems: - */ - if (c->x86 =3D=3D 6 && c->x86_model <=3D 13 && cfg->bootlog < 0) - cfg->bootlog =3D 0; - - if (c->x86_vfm =3D=3D INTEL_SANDYBRIDGE_X) - mce_flags.snb_ifu_quirk =3D 1; - - /* - * Skylake, Cascacde Lake and Cooper Lake require a quirk on - * rep movs. - */ - if (c->x86_vfm =3D=3D INTEL_SKYLAKE_X) - mce_flags.skx_repmov_quirk =3D 1; - } - - if (c->x86_vendor =3D=3D X86_VENDOR_ZHAOXIN) { - /* - * All newer Zhaoxin CPUs support MCE broadcasting. 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Suggested-by: Sohil Mehta Suggested-by: Dave Hansen Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo Reviewed-by: Sohil Mehta Reviewed-by: Yazen Ghannam --- Changes in v4: - No changes but rebased. Changes in v3: - Newly added. arch/x86/kernel/cpu/mce/core.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 3855ec2ed0e0..d288cc7390f6 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1954,6 +1954,10 @@ static void apply_quirks_intel(struct cpuinfo_x86 *c) { struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); =20 + /* Older CPUs (prior to family 6) don't need quirks. */ + if (c->x86_vfm < INTEL_PENTIUM_PRO) + return; + /* * SDM documents that on family 6 bank 0 should not be written * because it aliases to another special BIOS controlled @@ -1962,22 +1966,21 @@ static void apply_quirks_intel(struct cpuinfo_x86 *= c) * Don't ignore bank 0 completely because there could be a * valid event later, merely don't write CTL0. */ - if (c->x86 =3D=3D 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks= ) > 0) + if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks) > 0) mce_banks[0].init =3D false; =20 /* * All newer Intel systems support MCE broadcasting. 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Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Reviewed-by: Yazen Ghannam --- Changes in v4: - No changes. Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index d288cc7390f6..0f0c6e9d9183 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2118,10 +2118,9 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_= x86 *c) mce_intel_feature_init(c); break; =20 - case X86_VENDOR_AMD: { + case X86_VENDOR_AMD: mce_amd_feature_init(c); break; - } =20 case X86_VENDOR_HYGON: mce_hygon_feature_init(c); --=20 2.17.1 From nobody Sat Nov 23 19:41:09 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E57261537CB; Mon, 11 Nov 2024 06:34:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731306851; cv=none; b=cJiqz1Bg160W+6wOA/UvkJ8NElMvAC/MNBDLI7a65gd76hoAqK7O4dB6Oznglfylh+LNQmIjFpNKEfI0C57hAZ6iKdTELhxtfbNm2dMhowpUZfJjMNVwzmkwZw7CgkSypl7XMSiTBHIOUjDiDraJFy9LA8qPskI58EvuW9SBtaA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731306851; c=relaxed/simple; bh=ocS7zShDtGnLI5b4X5XRts5pmrdem65a4kf54K7qkQI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=RDoSsByMjKqzdVwfYYaMJiUIp9w+WqWM2jlUsSWH3b+Fahf2DG2LU/tmR/k/FWq7S5QeMzsKTZZSLrQFJRCjGA5U+e5lmwtWStjest6igLeowQ3vjVGEtNmmZLh1j12f6C03yyVs4Br2n+1+jgynPGVaYYUbDt0C+9tPNSXYDxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Sgoq3/id; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Sgoq3/id" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731306850; x=1762842850; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ocS7zShDtGnLI5b4X5XRts5pmrdem65a4kf54K7qkQI=; b=Sgoq3/idxTiPBPRMZHCxyN+V+FeMx1213xcKlfMfy9g7JUqC5NPL2B/L lsnFXIS0QHySQJ7rtdIZjdbpWW/eG/cWLR0aYmWUN17h68iOXbvqR+gJs Gw02mhJGalJHEUcWlsyqDAMvLsaB+WSvF0OUOvFshUAH9losW610j5tQE BDO4sGSDlu2wE8/O7rC02xe76UEXMM7Wo4C4WjdgsE5hc5xM/BTGkh7MR TE1+9X5p769Eux1RDPPhmzxejayD+2v+ZHh769eYcj59QPLcTIvFM8JXO 3hKcS45gpIkJP01TURs+6jQ8iYOlv6ew2tHdmrx7b9tNqJ4spQ6bicYZI w==; X-CSE-ConnectionGUID: 5T88Xm+hRE+hGAj0Rq/6vg== X-CSE-MsgGUID: 5B+pfDPFQ6GUEakkK56Qfw== X-IronPort-AV: E=McAfee;i="6700,10204,11252"; a="41715621" X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="41715621" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:34:09 -0800 X-CSE-ConnectionGUID: D2Ab2lAmRZ2/YVaIgiOvFQ== X-CSE-MsgGUID: 5KinCGrRQS6dpOdHAXk2Zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="117684695" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:34:06 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v4 7/8] x86/mce/amd: Remove unnecessary NULL pointer initializations Date: Mon, 11 Nov 2024 14:04:27 +0800 Message-Id: <20241111060428.44258-8-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241111060428.44258-1-qiuxu.zhuo@intel.com> References: <20241025024602.24318-1-qiuxu.zhuo@intel.com> <20241111060428.44258-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove unnecessary NULL pointer initializations from variables that are already initialized before use. Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Reviewed-by: Yazen Ghannam --- Changes in v4: - No changes. Changes in v3: - Collect "Reviewed-by:" Nikolay & Sohil. - Remove the variables' names from the commit message (Sohil). arch/x86/kernel/cpu/mce/amd.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 018874b554cb..c79a82912d38 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -921,8 +921,8 @@ static void log_and_reset_block(struct threshold_block = *block) */ static void amd_threshold_interrupt(void) { - struct threshold_block *first_block =3D NULL, *block =3D NULL, *tmp =3D N= ULL; struct threshold_bank **bp =3D this_cpu_read(threshold_banks); + struct threshold_block *first_block, *block, *tmp; unsigned int bank, cpu =3D smp_processor_id(); =20 /* @@ -1201,8 +1201,7 @@ static int allocate_threshold_blocks(unsigned int cpu= , struct threshold_bank *tb static int __threshold_add_blocks(struct threshold_bank *b) { struct list_head *head =3D &b->blocks->miscj; - struct threshold_block *pos =3D NULL; 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d="scan'208";a="117684706" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2024 22:34:14 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v4 8/8] x86/mce: Fix typos Date: Mon, 11 Nov 2024 14:04:28 +0800 Message-Id: <20241111060428.44258-9-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241111060428.44258-1-qiuxu.zhuo@intel.com> References: <20241025024602.24318-1-qiuxu.zhuo@intel.com> <20241111060428.44258-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix typos in comments. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v4: - No changes. Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. - Remove the detail typos from the commit message (Sohil). Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 0f0c6e9d9183..6e194ccffc7c 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1144,7 +1144,7 @@ static noinstr int mce_start(int *no_way_out) } else { /* * Subject: Now start the scanning loop one by one in - * the original callin order. + * the original calling order. * This way when there are any shared banks it will be * only seen by one CPU before cleared, avoiding duplicates. */ @@ -1917,7 +1917,7 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c) /* This should be disabled by the BIOS, but isn't always */ if (c->x86 =3D=3D 15 && this_cpu_read(mce_num_banks) > 4) { /* - * disable GART TBL walk error reporting, which + * disable GART TLB walk error reporting, which * trips off incorrectly with the IOMMU & 3ware * & Cerberus: */ --=20 2.17.1