From nobody Thu Dec 12 05:02:34 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9630915ECD7; Mon, 11 Nov 2024 01:31:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731288674; cv=none; b=FSwRpLdsULqOaiZHYindE2N4wj/yFp/rEqAUdn1zvrohVk2P1IiGaOQJhtJMbFcC/L9PLABLVegYbszTi6QByzN5aJpZKaz76Q/730TDt75XYXFVXEvX+ijXhQOVNMofGenxupjzoE1MZwUblfqSLoJ4Vwu7A61HAay97qdw/Ws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731288674; c=relaxed/simple; bh=lCVFWObsT1GX3rdDfh51cIAn159eLB+5yHJbzLiJ0JU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l4DoP8fi14r99Z0IPgotPMFq9E+XosO8O1zOqvYZHHy2yYwvwKdwdQftUfgCHTSJ8RbPN3CWFlXho0FijdZoq/hqMQPjaVxICV6Gjgm9p/G8ZDZaXvpHgdwpPkIxj1rH81MpAd8OXiWcCUBnjmDO++lGLvVAo1KNB2iEL4v+7bw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5551A1480; Sun, 10 Nov 2024 17:31:42 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 024B53F66E; Sun, 10 Nov 2024 17:31:10 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 14/14] arm64: dts: allwinner: a523: add Avaota-A1 router support Date: Mon, 11 Nov 2024 01:30:33 +0000 Message-ID: <20241111013033.22793-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241111013033.22793-1-andre.przywara@arm.com> References: <20241111013033.22793-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Avaota A1 router board is an Open Source hardware board, designed by YuzukiHD. Pine64 produces some boards. It uses the Allwinner T527 SoC, and comes with the following features: - Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU - 1GiB/2GiB/4GiB LPDDR4 DRAM - AXP717 + AXP323 PMIC - Raspberry-Pi-2 compatible GPIO header - 1 USB 2.0 type A host port, 1 USB 3.0 type A host post - 1 USB 2.0 type C port (OTG + serial debug) - MicroSD slot - eMMC between 16 and 128 GiB - on-board 16MiB bootable SPI NOR flash - two 1Gbps Ethernet ports (via RTL8211F PHYs) - HDMI port - DP port - camera and LCD connectors - 3.5mm headphone jack - (yet) unsupported WiFi/BT chip - 1.3" LC display, connected via SPI - 12 V barrel plug for power supply Add the devicetree file describing the currently supported features. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-t527-avaota-a1.dts | 311 ++++++++++++++++++ 2 files changed, 312 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 00bed412ee31c..0d678a7499e3c 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -52,3 +52,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx= -2024.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-sp.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-avaota-a1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts new file mode 100644 index 0000000000000..ac3e4a55231c7 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2024 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include + +/ { + model =3D "Avaota A1"; + compatible =3D "yuzukihd,avaota-a1", "allwinner,sun55i-t527"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + /* For now, until we have mainline components living in SRAM */ + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 128 KiB reserved for Trusted Firmware-A (BL31). */ + secmon@48000000 { + reg =3D <0x0 0x48000000 0x0 0x20000>; + no-map; + }; + + /* 256 KiB reserved for the SCP. */ + secmon@48100000 { + reg =3D <0x0 0x48100000 0x0 0x40000>; + no-map; + }; + }; + + reg_vcc12v: vcc12v { + /* DC input jack */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-12v"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-always-on; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the 12V->5V regulator */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc12v>; + regulator-always-on; + }; + + reg_vcc3v3: vcc3v3 { + /* 3.3V dummy supply for the SD card */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vcc5v>; + regulator-always-on; + }; + + reg_usb_vbus: vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ + enable-active-high; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_vcc3v3>; + cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_DOWN)>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply =3D <®_cldo1>; + vcc-pd-supply =3D <®_dcdc4>; + vcc-pe-supply =3D <®_dcdc4>; + vcc-pf-supply =3D <®_cldo3>; /* actually switchable */ + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply =3D <®_dcdc4>; + vcc-pj-supply =3D <®_dcdc4>; + vcc-pk-supply =3D <®_bldo3>; +}; + +&r_i2c0 { + status =3D "okay"; + + axp717: pmic@35 { + compatible =3D "x-powers,axp717"; + reg =3D <0x35>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + vin4-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <920000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1160000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-dram"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vdd-io"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + /* not connected */ + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-pl-pm"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pg-wifi-lvds"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-dram-1v8"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-cvp-pk-vid1v8"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pc"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-efuse"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-io-mmc-spi-ana"; + }; + + reg_cldo4: cldo4 { + /* not connected */ + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible =3D "x-powers,axp323"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + status =3D "okay"; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + aldo1 { + /* not connected */ + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* Some RISC-V management core related voltage */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply =3D <®_aldo3>; + */ + vcc-pm-supply =3D <®_aldo3>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pb_pins>; + status =3D "okay"; +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + usb0_vbus-supply =3D <®_usb_vbus>; + usb0_vbus_det-gpios =3D <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */ + status =3D "okay"; +}; --=20 2.46.2