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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4de787d62c6sm1410986173.81.2024.11.11.07.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2024 07:59:44 -0800 (PST) From: Trevor Gamblin Date: Mon, 11 Nov 2024 10:59:42 -0500 Subject: [PATCH 1/3] iio: adc: ad4695: fix buffered read timing in ad4695_buffer_preenable() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241111-tgamblin-ad4695_improvements-v1-1-698af4512635@baylibre.com> References: <20241111-tgamblin-ad4695_improvements-v1-0-698af4512635@baylibre.com> In-Reply-To: <20241111-tgamblin-ad4695_improvements-v1-0-698af4512635@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Trevor Gamblin X-Mailer: b4 0.14.1 Modify ad4695_buffer_preenable() by adding an extra SPI transfer after each data read to help ensure that the timing requirement between the last SCLK rising edge and the next CNV rising edge is met. This requires a restructure of the buf_read_xfer array in ad4695_state. Also define AD4695_T_SCK_CNV_DELAY_NS to use for each added transfer. Without this change it is possible for the data to become corrupted on sequential buffered reads due to the device not properly exiting conversion mode. Fixes: 6cc7e4bf2e08 ("iio: adc: ad4695: implement triggered buffer") Signed-off-by: Trevor Gamblin Suggested-by: David Lechner --- drivers/iio/adc/ad4695.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/ad4695.c b/drivers/iio/adc/ad4695.c index 595ec4158e73..82e930b21c69 100644 --- a/drivers/iio/adc/ad4695.c +++ b/drivers/iio/adc/ad4695.c @@ -91,6 +91,7 @@ #define AD4695_T_WAKEUP_SW_MS 3 #define AD4695_T_REFBUF_MS 100 #define AD4695_T_REGCONFIG_NS 20 +#define AD4695_T_SCK_CNV_DELAY_NS 80 #define AD4695_REG_ACCESS_SCLK_HZ (10 * MEGA) =20 /* Max number of voltage input channels. */ @@ -132,8 +133,13 @@ struct ad4695_state { unsigned int vref_mv; /* Common mode input pin voltage. */ unsigned int com_mv; - /* 1 per voltage and temperature chan plus 1 xfer to trigger 1st CNV */ - struct spi_transfer buf_read_xfer[AD4695_MAX_CHANNELS + 2]; + /* + * 2 per voltage and temperature chan plus 1 xfer to trigger 1st + * CNV. Excluding the trigger xfer, every 2nd xfer only serves + * to control CS and add a delay between the last SCLK and next + * CNV rising edges. + */ + struct spi_transfer buf_read_xfer[AD4695_MAX_CHANNELS * 2 + 3]; struct spi_message buf_read_msg; /* Raw conversion data received. */ u8 buf[ALIGN((AD4695_MAX_CHANNELS + 2) * AD4695_MAX_CHANNEL_SIZE, @@ -451,9 +457,6 @@ static int ad4695_buffer_preenable(struct iio_dev *indi= o_dev) xfer->bits_per_word =3D 16; xfer->rx_buf =3D &st->buf[(num_xfer - 1) * 2]; xfer->len =3D 2; - xfer->cs_change =3D 1; - xfer->cs_change_delay.value =3D AD4695_T_CONVERT_NS; - xfer->cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 if (bit =3D=3D temp_chan_bit) { temp_en =3D 1; @@ -468,6 +471,20 @@ static int ad4695_buffer_preenable(struct iio_dev *ind= io_dev) } =20 num_xfer++; + + /* + * We need to add a blank xfer in data reads, to meet + * the timing requirement of a minimum delay between the + * last SCLK rising edge and the CS deassert. + */ + xfer =3D &st->buf_read_xfer[num_xfer]; + xfer->delay.value =3D AD4695_T_SCK_CNV_DELAY_NS; + xfer->delay.unit =3D SPI_DELAY_UNIT_NSECS; + xfer->cs_change =3D 1; + xfer->cs_change_delay.value =3D AD4695_T_CONVERT_NS; + xfer->cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + + num_xfer++; } =20 /* --=20 2.39.5 From nobody Sat Nov 23 19:52:25 2024 Received: from mail-io1-f52.google.com (mail-io1-f52.google.com [209.85.166.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 021CC19E98E for ; Mon, 11 Nov 2024 15:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731340789; cv=none; b=akP67QaKBB//+OQzBnwq7mYjt5oI7Iv3N+z2l7G1RdiyrsdxitnMh7Yj8yjdvUhz7Ozqi94I4rkmJOKRzHJRwNX0rqk2MdRXnGDUuAfKOx2lt4eWc1S0mKUzaIHulkzPrBj1iKEPs0ByvhLu+HQY5PBMxkjrGtKxJjyAfMvdG2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4de787d62c6sm1410986173.81.2024.11.11.07.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2024 07:59:45 -0800 (PST) From: Trevor Gamblin Date: Mon, 11 Nov 2024 10:59:43 -0500 Subject: [PATCH 2/3] iio: adc: ad4695: make ad4695_exit_conversion_mode() more robust Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241111-tgamblin-ad4695_improvements-v1-2-698af4512635@baylibre.com> References: <20241111-tgamblin-ad4695_improvements-v1-0-698af4512635@baylibre.com> In-Reply-To: <20241111-tgamblin-ad4695_improvements-v1-0-698af4512635@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Trevor Gamblin X-Mailer: b4 0.14.1 Ensure that conversion mode is successfully exited when the command is issued by adding an extra transfer beforehand, matching the minimum CNV high and low times from the AD4695 datasheet. The AD4695 has a quirk where the exit command only works during a conversion, so guarantee this happens by triggering a conversion in ad4695_exit_conversion_mode(). Then make this even more robust by ensuring that the exit command is run at AD4695_REG_ACCESS_SCLK_HZ rather than the bus maximum. Signed-off-by: Trevor Gamblin Suggested-by: David Lechner --- drivers/iio/adc/ad4695.c | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad4695.c b/drivers/iio/adc/ad4695.c index 82e930b21c69..f36c1a1db886 100644 --- a/drivers/iio/adc/ad4695.c +++ b/drivers/iio/adc/ad4695.c @@ -92,6 +92,8 @@ #define AD4695_T_REFBUF_MS 100 #define AD4695_T_REGCONFIG_NS 20 #define AD4695_T_SCK_CNV_DELAY_NS 80 +#define AD4695_T_CNVL_NS 80 +#define AD4695_T_CNVH_NS 10 #define AD4695_REG_ACCESS_SCLK_HZ (10 * MEGA) =20 /* Max number of voltage input channels. */ @@ -364,11 +366,31 @@ static int ad4695_enter_advanced_sequencer_mode(struc= t ad4695_state *st, u32 n) */ static int ad4695_exit_conversion_mode(struct ad4695_state *st) { - struct spi_transfer xfer =3D { - .tx_buf =3D &st->cnv_cmd2, - .len =3D 1, - .delay.value =3D AD4695_T_REGCONFIG_NS, - .delay.unit =3D SPI_DELAY_UNIT_NSECS, + /* + * An extra transfer is needed to trigger a conversion here so + * that we can be 100% sure the command will be processed by the + * ADC, rather than relying on it to be in the correct state + * when this function is called (this chip has a quirk where the + * command only works when reading a conversion, and if the + * previous conversion was already read then it won't work). The + * actual conversion command is then run at the slower + * AD4695_REG_ACCESS_SCLK_HZ speed to guarantee this works. + */ + struct spi_transfer xfers[] =3D { + { + .delay.value =3D AD4695_T_CNVL_NS, + .delay.unit =3D SPI_DELAY_UNIT_NSECS, + .cs_change =3D 1, + .cs_change_delay.value =3D AD4695_T_CNVH_NS, + .cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS, + }, + { + .speed_hz =3D AD4695_REG_ACCESS_SCLK_HZ, + .tx_buf =3D &st->cnv_cmd2, + .len =3D 1, + .delay.value =3D AD4695_T_REGCONFIG_NS, + .delay.unit =3D SPI_DELAY_UNIT_NSECS, + }, }; =20 /* @@ -377,7 +399,7 @@ static int ad4695_exit_conversion_mode(struct ad4695_st= ate *st) */ st->cnv_cmd2 =3D AD4695_CMD_EXIT_CNV_MODE << 3; =20 - return spi_sync_transfer(st->spi, &xfer, 1); + return spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); } =20 static int ad4695_set_ref_voltage(struct ad4695_state *st, int vref_mv) --=20 2.39.5 From nobody Sat Nov 23 19:52:25 2024 Received: from mail-io1-f47.google.com (mail-io1-f47.google.com [209.85.166.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 974F819E99C for ; Mon, 11 Nov 2024 15:59:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731340789; cv=none; b=ERnUT1Ua2XVFWuXMuRxnAthHtQucxAK5IfkQtIAJBlhY6cSvGEnzU0tBESWCcQmrOTnOMJHBv9JTzu973x+xczgmHuzfAyb1ZLLHW0nEshxM9BqZiRG4cyCbpsbylB+6pC8TDQsHFLSQZXgikaQe3Fi3xR/zhg1Aci6hoDSAsfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731340789; c=relaxed/simple; bh=HDcW1VcFC6TUobbEsvgtNwj7T/A2DfMJi7G65Cb9CEw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RNn8YoMr9RNz1nvtDWwkMhN2pjI04bglNy/6ZKZWgMgaO+ACt+zGMnSb4g8SYEhBTAmFyIrwTlJnHiuLg0u3twHbiintX4pVnw03BxlPEKSutLeydprPAG2RTqC0jhpRYGGCU6IxVG+r2TjhzngmL1pvfXokbICiNHv8z55m9D4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=kn3gIP/i; arc=none smtp.client-ip=209.85.166.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="kn3gIP/i" Received: by mail-io1-f47.google.com with SMTP id ca18e2360f4ac-83ab21c269eso177249439f.2 for ; Mon, 11 Nov 2024 07:59:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1731340787; x=1731945587; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MRx61QutqkHqE8LsifHeDvLFt2mQ7Pk/J2Li4P0J5EU=; b=kn3gIP/iAqIFjThhhJdpY5p+TfBzmvYJuz+/2qolTlJII5mEKK3j7U07QJoL3wSF3p jPelUIGdgnhYM50ecJrK8+Pv/8/tuFnv0h+pHKanUQPIUaFsxKSJYnOobzeTkdpSdXq6 WAKSIhzw7pwP8nbNXiPfqzfsFfhhDfaLwWj1Q6jMhDdebiz1BuEU9tH4WTQcklwnQqee FUZdV+8Xq32DcT044rA3HqOe6V3qjYo9jQPTC+AvVdZWPBLqnfpc4HkD1QMtV6Lmzv/F Z7Me14w4U3UoVW3VSlUTDO1j9LyDLyk2/3KGSwdfzcEod4P4uVqBHRZbBIuaRLNpJNfT mCYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731340787; x=1731945587; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MRx61QutqkHqE8LsifHeDvLFt2mQ7Pk/J2Li4P0J5EU=; b=UBQnlVWItG/VrcXKgCUU4sEWQ04nKPOi70noOT1FzxBCgyBrGpUt1TpamjOhUnFS7D fq7WzTYQ2SRnsNqW9D5Vynlj18BESo3/9dosAd0cgMZXQrnemtX8voVhCyGnlItwQyvr JIHL4npFI0Cue8NEHRg0kuYrd5Si1kJWpXI+Ohai7ez7v2X5GhFtxCfoOsMsTQW3h/bA GZpQKsT95utirC4jvLiDMsjRhzpYVEXf4r4i/H0LGeMWNQ81M63U2LUCitx1t3ymEYFq 5+CadpUoaHmtT0aMeTaVNO9xZndA9E5PeltPEtsOGlHUB1BPv7dNangTGI5AglCklJFG V8gA== X-Forwarded-Encrypted: i=1; AJvYcCVAHNOCuC5nyUPZ+d5E1bXoWItBOu0xoJm9GGJUuNaOiH8jRo78zdnSSf+8SysdD4BlLFRPGB63N4yZT+c=@vger.kernel.org X-Gm-Message-State: AOJu0YzNwPJbQFdmw/LgCIq7r1HElnO3APSEL/TmuEZHHTxXnZozirh/ XsNAl9ab5RGublVqaH9iTcS2TVcZfYVsIsPMAbSE1rEJru2+z5eSjke9C09RvJWURES9mOTTq+N L X-Google-Smtp-Source: AGHT+IFz5onGePgbNMaG6Xw/7Xs9ETfUP+zGO0bMsWlJBZyv1Ip2qkVxHrYh9z77fz9YgW2JWKoJmg== X-Received: by 2002:a05:6602:13d3:b0:83a:acfa:b0ba with SMTP id ca18e2360f4ac-83e032a171dmr1370582039f.1.1731340786793; Mon, 11 Nov 2024 07:59:46 -0800 (PST) Received: from [127.0.1.1] (d24-150-219-207.home.cgocable.net. [24.150.219.207]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4de787d62c6sm1410986173.81.2024.11.11.07.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2024 07:59:46 -0800 (PST) From: Trevor Gamblin Date: Mon, 11 Nov 2024 10:59:44 -0500 Subject: [PATCH 3/3] iio: adc: ad4695: add custom regmap bus callbacks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241111-tgamblin-ad4695_improvements-v1-3-698af4512635@baylibre.com> References: <20241111-tgamblin-ad4695_improvements-v1-0-698af4512635@baylibre.com> In-Reply-To: <20241111-tgamblin-ad4695_improvements-v1-0-698af4512635@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , David Lechner , Jonathan Cameron Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Trevor Gamblin X-Mailer: b4 0.14.1 Add a custom implementation of regmap read/write callbacks using the SPI bus. This allows them to be performed at a lower SCLK rate than data reads. Previously, all SPI transfers were being performed at a lower speed, but with this change sample data is read at the max bus speed while the register reads/writes remain at the lower rate. Also remove .can_multi_write from the AD4695 driver's regmap_configs, as this isn't implemented or needed. For some background context, see: https://lore.kernel.org/linux-iio/20241028163907.00007e12@Huawei.com/ Suggested-by: David Lechner Signed-off-by: Trevor Gamblin --- drivers/iio/adc/Kconfig | 2 +- drivers/iio/adc/ad4695.c | 74 +++++++++++++++++++++++++++++++++++++++++++-= ---- 2 files changed, 68 insertions(+), 8 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 6c4e74420fd2..e0f9d01ce37d 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -51,9 +51,9 @@ config AD4130 config AD4695 tristate "Analog Device AD4695 ADC Driver" depends on SPI - select REGMAP_SPI select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select REGMAP help Say yes here to build support for Analog Devices AD4695 and similar analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4695.c b/drivers/iio/adc/ad4695.c index f36c1a1db886..180a0fd4f03c 100644 --- a/drivers/iio/adc/ad4695.c +++ b/drivers/iio/adc/ad4695.c @@ -150,6 +150,8 @@ struct ad4695_state { /* Commands to send for single conversion. */ u16 cnv_cmd; u8 cnv_cmd2; + /* Buffer for storing data from regmap bus reads/writes */ + u8 regmap_bus_data[4]; }; =20 static const struct regmap_range ad4695_regmap_rd_ranges[] =3D { @@ -194,7 +196,6 @@ static const struct regmap_config ad4695_regmap_config = =3D { .max_register =3D AD4695_REG_AS_SLOT(127), .rd_table =3D &ad4695_regmap_rd_table, .wr_table =3D &ad4695_regmap_wr_table, - .can_multi_write =3D true, }; =20 static const struct regmap_range ad4695_regmap16_rd_ranges[] =3D { @@ -226,7 +227,67 @@ static const struct regmap_config ad4695_regmap16_conf= ig =3D { .max_register =3D AD4695_REG_GAIN_IN(15), .rd_table =3D &ad4695_regmap16_rd_table, .wr_table =3D &ad4695_regmap16_wr_table, - .can_multi_write =3D true, +}; + +static int ad4695_regmap_bus_reg_write(void *context, const void *data, + size_t count) +{ + struct ad4695_state *st =3D context; + struct spi_transfer xfer =3D { + .speed_hz =3D AD4695_REG_ACCESS_SCLK_HZ, + .len =3D count, + .tx_buf =3D st->regmap_bus_data, + }; + + if (count > ARRAY_SIZE(st->regmap_bus_data)) + return -EINVAL; + + memcpy(st->regmap_bus_data, data, count); + + return spi_sync_transfer(st->spi, &xfer, 1); +} + +static int ad4695_regmap_bus_reg_read(void *context, const void *reg, + size_t reg_size, void *val, + size_t val_size) +{ + struct ad4695_state *st =3D context; + struct spi_transfer xfers[] =3D { + { + .speed_hz =3D AD4695_REG_ACCESS_SCLK_HZ, + .len =3D reg_size, + .tx_buf =3D &st->regmap_bus_data[0], + }, { + .speed_hz =3D AD4695_REG_ACCESS_SCLK_HZ, + .len =3D val_size, + .rx_buf =3D &st->regmap_bus_data[2], + }, + }; + int ret; + + if (reg_size > 2) + return -EINVAL; + + if (val_size > 2) + return -EINVAL; + + memcpy(&st->regmap_bus_data[0], reg, reg_size); + + ret =3D spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); + if (ret) + return ret; + + memcpy(val, &st->regmap_bus_data[2], val_size); + + return 0; +} + +static const struct regmap_bus ad4695_regmap_bus =3D { + .write =3D ad4695_regmap_bus_reg_write, + .read =3D ad4695_regmap_bus_reg_read, + .read_flag_mask =3D 0x80, + .reg_format_endian_default =3D REGMAP_ENDIAN_BIG, + .val_format_endian_default =3D REGMAP_ENDIAN_BIG, }; =20 static const struct iio_chan_spec ad4695_channel_template =3D { @@ -1040,15 +1101,14 @@ static int ad4695_probe(struct spi_device *spi) if (!st->chip_info) return -EINVAL; =20 - /* Registers cannot be read at the max allowable speed */ - spi->max_speed_hz =3D AD4695_REG_ACCESS_SCLK_HZ; - - st->regmap =3D devm_regmap_init_spi(spi, &ad4695_regmap_config); + st->regmap =3D devm_regmap_init(dev, &ad4695_regmap_bus, st, + &ad4695_regmap_config); if (IS_ERR(st->regmap)) return dev_err_probe(dev, PTR_ERR(st->regmap), "Failed to initialize regmap\n"); =20 - st->regmap16 =3D devm_regmap_init_spi(spi, &ad4695_regmap16_config); + st->regmap16 =3D devm_regmap_init(dev, &ad4695_regmap_bus, st, + &ad4695_regmap_config); if (IS_ERR(st->regmap16)) return dev_err_probe(dev, PTR_ERR(st->regmap16), "Failed to initialize regmap16\n"); --=20 2.39.5