From nobody Sun Nov 24 01:21:10 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D49F118FC99; Sat, 9 Nov 2024 12:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731154110; cv=none; b=GMYptS+gQryBZL1ejk0FkCSkkBKiLzalHriLnOhUozEJKjOm5nqU31jbIQzXyMTDmB+5bXM62Dz2qyCUrIA4vqc1tNQdUsmIyAnefriR7yLgUM+361pyQnxaPBZiPu44dTfwSOIc7pY3BJ3gwd2hXFSvv3JhHCwMAuFr40YyoMQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731154110; c=relaxed/simple; bh=iMio1sFFPMG/RV6SGsUpBNsNCA9dTd4qsbD81Kgo4LU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kCc6aIDM/p7Fqizwectkre7NYISjr5HRHhObaxC45wfzvyU6dmqcV34WDiBUfsFO3/I0sbhsQcGanzdyjZa1Zidzbxvmt/g0dhI2r8NTdUw79JNXrzYywaT+iS3vl06fUOFDe6plEYiSqsUgCzFl+zd13D2zeMGz8jsffuv4xiQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=LqU3R5dM; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="LqU3R5dM" Received: from [192.168.118.162] (254C229A.nat.pool.telekom.hu [37.76.34.154]) by mail.mainlining.org (Postfix) with ESMTPSA id 66541E45CB; Sat, 9 Nov 2024 12:08:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1731154104; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D+WL6+u4t8+8AsjTJRh3ejc4Yqvwk4DtV7SSjGUvgI8=; b=LqU3R5dMImvbhgORQIXiG9cLgqnCGHf+E0WJ8eFsz+VnJim8nYh2c1fJM77i4Y98keotsf Vm1W7PdhmF5nSu8YXlgwxVUEZtrnVpPiwKUnDwUuNz9HEy10zGY0yWP4DKNrjpbH11C5EO 2NUKmD5nAk5xd+Kso6bgEwX8dipIZhKk1WTYH5YVZQloIq8ogctXygarrHCmDN3Y4G1RNB 8nnNSVbZonIPFkLrlVcY/8Dvzs8q4OP3XLDKt5mldgav7CpEBukZ7EbzizOjlR+p3YSsa0 GEFoEUvDNSAozPxbeXkosr884+inRf4l7WVG6mWBaoIJH5bIM9/k2PCUPCoc1Q== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Sat, 09 Nov 2024 13:08:10 +0100 Subject: [PATCH v4 08/10] arm64: dts: qcom: Add initial support for MSM8917 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241109-msm8917-v4-8-8be9904792ab@mainlining.org> References: <20241109-msm8917-v4-0-8be9904792ab@mainlining.org> In-Reply-To: <20241109-msm8917-v4-0-8be9904792ab@mainlining.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731154089; l=47678; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=tp6DMynFTt99H90cKCyE39LgDHIs6/6ywjI6jcpGH8U=; b=NhA8HY+xw6EtAYeuwYbXXfiZrfgLmB4K2gZpUI8fYQrWtxjTNv4MkrSpTVQNvh/wOp1NFtZdP 1sE76StVYzWB5vSUjR3n2QsIldhiWdqvtJKf5RXugceSX0teRNmPwMv X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Otto Pfl=C3=BCger Add initial support for MSM8917 SoC. Signed-off-by: Otto Pfl=C3=BCger [reword commit, rebase, fix schema errors] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/msm8917.dtsi | 1997 +++++++++++++++++++++++++++++= ++++ 1 file changed, 1997 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qc= om/msm8917.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..f866843772684c695069debfc76= 4f7a0a58843bb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -0,0 +1,1997 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { }; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + }; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + + cpu1: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + }; + + cpu2: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + }; + + cpu3: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000023>; + entry-latency-us =3D <700>; + exit-latency-us =3D <650>; + min-residency-us =3D <1972>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000043>; + entry-latency-us =3D <240>; + exit-latency-us =3D <280>; + min-residency-us =3D <806>; + }; + + cluster_sleep_2: cluster-sleep-2 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000053>; + entry-latency-us =3D <700>; + exit-latency-us =3D <1000>; + min-residency-us =3D <6500>; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_sleep_0: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "standalone-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <125>; + exit-latency-us =3D <180>; + min-residency-us =3D <595>; + local-timer-stop; + }; + }; + + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8916", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", "bus", "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0>, + <&cluster_sleep_1>, + <&cluster_sleep_2>; + }; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8917-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8917", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8917", "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + qseecom_mem: qseecom@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + /* + * The memory region for the mpss firmware is generally + * relocatable and could be allocated dynamically. + * However, many firmware versions tend to fail when + * loaded to some special addresses, so it is hard to + * define reliable alloc-ranges. + * + * alignment =3D <0x0 0x400000>; + * alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + */ + reg =3D <0x0 0x86800000 0x0 0>; /* size is device-specific */ + no-map; + status =3D "disabled"; + }; + + rmtfs@92100000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x92100000 0x0 0x180000>; + no-map; + + qcom,client-id =3D <1>; + }; + + adsp_mem: adsp { + size =3D <0x0 0x1100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x400000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + wcnss_mem: wcnss { + size =3D <0x0 0x700000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apcs 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + qcom,ipc =3D <&apcs 8 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <451>, <431>; + + interrupts =3D ; + + qcom,ipc =3D <&apcs 8 18>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mboxes =3D <0>, <&apcs 13>, <0>, <&apcs 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0xffffffff>; + compatible =3D "simple-bus"; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x00060000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x0006c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&xo_board>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", "ahb", "sleep"; + resets =3D <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", "por"; + status =3D "disabled"; + }; + + qfprom: qfprom@a4000 { + compatible =3D "qcom,msm8917-qfprom", "qcom,qfprom"; + reg =3D <0x000a4000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_base1: base1@1d8 { + reg =3D <0x1d8 1>; + bits =3D <0 8>; + }; + + tsens_s5_p1: s5-p1@1d9 { + reg =3D <0x1d9 1>; + bits =3D <0 6>; + }; + + tsens_s5_p2: s5-p2@1d9 { + reg =3D <0x1d9 2>; + bits =3D <6 6>; + }; + + tsens_s6_p1: s6-p1@1da { + reg =3D <0x1da 2>; + bits =3D <4 6>; + }; + + tsens_s6_p2: s6-p2@1db { + reg =3D <0x1db 1>; + bits =3D <2 6>; + }; + + tsens_s7_p1: s7-p1@1dc { + reg =3D <0x1dc 1>; + bits =3D <0 6>; + }; + + tsens_s7_p2: s7-p2@1dc { + reg =3D <0x1dc 2>; + bits =3D <6 6>; + }; + + tsens_s8_p1: s8-p1@1dd { + reg =3D <0x1dd 2>; + bits =3D <4 6>; + }; + + tsens_s8_p2: s8-p2@1de { + reg =3D <0x1de 1>; + bits =3D <2 6>; + }; + + tsens_base2: base2@1df { + reg =3D <0x1df 1>; + bits =3D <0 8>; + }; + + tsens_mode: mode@210 { + reg =3D <0x210 1>; + bits =3D <0 3>; + }; + + tsens_s0_p1: s0-p1@210 { + reg =3D <0x210 2>; + bits =3D <3 6>; + }; + + tsens_s0_p2: s0-p2@211 { + reg =3D <0x211 1>; + bits =3D <1 6>; + }; + + tsens_s1_p1: s1-p1@211 { + reg =3D <0x211 2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@212 { + reg =3D <0x212 2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@213 { + reg =3D <0x213 2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@214 { + reg =3D <0x214 1>; + bits =3D <1 6>; + }; + + tsens_s3_p1: s3-p1@214 { + reg =3D <0x214 2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@215 { + reg =3D <0x215 2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@216 { + reg =3D <0x216 2>; + bits =3D <3 6>; + }; + + tsens_s4_p2: s4-p2@217 { + reg =3D <0x217 1>; + bits =3D <1 6>; + }; + + tsens_s9_p1: s9-p1@230{ + reg =3D <0x230 1>; + bits =3D <0 6>; + }; + + tsens_s9_p2: s9-p2@230 { + reg =3D <0x230 2>; + bits =3D <6 6>; + }; + + tsens_s10_p1: s10-p1@231 { + reg =3D <0x231 2>; + bits =3D <4 6>; + }; + + tsens_s10_p2: s10-p2@232 { + reg =3D <0x232 1>; + bits =3D <2 6>; + }; + }; + + rng@e3000 { + compatible =3D "qcom,prng"; + reg =3D <0x000e3000 0x1000>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8937-tsens", "qcom,tsens-v1"; + reg =3D <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts =3D ; + interrupt-names =3D "uplow"; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names =3D "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + #qcom,sensors =3D <11>; + #thermal-sensor-cells =3D <1>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8917-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + i2c2_default: i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c2_sleep: i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_default: i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_default: i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_sleep: i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_default: i2c5-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_sleep: i2c5-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc1_clk_on: sdc1-clk-on-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + sdc1_clk_off: sdc1-clk-off-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_cmd_on: sdc1-cmd-on-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <10>; + }; + + sdc1_cmd_off: sdc1-cmd-off-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_data_on: sdc1-data-on-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc1_data_off: sdc1-data-off-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc1_rclk_on: sdc1-rclk-on-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: sdc1-rclk-off-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc2_clk_on: sdc2-clk-on-state { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_clk_off: sdc2-clk-off-state { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc2_cd_on: cd-on-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc2_data_on: sdc2-data-on-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_data_off: sdc2-data-off-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + spi3_default: spi3-default-state { + cs-pins { + pins =3D "gpio10"; + function =3D "blsp_spi3"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "blsp_spi3"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + spi3_sleep: spi3-sleep-state { + cs-pins { + pins =3D "gpio10"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + spi6_default: spi6-default-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + }; + + spi6_sleep: spi6-sleep-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan-pins { + pins =3D "gpio79", "gpio80"; + function =3D "wcss_wlan"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan0-pins { + pins =3D "gpio78"; + function =3D "wcss_wlan0"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan1-pins { + pins =3D "gpio77"; + function =3D "wcss_wlan1"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan2-pins { + pins =3D "gpio76"; + function =3D "wcss_wlan2"; + drive-strength =3D <6>; + bias-pull-up; + + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8917"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + reg =3D <0x01800000 0x80000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>; + clock-names =3D "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8917", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ab0000 0x1040>; + reg-names =3D "mdss_phys", "vbif_phys"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + status =3D "disabled"; + + mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8917-mdp5", "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + iommus =3D <&apps_iommu 0x15>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdp5_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a94000 0x300>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&mdss_dsi0_opp_table>; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94a00 { + compatible =3D "qcom,dsi-phy-28nm-8937"; + reg =3D <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names =3D "iface", "ref"; + }; + }; + + apps_iommu: iommu@1e20000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + compatible =3D "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; + ranges =3D <0 0x01e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", "bus"; + + qcom,iommu-secure-id =3D <17>; + + /* VFE */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x14000 0x1000>; + interrupts =3D ; + }; + + /* MDP_0 */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x15000 0x1000>; + interrupts =3D ; + }; + + /* VENUS_NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x16000 0x1000>; + interrupts =3D ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + compatible =3D "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; + + ranges =3D <0 0x01f08000 0x10000>; + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names =3D "iface", "bus"; + qcom,iommu-secure-id =3D <18>; + + iommu-ctx@0 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0 0x1000>; + interrupts =3D ; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-306.32", "qcom,adreno"; + reg =3D <0x01c00000 0x20000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + clock-names =3D "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gfx3d"; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains =3D <&gcc OXILI_GX_GDSC>; + operating-points-v2 =3D <&gpu_opp_table>; + #cooling-cells =3D <2>; + + iommus =3D <&gpu_iommu 0>; + + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-598000000 { + opp-hz =3D /bits/ 64 <598000000>; + }; + + opp-523200000 { + opp-hz =3D /bits/ 64 <523200000>; + }; + + opp-484800000 { + opp-hz =3D /bits/ 64 <484800000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + }; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + }; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x04044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + + num-channels =3D <6>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x500>, + <0x07824000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x500>, + <0x07864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + bus-width =3D <4>; + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07ac4000 0x1d000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <10>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart1_default>; + pinctrl-1 =3D <&blsp1_uart1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c2_default>; + pinctrl-1 =3D <&i2c2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c3_default>; + pinctrl-1 =3D <&i2c3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&spi3_default>; + pinctrl-1 =3D <&spi3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c4_default>; + pinctrl-1 =3D <&i2c4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c5: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x07af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c5_default>; + pinctrl-1 =3D <&i2c5_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi6: spi@7af6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x07af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&spi6_default>; + pinctrl-1 =3D <&spi6_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078db000 0x200>, + <0x078db200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + phy_type =3D "ulpi"; + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + status =3D "disabled"; + #reset-cells =3D <1>; + }; + + wcnss: remoteproc@a204000 { + compatible =3D "qcom,pronto-v3-pil", "qcom,pronto"; + reg =3D <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names =3D "ccu", "dxe", "pmu"; + + memory-region =3D <&wcnss_mem>; + + interrupts-extended =3D <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains =3D <&rpmpd MSM8917_VDDCX>, + <&rpmpd MSM8917_VDDMX>; + power-domain-names =3D "cx", "mx"; + + qcom,smem-states =3D <&wcnss_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + pinctrl-0 =3D <&wcnss_pin_a>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + + wcnss_iris: iris { + clocks =3D <&rpmcc RPM_SMD_RF_CLK2>; + clock-names =3D "xo"; + }; + + smd-edge { + interrupts =3D ; + + mboxes =3D <&apcs 17>; + qcom,smd-edge =3D <6>; + qcom,remote-pid =3D <4>; + + label =3D "pronto"; + + wcnss_ctrl: wcnss { + compatible =3D "qcom,wcnss"; + qcom,smd-channels =3D "WCNSS_CTRL"; + + qcom,mmio =3D <&wcnss>; + + wcnss_bt: bluetooth { + compatible =3D "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible =3D "qcom,wcnss-wlan"; + + interrupts =3D , + ; + interrupt-names =3D "tx", "rx"; + + qcom,smem-states =3D <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names =3D "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + }; + + a53pll: clock@b016000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b016000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table>; + + pll_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0x0b017000 0x1000>; + clocks =3D <&sleep_clk>; + }; + + timer@b120000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b120000 0x1000>; + clock-frequency =3D <19200000>; + + frame@b121000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0b123000 0x1000>; + status =3D "disabled"; + }; + + frame@b124000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0b124000 0x1000>; + status =3D "disabled"; + }; + + frame@b125000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0b125000 0x1000>; + status =3D "disabled"; + }; + + frame@b126000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0b126000 0x1000>; + status =3D "disabled"; + }; + + frame@b127000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0b127000 0x1000>; + status =3D "disabled"; + }; + + frame@b128000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x0b128000 0x1000>; + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; + + thermal_zones: thermal-zones { + aoss-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 4>; + + cooling-maps { + map0 { + trip =3D <&cpuss1_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpuss1_crit: cpuss1-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 5>; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu0_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 6>; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 7>; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu2_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu2_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 8>; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu3_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu3_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 9>; + + cooling-maps { + map0 { + trip =3D <&gpu_alert>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_alert: trip-point0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_crit: gpu-crit { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + }; + + mdm-core-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 1>; + + trips { + mdm_core_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + q6-thermal { + polling-delay-passive =3D <250>; + + thermal-sensors =3D <&tsens 2>; + + trips { + q6_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; +}; --=20 2.47.0