From nobody Sun Nov 24 00:32:57 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 249E021CF82 for ; Fri, 8 Nov 2024 23:46:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731109604; cv=none; b=uE/cgEe0hGztPQSp7gzyVKD6Pmy5pK+rOYz+jVKlnB0y1PGebrdDwot+115I6hx2wT/vdqYkVIJvIor39LOfct3uOx5AhG6r8FEmAoVSiJu05QoMzgriRDV1KDgrYeB586e6g8P1FAqrWzkM7sLzigKDbamqGN2QFrGdbTMoqMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731109604; c=relaxed/simple; bh=lxwX8wQlEPnS+PAZeVSY9HLlrY+iYxf2rLWu2wd8+M4=; h=Date:In-Reply-To:Message-Id:Mime-Version:References:Subject:From: To:Content-Type; b=vAkq3yXAH/qpgccgSsSwxUfjNJA1ZITEo1+V4A2cCg6HRNgGlFy/cTZurnRKb8hQKlJZYpzX3Z0LYm87hfNDZR1xWiTiaVHMkdSUClPpq8Lqs5BQxfWjB0VoV5IdTxstR1KJjqp9IcSskeCcyyvB8WhRAn/RsKHsfxv7pH7/BnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=fpOC0g+m; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="fpOC0g+m" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6ea95f530fdso51644357b3.1 for ; Fri, 08 Nov 2024 15:46:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1731109602; x=1731714402; darn=vger.kernel.org; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=eqWMrnzo0j4YyPMZKa2aiWl4n8rmwjjeUqcbD/Ug9qQ=; b=fpOC0g+mNqly1/ZQmdhE/FH/GJnQnHVLQNMlGauQFHY5KCQ7iO2qk8og+aySMu+RwF J+aCP8UtGQEf78Q1o0UOKFO9D29HYgcvDLAkGDVZDhyPJabVbFAYm1w39ljB+vHdjQ5m VN5Q93gKIdpWnzQXxSaxTWnQLN3FbKoRT+FIrmObm1oM1Cd/0QmTpJWxYf7tlEQ058AJ t8kgeboZVfbCVI5TumPVVkneCFwH02AxT7B9LJ75EfEYD21lspPBTyqTaLVt/fhsHbhl LQDq78xZgkbAKLu9NPbtVltJhXwO9lIgDUGMQiojdcRHj2+EWitYCIibMKVFhkeembMO 7rHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731109602; x=1731714402; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=eqWMrnzo0j4YyPMZKa2aiWl4n8rmwjjeUqcbD/Ug9qQ=; b=oKeeRnYTwaw2PY5icBCyCG881+ygBTmgg5Fk8CB3RxxtbQ7krRW4+mJVPNJlbmpCyd 8S3gfhLkDy4STpom4Wo4pYiXb7NPq3LzSdSKfWnC6ddb/CQL3ptElALxq1CK7+XVioCg WG6s+KWp+cZ5dVCZcvfIVph37ULv6NOy0Q/yWuMj9vnv9IFUvFPs6DgsWBAeulz5hFzC TmrikO86ITedFskSiChZiI569vR1lGFWP4ul5J29pltVVAw3z+j2WxVgJG36o5I+BsUH UEURyiD2VpYJJDBemvHl2Iyj6pnu8XfV7p9QXy61dXFZqf+EFVt4Vp/qiNAwrb+T1bcE Vy3Q== X-Forwarded-Encrypted: i=1; AJvYcCVCGhSgcLGYAQ4vUkiVQ/IPqWAIv/z8WxazOfVJ4EPK50MgLM/aBb4P4OGaqWY0oceCK2RvmlrCLIa4hU0=@vger.kernel.org X-Gm-Message-State: AOJu0YyFOAsdNqWiEo4JY7XB73bkIxnag87i1LsHNFfH8SoOTo7ihTH9 oIesb504LhgtLePl97Gh6kbIHQ8fXciJPJVyp9PQZEvaQHlWHQi86DF0WYdrQAPpxPSEddAyM6U UD9dWyQ== X-Google-Smtp-Source: AGHT+IHQv2/HetZIKd9sCauNhBkFTTcfGmC6Wh+WbHbWlZ+a9vS0rL2sguJXg20BQRNHR1FgsV28QiZqkehn X-Received: from irogers.svl.corp.google.com ([2620:15c:2c5:11:6fd2:1e36:6d8c:7c49]) (user=irogers job=sendgmr) by 2002:a0d:c7c5:0:b0:6ea:6872:2fe6 with SMTP id 00721157ae682-6eadde3cde7mr310537b3.4.1731109602037; Fri, 08 Nov 2024 15:46:42 -0800 (PST) Date: Fri, 8 Nov 2024 15:45:59 -0800 In-Reply-To: <20241108234606.429459-1-irogers@google.com> Message-Id: <20241108234606.429459-15-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241108234606.429459-1-irogers@google.com> X-Mailer: git-send-email 2.47.0.277.g8800431eea-goog Subject: [PATCH v4 14/20] perf riscv: Remove dwarf-regs.c and add dwarf-regs-table.h From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Guo Ren , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nick Terrell , "Masami Hiramatsu (Google)" , Changbin Du , Guilherme Amadio , Yang Jihong , Aditya Gupta , Athira Rajeev , Masahiro Yamada , Bibo Mao , Huacai Chen , Kajol Jain , Atish Patra , Shenlin Liang , Anup Patel , Oliver Upton , "Steinar H. Gunderson" , "Dr. David Alan Gilbert" , Chen Pei , Dima Kogan , Przemek Kitszel , "David S. Miller" , Alexander Lobakin , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-riscv@lists.infradead.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The file just provides the function get_arch_regstr, however, if in the only caller get_dwarf_regstr EM_HOST is used for the EM_NONE case, and the register table is provided in a header file, the function can never be called. So remove as dead code. Tidy up the EM_NONE cases for riscv in dwarf-regs.c. Reviewed-by: Masami Hiramatsu (Google) Signed-off-by: Ian Rogers --- .../dwarf-regs-table.h} | 32 ++++--------------- tools/perf/arch/riscv/util/Build | 1 - tools/perf/util/dwarf-regs.c | 7 ++-- tools/perf/util/include/dwarf-regs.h | 2 +- 4 files changed, 12 insertions(+), 30 deletions(-) rename tools/perf/arch/riscv/{util/dwarf-regs.c =3D> include/dwarf-regs-ta= ble.h} (56%) diff --git a/tools/perf/arch/riscv/util/dwarf-regs.c b/tools/perf/arch/risc= v/include/dwarf-regs-table.h similarity index 56% rename from tools/perf/arch/riscv/util/dwarf-regs.c rename to tools/perf/arch/riscv/include/dwarf-regs-table.h index a9c4402ae57e..a45b63a6d5a8 100644 --- a/tools/perf/arch/riscv/util/dwarf-regs.c +++ b/tools/perf/arch/riscv/include/dwarf-regs-table.h @@ -1,23 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. - * Mapping of DWARF debug register numbers into register names. - */ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifdef DEFINE_DWARF_REGSTR_TABLE +/* This is included in perf/util/dwarf-regs.c */ =20 -#include -#include /* for EINVAL */ -#include /* for strcmp */ -#include +#define REG_DWARFNUM_NAME(reg, idx) [idx] =3D "%" #reg =20 -struct regs_dwarfnum { - const char *name; - unsigned int dwarfnum; -}; - -#define REG_DWARFNUM_NAME(r, num) {.name =3D r, .dwarfnum =3D num} -#define REG_DWARFNUM_END {.name =3D NULL, .dwarfnum =3D 0} - -struct regs_dwarfnum riscv_dwarf_regs_table[] =3D { +static const char * const riscv_regstr_tbl[] =3D { REG_DWARFNUM_NAME("%zero", 0), REG_DWARFNUM_NAME("%ra", 1), REG_DWARFNUM_NAME("%sp", 2), @@ -50,13 +37,6 @@ struct regs_dwarfnum riscv_dwarf_regs_table[] =3D { REG_DWARFNUM_NAME("%t4", 29), REG_DWARFNUM_NAME("%t5", 30), REG_DWARFNUM_NAME("%t6", 31), - REG_DWARFNUM_END, }; =20 -#define RISCV_MAX_REGS ((sizeof(riscv_dwarf_regs_table) / \ - sizeof(riscv_dwarf_regs_table[0])) - 1) - -const char *get_arch_regstr(unsigned int n) -{ - return (n < RISCV_MAX_REGS) ? riscv_dwarf_regs_table[n].name : NULL; -} +#endif diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/= Build index 8f93091b8345..58a672246024 100644 --- a/tools/perf/arch/riscv/util/Build +++ b/tools/perf/arch/riscv/util/Build @@ -2,5 +2,4 @@ perf-util-y +=3D perf_regs.o perf-util-y +=3D header.o =20 perf-util-$(CONFIG_LIBTRACEEVENT) +=3D kvm-stat.o -perf-util-$(CONFIG_LIBDW) +=3D dwarf-regs.o perf-util-$(CONFIG_LIBDW_DWARF_UNWIND) +=3D unwind-libdw.o diff --git a/tools/perf/util/dwarf-regs.c b/tools/perf/util/dwarf-regs.c index 3d98c2bf6035..2c6b197556dd 100644 --- a/tools/perf/util/dwarf-regs.c +++ b/tools/perf/util/dwarf-regs.c @@ -20,6 +20,7 @@ #include "../arch/arm64/include/dwarf-regs-table.h" #include "../arch/sh/include/dwarf-regs-table.h" #include "../arch/powerpc/include/dwarf-regs-table.h" +#include "../arch/riscv/include/dwarf-regs-table.h" #include "../arch/s390/include/dwarf-regs-table.h" #include "../arch/sparc/include/dwarf-regs-table.h" #include "../arch/xtensa/include/dwarf-regs-table.h" @@ -33,7 +34,7 @@ const char *get_dwarf_regstr(unsigned int n, unsigned int= machine, unsigned int { #if EM_HOST =3D=3D EM_X86_64 || EM_HOST =3D=3D EM_386 || EM_HOST =3D=3D EM= _AARCH64 || EM_HOST =3D=3D EM_ARM \ || EM_HOST =3D=3D EM_CSKY || EM_HOST =3D=3D EM_LOONGARCH || EM_HOST = =3D=3D EM_MIPS || EM_HOST =3D=3D EM_PPC \ - || EM_HOST =3D=3D EM_PPC64 + || EM_HOST =3D=3D EM_PPC64 || EM_HOST =3D=3D EM_RISCV if (machine =3D=3D EM_NONE) { /* Generic arch - use host arch */ machine =3D EM_HOST; @@ -42,7 +43,7 @@ const char *get_dwarf_regstr(unsigned int n, unsigned int= machine, unsigned int switch (machine) { #if EM_HOST !=3D EM_X86_64 && EM_HOST !=3D EM_386 && EM_HOST !=3D EM_AARCH= 64 && EM_HOST !=3D EM_ARM \ && EM_HOST !=3D EM_CSKY && EM_HOST !=3D EM_LOONGARCH && EM_HOST !=3D E= M_MIPS && EM_HOST !=3D EM_PPC \ - && EM_HOST !=3D EM_PPC64 + && EM_HOST !=3D EM_PPC64 && EM_HOST !=3D EM_RISCV case EM_NONE: /* Generic arch - use host arch */ return get_arch_regstr(n); #endif @@ -63,6 +64,8 @@ const char *get_dwarf_regstr(unsigned int n, unsigned int= machine, unsigned int case EM_PPC: case EM_PPC64: return __get_dwarf_regstr(powerpc_regstr_tbl, n); + case EM_RISCV: + return __get_dwarf_regstr(riscv_regstr_tbl, n); case EM_SPARC: case EM_SPARCV9: return __get_dwarf_regstr(sparc_regstr_tbl, n); diff --git a/tools/perf/util/include/dwarf-regs.h b/tools/perf/util/include= /dwarf-regs.h index e47c4697da36..28075de8bcf4 100644 --- a/tools/perf/util/include/dwarf-regs.h +++ b/tools/perf/util/include/dwarf-regs.h @@ -91,7 +91,7 @@ #ifdef HAVE_LIBDW_SUPPORT #if !defined(__x86_64__) && !defined(__i386__) && !defined(__aarch64__) &&= !defined(__arm__) \ && !defined(__loongarch__) && !defined(__mips__) && !defined(__powerpc= __) \ - && !defined(__powerpc64__) + && !defined(__powerpc64__) && !defined(__riscv__) const char *get_arch_regstr(unsigned int n); #endif =20 --=20 2.47.0.277.g8800431eea-goog