From nobody Sat Nov 23 23:46:44 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C38C1AA1E7; Fri, 8 Nov 2024 18:52:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731091954; cv=none; b=g6hcynMVovLyLww/45peywTUTKu+wz51Pb7U50Zwv3DY+23f2Sx3GrIXCICkreBNCCJIsjvPDTMm6sLdxZRVY46tCeOfqWc12Q7z25FSMhkDhabitD1THhAel4XZOD/qVvwQ8Jnk0EZ9hDoLFThjy4P3Xj8JTjShudduEmkYH8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731091954; c=relaxed/simple; bh=zzcz+Stq2T7s9D0cmgD0YFLHantSHMsqXWl51R2tUCg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ibn+zg7hOwsd1eFpVYWGYv7ACQfjfXfAuB+g66AIQGghU0u+wF97enDbJULA28iqv8bMKLkoysIKCZJ578N3a8woWQWEd3+XqpVtdhh8Xx16JMSZp7ZMa2/wG3ywvCOXcDQ4CQzR/nAPetVkpiZnbvYXG8n+JmwOwqYeAYsoC6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=hV6unLtf; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="hV6unLtf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731091950; bh=zzcz+Stq2T7s9D0cmgD0YFLHantSHMsqXWl51R2tUCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hV6unLtfPWrM3YOLJ3wA7SThBaEEZQUBcI+28bEdF449hvRESbGdf/cxhSau/LDXj U4PLuKGLJi5AVpr2RzIVKRlSMF68j4cN7NaM+WbdP3aoeW+M3fT51wYXmMJ/oYCCaI OK0XQVfsVTlxDKS9QvhttqVeJTs20de7AdeynuA3pIQW/a1b1JAdSRFXGWT2/0fMUe YjYiQxqZPToVWZwZhkp4BZLmYf4cWVpG8rG4O7yTjvKwQGRvo9mklMhmg2IuSnUYnh VI8Ce4h/bSmBDVLl6xy3wjQ/YaiAks+iw2PzP+ztCv0poNFa02+85OBI84EudGSQQ9 aYrqnvPfdSGZg== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id C1CE817E376C; Fri, 8 Nov 2024 19:52:27 +0100 (CET) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Sandy Huang , Heiko Stubner , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Dragan Simic , Alexey Charkov , Jianfeng Liu , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, Detlev Casanova Subject: [PATCH v3 1/3] vop2: Add clock resets support Date: Fri, 8 Nov 2024 13:50:39 -0500 Message-ID: <20241108185212.198603-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241108185212.198603-1-detlev.casanova@collabora.com> References: <20241108185212.198603-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the end of initialization, each VP clock needs to be reset before they can be used. Failing to do so can put the VOP in an undefined state where the generated HDMI signal is either lost or not matching the selected mode. This issue can be reproduced by switching modes multiple times. Depending on the setup, after about 10 mode switches, the signal will be lost and the value in register 0x890 (VSYNCWIDTH + VFRONT) will take the va= lue `0x0000018c`. That makes VSYNCWIDTH=3D0, which is wrong. Adding the clock resets after the VOP configuration fixes the issue. Signed-off-by: Detlev Casanova --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 9873172e3fd3..6122eb18e6c9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #include @@ -157,6 +158,7 @@ struct vop2_win { struct vop2_video_port { struct drm_crtc crtc; struct vop2 *vop2; + struct reset_control *dclk_rst; struct clk *dclk; unsigned int id; const struct vop2_video_port_data *data; @@ -1917,6 +1919,26 @@ static int us_to_vertical_line(struct drm_display_mo= de *mode, int us) return us * mode->clock / mode->htotal / 1000; } =20 +static int vop2_clk_reset(struct vop2_video_port *vp) +{ + struct reset_control *rstc =3D vp->dclk_rst; + struct vop2 *vop2 =3D vp->vop2; + int ret; + + if (!rstc) + return 0; + + ret =3D reset_control_assert(rstc); + if (ret < 0) + drm_warn(vop2->drm, "failed to assert reset\n"); + udelay(10); + ret =3D reset_control_deassert(rstc); + if (ret < 0) + drm_warn(vop2->drm, "failed to deassert reset\n"); + + return ret; +} + static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -2057,6 +2079,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, =20 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); =20 + vop2_clk_reset(vp); + drm_crtc_vblank_on(crtc); =20 vop2_unlock(vop2); @@ -2708,6 +2732,12 @@ static int vop2_create_crtcs(struct vop2 *vop2) vp->data =3D vp_data; =20 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); + vp->dclk_rst =3D devm_reset_control_get_optional(vop2->dev, dclk_name); + if (IS_ERR(vp->dclk_rst)) { + drm_err(vop2->drm, "failed to get %s reset\n", dclk_name); + return PTR_ERR(vp->dclk_rst); + } + vp->dclk =3D devm_clk_get(vop2->dev, dclk_name); if (IS_ERR(vp->dclk)) { drm_err(vop2->drm, "failed to get %s\n", dclk_name); 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Fri, 8 Nov 2024 19:52:30 +0100 (CET) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Sandy Huang , Heiko Stubner , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Dragan Simic , Alexey Charkov , Jianfeng Liu , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, Detlev Casanova Subject: [PATCH v3 2/3] arm64: dts: rockchip: Add VOP clock resets for rk3588s Date: Fri, 8 Nov 2024 13:50:40 -0500 Message-ID: <20241108185212.198603-3-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241108185212.198603-1-detlev.casanova@collabora.com> References: <20241108185212.198603-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds the needed clock resets for all rk3588(s) based SOCs. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index fc67585b64b7..50064f39260c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1272,6 +1272,18 @@ vop: vop@fdd90000 { "pclk_vop"; iommus =3D <&vop_mmu>; power-domains =3D <&power RK3588_PD_VOP>; + resets =3D <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_D_VOP0>, + <&cru SRST_D_VOP1>, + <&cru SRST_D_VOP2>, + <&cru SRST_D_VOP3>; + reset-names =3D "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3"; rockchip,grf =3D <&sys_grf>; rockchip,vop-grf =3D <&vop_grf>; rockchip,vo1-grf =3D <&vo1_grf>; --=20 2.47.0 From nobody Sat Nov 23 23:46:44 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12D5B1C1F21; Fri, 8 Nov 2024 18:52:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731091960; cv=none; b=KySmEuJrmcGTKCjF/zXNB9Sxx5AZYyBE1cw28e1ovI8oMA7qwV6A6rQenJhKPVdHRaaj+TiNlrowwVdm1r/21ZMftyKUctBbnHk23nS0S5ryGkOCRFpAPMK1CRG6y157vQ8D0YtMUAVPpvS4s3cFGgRnZdtidvkxnM/g8Iq/ExM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731091960; c=relaxed/simple; bh=69F+XwHGUM8j8Npu0CVV/bvnKz12bT/JSO/FqsNELcI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k6BoXTh3vREmKh8k64c8NWVwr8o7lViCOJBL2szBFOjJ4doKEGNtQLSfTVXOAiQ77JwiNAWo4PrnEwp0kXxWoi6XFgft1SCDDor+QI0lrXneBKQr/FeQNLHNPXAn22uegay1nkplEdEX612txMRLe5PKlPy8Q67jHNC2zIpHE7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=gxZ8JrRO; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="gxZ8JrRO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731091957; bh=69F+XwHGUM8j8Npu0CVV/bvnKz12bT/JSO/FqsNELcI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gxZ8JrRO6t3KYBAYrnFkHOPCL/5Yxe3jqsw9SPxYt2ta/JHJB6SkhPQBfiqMcr44y P4+zIAAi2twZ/QxYywjpghDPcuDArxlYYzT9MtPWwL86l9BQ6gorsdxHj8zqUo5ROL /w1ky90u+sQrBJcWsGKcBjPOj9npFAIAoxvQKAeBgquDfpu8RqBXsou5TaDQFopVcD ILQvaX8nUA/rLvjrjQn+5Rspwrex5SUdCdt6JHTcVNYiBD/FWFFPBZTjWDLFQaycc0 GdWqS0J2qpDMJyO8l85plGqYlVCcKHuzOmrhpi4dx/FfEXbHTGxyMUgE+CQtF+xuX/ fjYO3xBTMPFug== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4088D17E3770; Fri, 8 Nov 2024 19:52:34 +0100 (CET) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Sandy Huang , Heiko Stubner , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Dragan Simic , Alexey Charkov , Jianfeng Liu , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, Detlev Casanova , Conor Dooley Subject: [PATCH v3 3/3] dt-bindings: display: vop2: Add VP clock resets Date: Fri, 8 Nov 2024 13:50:41 -0500 Message-ID: <20241108185212.198603-4-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241108185212.198603-1-detlev.casanova@collabora.com> References: <20241108185212.198603-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the documentation for VOP2 video ports reset clocks. One reset can be set per video port. Reviewed-by: Conor Dooley Signed-off-by: Detlev Casanova --- .../display/rockchip/rockchip-vop2.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vo= p2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.= yaml index 2531726af306..5b59d91de47b 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -65,6 +65,26 @@ properties: - const: dclk_vp3 - const: pclk_vop =20 + resets: + minItems: 5 + items: + - description: AXI clock reset. + - description: AHB clock reset. + - description: Pixel clock reset for video port 0. + - description: Pixel clock reset for video port 1. + - description: Pixel clock reset for video port 2. + - description: Pixel clock reset for video port 3. + + reset-names: + minItems: 5 + items: + - const: aclk + - const: hclk + - const: dclk_vp0 + - const: dclk_vp1 + - const: dclk_vp2 + - const: dclk_vp3 + rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -128,6 +148,11 @@ allOf: clock-names: minItems: 7 =20 + resets: + minItems: 6 + reset-names: + minItems: 6 + ports: required: - port@0 @@ -152,6 +177,11 @@ allOf: clock-names: maxItems: 5 =20 + resets: + maxItems: 5 + reset-names: + maxItems: 5 + ports: required: - port@0 @@ -183,6 +213,16 @@ examples: "dclk_vp0", "dclk_vp1", "dclk_vp2"; + resets =3D <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_VOP0>, + <&cru SRST_VOP1>, + <&cru SRST_VOP2>; + reset-names =3D "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; power-domains =3D <&power RK3568_PD_VO>; iommus =3D <&vop_mmu>; vop_out: ports { --=20 2.47.0