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charset="utf-8" Add clocks, assigned-clocks and assigned-clock-parents for ICSSG Signed-off-by: MD Danish Anwar --- Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Docum= entation/devicetree/bindings/soc/ti/ti,pruss.yaml index 3cb1471cc6b6..12350409d154 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -92,6 +92,11 @@ properties: description: | This property is as per sci-pm-domain.txt. =20 + clocks: + items: + - description: ICSSG_CORE Clock + - description: ICSSG_ICLK Clock + patternProperties: =20 memories@[a-f0-9]+$: --=20 2.34.1 From nobody Sun Nov 24 01:05:50 2024 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF9E81F4702; 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charset="utf-8" ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at 333MHz. ICSSG_CORE clock will help get the most out of ICSSG as more cycles are needed to fully support all ICSSG features. This commit also changes assigned-clock-parents of coreclk-mux to ICSSG_CORE clock from ICSSG_ICLK. Performance update in dual mac mode With ICSSG_CORE Clk @ 333MHz Tx throughput - 934 Mbps Rx throuhput - 914 Mbps, With ICSSG_ICLK clk @ 250MHz, Tx throughput - 920 Mbps Rx throughput - 706 Mbps Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index c66289a4362b..ceceee2affd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1227,6 +1227,10 @@ icssg0: icssg@30000000 { #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x0 0x00 0x30000000 0x80000>; + clocks =3D <&k3_clks 81 0>, /* icssg0_core_clk */ + <&k3_clks 81 20>; /* icssg0_iclk */ + assigned-clocks =3D <&k3_clks 81 0>; + assigned-clock-parents =3D <&k3_clks 81 2>; =20 icssg0_mem: memories@0 { reg =3D <0x0 0x2000>, @@ -1252,7 +1256,7 @@ icssg0_coreclk_mux: coreclk-mux@3c { clocks =3D <&k3_clks 81 0>, /* icssg0_core_clk */ <&k3_clks 81 20>; /* icssg0_iclk */ assigned-clocks =3D <&icssg0_coreclk_mux>; - assigned-clock-parents =3D <&k3_clks 81 20>; + assigned-clock-parents =3D <&k3_clks 81 0>; }; =20 icssg0_iepclk_mux: iepclk-mux@30 { @@ -1397,6 +1401,10 @@ icssg1: icssg@30080000 { #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x0 0x00 0x30080000 0x80000>; + clocks =3D <&k3_clks 82 0>, /* icssg1_core_clk */ + <&k3_clks 82 20>; /* icssg1_iclk */ + assigned-clocks =3D <&k3_clks 82 0>; + assigned-clock-parents =3D <&k3_clks 82 2>; =20 icssg1_mem: memories@0 { reg =3D <0x0 0x2000>, @@ -1422,7 +1430,7 @@ icssg1_coreclk_mux: coreclk-mux@3c { clocks =3D <&k3_clks 82 0>, /* icssg1_core_clk */ <&k3_clks 82 20>; /* icssg1_iclk */ assigned-clocks =3D <&icssg1_coreclk_mux>; - assigned-clock-parents =3D <&k3_clks 82 20>; + assigned-clock-parents =3D <&k3_clks 82 0>; }; =20 icssg1_iepclk_mux: iepclk-mux@30 { --=20 2.34.1