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charset="utf-8" Blaize, Inc. (www.blaize.com) is a SoC manufacturer with integrated programmable Graph-Streaming-Processors for AI and ML. Resolves: PESW-2604 Reviewed-by: Rob Herring (Arm) Signed-off-by: Nikolaos Pasaloukos --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index b97d298b3eb6..746ff14028d1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -214,6 +214,8 @@ patternProperties: description: Shenzhen BigTree Tech Co., LTD "^bitmain,.*": description: Bitmain Technologies + "^blaize,.*": + description: Blaize, Inc. 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charset="utf-8" Add device tree bindings for the Blaize BLZP1600 CB2 development board (carrier board), which uses the BLZP1600 SoM. Resolves: PESW-2604 Checkpatch: ignore Reviewed-by: James Cowgill Reviewed-by: Matt Redfearn Reviewed-by: Neil Jones Signed-off-by: Nikolaos Pasaloukos --- .../devicetree/bindings/arm/blaize.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentat= ion/devicetree/bindings/arm/blaize.yaml new file mode 100644 index 000000000000..e93e1b8ececc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/blaize.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/blaize.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Blaize Platforms + +maintainers: + - James Cowgill + - Matt Redfearn + - Neil Jones + - Nikolaos Pasaloukos + +description: | + Blaize Platforms using SoCs designed by Blaize Inc. + + The products currently based on the BLZP1600 SoC: + + - BLZP1600-SoM: SoM module + - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Blaize BLZP1600 based boards + items: + - enum: + - blaize,blzp1600-cb2 + - const: blaize,blzp1600 + +additionalProperties: true + +... --=20 2.43.0 From nobody Sat Nov 23 23:47:47 2024 Received: from mx07-0063e101.pphosted.com (mx07-0063e101.pphosted.com [205.220.184.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 252CE1E2833; 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charset="utf-8" Add ARCH_BLAIZE_BLZP1600 SoC family to the arm64 architecture. Resolves: PESW-2604 Checkpatch: ignore Reviewed-by: James Cowgill Reviewed-by: Matt Redfearn Reviewed-by: Neil Jones Signed-off-by: Nikolaos Pasaloukos --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad5..c2a523637b23 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -94,6 +94,11 @@ config ARCH_BITMAIN help This enables support for the Bitmain SoC Family. =20 +config ARCH_BLAIZE_BLZP1600 + bool "Blaize BLZP1600 SoC Platforms" + help + This enables support for the Blaize BLZP1600 SoC family + config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG --=20 2.43.0 From nobody Sat Nov 23 23:47:47 2024 Received: from mx07-0063e101.pphosted.com (mx07-0063e101.pphosted.com [205.220.184.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2526D1E2603; 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b=EQ1h+vx/IpD/tdF/bsU0DUXF7Ec6wxII7PZf3TUB0SU+6ZTFNN9Peuk5+2NC1DhKmb7zTiKdWjplVyrHUOFcFwwBNzyKiyu9xzoRT9rhtVHjB/oJwvtlAeAd4Q7qqttTeHX6TbNGT5rJctd4O03Sbi53/IycIhsjpjq7dn3I6Yw= Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:12a::5) by PN0PR01MB7813.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:b5::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21; Fri, 8 Nov 2024 10:31:58 +0000 Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655]) by MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655%4]) with mapi id 15.20.8137.019; Fri, 8 Nov 2024 10:31:58 +0000 From: Niko Pasaloukos To: James Cowgill , Matt Redfearn , Neil Jones , Niko Pasaloukos , "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , "hverkuil-cisco@xs4all.nl" , "shawnguo@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "angelogioacchino.delregno@collabora.com" , "nm@ti.com" , "neil.armstrong@linaro.org" , "nfraprado@collabora.com" , "johan+linaro@kernel.org" CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v4 4/6] arm64: Add initial support for Blaize BLZP1600 CB2 Thread-Topic: [PATCH v4 4/6] arm64: Add initial support for Blaize BLZP1600 CB2 Thread-Index: AQHbMclwfRt3f4mfrUa2QPPbgzG5og== Date: Fri, 8 Nov 2024 10:31:57 +0000 Message-ID: <20241108103120.9955-5-nikolaos.pasaloukos@blaize.com> References: <20241108103120.9955-1-nikolaos.pasaloukos@blaize.com> In-Reply-To: <20241108103120.9955-1-nikolaos.pasaloukos@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|PN0PR01MB7813:EE_ x-ms-office365-filtering-correlation-id: d268f0a5-69ee-4ed0-a738-08dcffe092ba x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|38070700018|921020; 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charset="utf-8" Adds support for the Blaize CB2 development board based on BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM. The blaize-blzp1600.dtsi is the common part for the SoC, blaize-blzp1600-som.dtsi is the common part for the SoM and blaize-blzp1600-cb2.dts is the board specific file. Checkpatch: ignore Resolves: PESW-2604 Co-developed-by: James Cowgill Signed-off-by: James Cowgill Co-developed-by: Matt Redfearn Signed-off-by: Matt Redfearn Co-developed-by: Neil Jones Signed-off-by: Neil Jones Signed-off-by: Nikolaos Pasaloukos --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/blaize/Makefile | 2 + .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++ .../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++ .../boot/dts/blaize/blaize-blzp1600.dtsi | 205 ++++++++++++++++++ 5 files changed, 315 insertions(+) create mode 100644 arch/arm64/boot/dts/blaize/Makefile create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 30dd6347a929..601b6381ea0c 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y +=3D apm subdir-y +=3D apple subdir-y +=3D arm subdir-y +=3D bitmain +subdir-y +=3D blaize subdir-y +=3D broadcom subdir-y +=3D cavium subdir-y +=3D exynos diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blai= ze/Makefile new file mode 100644 index 000000000000..9118d7fb600f --- /dev/null +++ b/arch/arm64/boot/dts/blaize/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) +=3D blaize-blzp1600-cb2.dtb diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm6= 4/boot/dts/blaize/blaize-blzp1600-cb2.dts new file mode 100644 index 000000000000..5416f7e84ac0 --- /dev/null +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Blaize, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "blaize-blzp1600-som.dtsi" +#include + +/ { + model =3D "Blaize BLZP1600 SoM1600P CB2 Development Board"; + + compatible =3D "blaize,blzp1600-cb2", "blaize,blzp1600"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200"; + }; +}; + +&i2c0 { + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&i2c3 { + clock-frequency =3D <100000>; + status =3D "okay"; + + gpio_expander: gpio@74 { + compatible =3D "ti,tca9539"; + reg =3D <0x74>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "RSP_PIN_7", /* GPIO_0 */ + "RSP_PIN_11", /* GPIO_1 */ + "RSP_PIN_13", /* GPIO_2 */ + "RSP_PIN_15", /* GPIO_3 */ + "RSP_PIN_27", /* GPIO_4 */ + "RSP_PIN_29", /* GPIO_5 */ + "RSP_PIN_31", /* GPIO_6 */ + "RSP_PIN_33", /* GPIO_7 */ + "RSP_PIN_37", /* GPIO_8 */ + "RSP_PIN_16", /* GPIO_9 */ + "RSP_PIN_18", /* GPIO_10 */ + "RSP_PIN_22", /* GPIO_11 */ + "RSP_PIN_28", /* GPIO_12 */ + "RSP_PIN_32", /* GPIO_13 */ + "RSP_PIN_36", /* GPIO_14 */ + "TP31"; /* GPIO_15 */ + }; + + gpio_expander_m2: gpio@75 { + compatible =3D "ti,tca9539"; + reg =3D <0x75>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "M2_W_DIS1_N", /* GPIO_0 */ + "M2_W_DIS2_N", /* GPIO_1 */ + "M2_UART_WAKE_N", /* GPIO_2 */ + "M2_COEX3", /* GPIO_3 */ + "M2_COEX_RXD", /* GPIO_4 */ + "M2_COEX_TXD", /* GPIO_5 */ + "M2_VENDOR_PIN40", /* GPIO_6 */ + "M2_VENDOR_PIN42", /* GPIO_7 */ + "M2_VENDOR_PIN38", /* GPIO_8 */ + "M2_SDIO_RST_N", /* GPIO_9 */ + "M2_SDIO_WAKE_N", /* GPIO_10 */ + "M2_PETN1", /* GPIO_11 */ + "M2_PERP1", /* GPIO_12 */ + "M2_PERN1", /* GPIO_13 */ + "UIM_SWP", /* GPIO_14 */ + "UART1_TO_RSP"; /* GPIO_15 */ + }; +}; diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm= 64/boot/dts/blaize/blaize-blzp1600-som.dtsi new file mode 100644 index 000000000000..d54707c17163 --- /dev/null +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Blaize, Inc. All rights reserved. + */ + +#include "blaize-blzp1600.dtsi" + +/ { + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x00000000 0xffffffff>; + }; +}; + +/* i2c4 bus is available only on the SoM, not on the board */ +&i2c4 { + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/b= oot/dts/blaize/blaize-blzp1600.dtsi new file mode 100644 index 000000000000..6d524d0dba62 --- /dev/null +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 Blaize, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <1>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + firmware { + scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82002000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + shmem =3D <&scmi0_shm>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + + scmi_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>; + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + /* SCMI reserved buffer space on DDR space */ + scmi0_shm: scmi-shmem@800 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x800 0x80>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D /* Physical Secure PPI */ + , + /* Physical Non-Secure PPI */ + , + /* Hypervisor PPI */ + , + /* Virtual PPI */ + ; + }; + + soc@200000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x2 0x0 0x850000>; + + gic: interrupt-controller@410000 { + compatible =3D "arm,gic-400"; + reg =3D <0x410000 0x20000>, + <0x420000 0x20000>, + <0x440000 0x20000>, + <0x460000 0x20000>; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D ; + }; + + uart0: serial@4d0000 { + compatible =3D "ns16550a"; + reg =3D <0x4d0000 0x1000>; + clocks =3D <&scmi_clk 59>; + resets =3D <&scmi_rst 59>; + reg-shift =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart1: serial@4e0000 { + compatible =3D "ns16550a"; + reg =3D <0x4e0000 0x1000>; + clocks =3D <&scmi_clk 60>; + resets =3D <&scmi_rst 60>; + reg-shift =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + i2c0: i2c@4f0000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x4f0000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk 54>; + resets =3D <&scmi_rst 54>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@500000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x500000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk 55>; + resets =3D <&scmi_rst 55>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@510000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x510000 0x1000>; + interrupts =3D ; + clocks =3D <&scmi_clk 56>; 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b=THQPlKftbIyP3I82Pq1DEKqOZnPCEAL77rBuHg0qVwq7eu6kMoaD878EZPA3RILKkJLWsABmFqzb1rxUBDdHveNwFIoZJwRyLEt6K4YQJggr0u/EffzKAxSUoBtu2OLVYN3FUnw9MEnAWkuDkyhKC4Wldrdb4UdTl1/8JKp9JLc= Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:12a::5) by PN0PR01MB7813.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:b5::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21; Fri, 8 Nov 2024 10:31:58 +0000 Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655]) by MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655%4]) with mapi id 15.20.8137.019; Fri, 8 Nov 2024 10:31:58 +0000 From: Niko Pasaloukos To: James Cowgill , Matt Redfearn , Neil Jones , Niko Pasaloukos , "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , "hverkuil-cisco@xs4all.nl" , "shawnguo@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "angelogioacchino.delregno@collabora.com" , "nm@ti.com" , "neil.armstrong@linaro.org" , "nfraprado@collabora.com" , "johan+linaro@kernel.org" CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v4 5/6] arm64: defconfig: Enable ARCH_BLAIZE_BLZP1600 Thread-Topic: [PATCH v4 5/6] arm64: defconfig: Enable ARCH_BLAIZE_BLZP1600 Thread-Index: AQHbMclwCwq7DoKch0yhrxts1OZQHw== Date: Fri, 8 Nov 2024 10:31:58 +0000 Message-ID: <20241108103120.9955-6-nikolaos.pasaloukos@blaize.com> References: <20241108103120.9955-1-nikolaos.pasaloukos@blaize.com> In-Reply-To: <20241108103120.9955-1-nikolaos.pasaloukos@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|PN0PR01MB7813:EE_ x-ms-office365-filtering-correlation-id: 6d7fa88b-6177-4504-c360-08dcffe09338 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|38070700018|921020; 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charset="utf-8" Enable ARCH_BLAIZE_BLZP1600 to get proper build coverage. Resolves: PESW-2604 Signed-off-by: Nikolaos Pasaloukos --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..7d368a8911bf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -43,6 +43,7 @@ CONFIG_ARCH_BCM_IPROC=3Dy CONFIG_ARCH_BCMBCA=3Dy CONFIG_ARCH_BRCMSTB=3Dy CONFIG_ARCH_BERLIN=3Dy +CONFIG_ARCH_BLAIZE_BLZP1600=3Dy CONFIG_ARCH_EXYNOS=3Dy CONFIG_ARCH_SPARX5=3Dy CONFIG_ARCH_K3=3Dy --=20 2.43.0 From nobody Sat Nov 23 23:47:47 2024 Received: from mx07-0063e101.pphosted.com (mx07-0063e101.pphosted.com [205.220.184.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 251D71DE8A8; Fri, 8 Nov 2024 10:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=205.220.184.123 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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b=NF8W7dfMOGtnO0J2Bq4gF+TQuiSS09HtF1c1vOdI9hZeNGrGAfMHEY6UAAYOjIH9MgTWyPeHkaAyB6Ynf82J1f0S7M29c3luVNJ/3P0EFgsw+mkpVmlRslD/HeUwm9wzP/d7BzCnjlJdxIrBSgDmekr6V0rQwohTkb/iNCAfLSs= Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:12a::5) by PN0PR01MB7813.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:b5::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21; Fri, 8 Nov 2024 10:31:59 +0000 Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655]) by MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655%4]) with mapi id 15.20.8137.019; Fri, 8 Nov 2024 10:31:59 +0000 From: Niko Pasaloukos To: James Cowgill , Matt Redfearn , Neil Jones , Niko Pasaloukos , "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , "hverkuil-cisco@xs4all.nl" , "shawnguo@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "angelogioacchino.delregno@collabora.com" , "nm@ti.com" , "neil.armstrong@linaro.org" , "nfraprado@collabora.com" , "johan+linaro@kernel.org" CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v4 6/6] MAINTAINER: Add entry for Blaize SoC Thread-Topic: [PATCH v4 6/6] MAINTAINER: Add entry for Blaize SoC Thread-Index: AQHbMclxND9+YNk/m0CAi4+5zBw6OQ== Date: Fri, 8 Nov 2024 10:31:59 +0000 Message-ID: <20241108103120.9955-7-nikolaos.pasaloukos@blaize.com> References: <20241108103120.9955-1-nikolaos.pasaloukos@blaize.com> In-Reply-To: <20241108103120.9955-1-nikolaos.pasaloukos@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|PN0PR01MB7813:EE_ x-ms-office365-filtering-correlation-id: eb965b58-4262-42cb-64ce-08dcffe093be x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|38070700018|921020; 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charset="utf-8" Add MAINTAINERS entry for Blaize SoC platform with a list of maintainers. Resolves: PESW-2604 Signed-off-by: Nikolaos Pasaloukos --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9db17a2fe3b0..11ede0281316 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2037,6 +2037,15 @@ F: arch/arm64/boot/dts/bitmain/ F: drivers/clk/clk-bm1880.c F: drivers/pinctrl/pinctrl-bm1880.c =20 +ARM/BLAIZE ARCHITECTURE +M: James Cowgill +M: Matt Redfearn +M: Neil Jones +M: Nikolaos Pasaloukos +S: Maintained +F: Documentation/devicetree/bindings/arm/blaize.yaml +F: arch/arm64/boot/dts/blaize/ + ARM/CALXEDA HIGHBANK ARCHITECTURE M: Andre Przywara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0