From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C02A1E0DAC; Fri, 8 Nov 2024 10:29:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.89.224.132 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731061776; cv=none; b=FdQXbKrKi7J1umZjVzAjXHMR20QehApG7ms/odfFS0nQECiD7kqz641121s7RS0QozRDy5dfrPwobMi6uP10KWaNdkeuMc5TV0QyDa5D+qpEHGvRLEcI7DHNh+DheoxC91r8Ghn3hclBpXkauYabqBibJ/iblU+pDyw/cVsRIYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731061776; c=relaxed/simple; bh=X2H+XrbQ/GrQDJB0Xc9tQVfKae/vZngNpsMz83vReb0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YDo0mepLRBntgm/BHHd2jkJaspEKgh8BM9DJPr2o4G/6W7Hz6B/MG6ZHPJo4NPgHKhS6FRCt/Kf9JSEi2rAFEOPPA7bO1lQ1mg0eYu5oQLpc7rIhnqXqOBRK2teVWdcuXKEfiGxcGM5pUptlhlPumbGOjtcZw2giGXvvqs5V8aw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com; spf=pass smtp.mailfrom=salutedevices.com; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b=VIWEhO0v; arc=none smtp.client-ip=45.89.224.132 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=salutedevices.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b="VIWEhO0v" Received: from p-infra-ksmg-sc-msk02.sberdevices.ru (localhost [127.0.0.1]) by mx1.sberdevices.ru (Postfix) with ESMTP id 2C03012002E; Fri, 8 Nov 2024 13:29:25 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.sberdevices.ru 2C03012002E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=salutedevices.com; s=mail; t=1731061765; bh=WFuAArP6J98eZb/1JhFy1BBqp0mr+GrAAmxwASrRsUI=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=VIWEhO0vQE3PJyg3XT/wxB10Kg/BJllw5SNZU3cmnVRIr7XZdMcXiOjXWM5M2vJEQ JCo7gD+SY58c9dQdZ1gO3FxcTkryeuOM+1aPG1+E1YZhQaclcr/8jtlG0xEITr42xi IHoJnmcE8ZOK7yw25S0P5LSDtlGsgON49hT8UbsGbo6Dd2q9O2eC5fDmbRtuLSk/h/ q15wyeG6o5sE7vjGtRPS9im7O5dZW/8hB5nuDKQYZ8H3ElbWTom7RI4m7J1VaMH5uY kIuZDVaAdspGDs8V/n9qiJom48oHxhBLCi3rEaSXWEopoPJw8ESZ9Bc2OKOuFoeJli a7NfzKbDaSO9g== Received: from smtp.sberdevices.ru (p-i-exch-sc-m02.sberdevices.ru [172.16.192.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.sberdevices.ru (Postfix) with ESMTPS; Fri, 8 Nov 2024 13:29:25 +0300 (MSK) From: Alexey Romanov To: , , , , , , , , , , , CC: , , , , , , "Alexey Romanov" Subject: [PATCH v10 01/22] crypto: amlogic - Don't hardcode IRQ count Date: Fri, 8 Nov 2024 13:28:46 +0300 Message-ID: <20241108102907.1788584-2-avromanov@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108102907.1788584-1-avromanov@salutedevices.com> References: <20241108102907.1788584-1-avromanov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189039 [Nov 08 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: avromanov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;smtp.sberdevices.ru:7.1.1,5.0.1;127.0.0.199:7.1.2, FromAlignment: s X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/08 08:34:00 #26834472 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" IRQ count is no longer hardcoded, and make it part of struct meson_flow. We need this for extend driver support for other Amlogic SoC's. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 2 +- drivers/crypto/amlogic/amlogic-gxl-core.c | 47 ++++++++++++--------- drivers/crypto/amlogic/amlogic-gxl.h | 8 ++-- 3 files changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index 29048da6f50a..b19032f92415 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -19,7 +19,7 @@ =20 static int get_engine_number(struct meson_dev *mc) { - return atomic_inc_return(&mc->flow) % MAXFLOW; + return atomic_inc_return(&mc->flow) % mc->flow_cnt; } =20 static bool meson_cipher_need_fallback(struct skcipher_request *areq) diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 1c18a5b8470e..dc35d7304eb0 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -28,8 +28,8 @@ static irqreturn_t meson_irq_handler(int irq, void *data) int flow; u32 p; =20 - for (flow =3D 0; flow < MAXFLOW; flow++) { - if (mc->irqs[flow] =3D=3D irq) { + for (flow =3D 0; flow < mc->flow_cnt; flow++) { + if (mc->chanlist[flow].irq =3D=3D irq) { p =3D readl(mc->base + ((0x04 + flow) << 2)); if (p) { writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2)); @@ -110,7 +110,7 @@ static int meson_debugfs_show(struct seq_file *seq, voi= d *v) struct meson_dev *mc __maybe_unused =3D seq->private; int i; =20 - for (i =3D 0; i < MAXFLOW; i++) + for (i =3D 0; i < mc->flow_cnt; i++) seq_printf(seq, "Channel %d: nreq %lu\n", i, #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG mc->chanlist[i].stat_req); @@ -153,14 +153,32 @@ static void meson_free_chanlist(struct meson_dev *mc,= int i) */ static int meson_allocate_chanlist(struct meson_dev *mc) { + struct platform_device *pdev =3D to_platform_device(mc->dev); int i, err; =20 - mc->chanlist =3D devm_kcalloc(mc->dev, MAXFLOW, + mc->flow_cnt =3D platform_irq_count(pdev); + if (mc->flow_cnt <=3D 0) { + dev_err(mc->dev, "No IRQs defined\n"); + return -ENODEV; + } + + mc->chanlist =3D devm_kcalloc(mc->dev, mc->flow_cnt, sizeof(struct meson_flow), GFP_KERNEL); if (!mc->chanlist) return -ENOMEM; =20 - for (i =3D 0; i < MAXFLOW; i++) { + for (i =3D 0; i < mc->flow_cnt; i++) { + mc->chanlist[i].irq =3D platform_get_irq(pdev, i); + if (mc->chanlist[i].irq < 0) + return mc->chanlist[i].irq; + + err =3D devm_request_irq(mc->dev, mc->chanlist[i].irq, + meson_irq_handler, 0, "aml-crypto", mc); + if (err < 0) { + dev_err(mc->dev, "Cannot request IRQ for flow %d\n", i); + return err; + } + init_completion(&mc->chanlist[i].complete); =20 mc->chanlist[i].engine =3D crypto_engine_alloc_init(mc->dev, true); @@ -230,7 +248,7 @@ static void meson_unregister_algs(struct meson_dev *mc) static int meson_crypto_probe(struct platform_device *pdev) { struct meson_dev *mc; - int err, i; + int err; =20 mc =3D devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); if (!mc) @@ -250,19 +268,6 @@ static int meson_crypto_probe(struct platform_device *= pdev) return err; } =20 - for (i =3D 0; i < MAXFLOW; i++) { - mc->irqs[i] =3D platform_get_irq(pdev, i); - if (mc->irqs[i] < 0) - return mc->irqs[i]; - - err =3D devm_request_irq(&pdev->dev, mc->irqs[i], meson_irq_handler, 0, - "gxl-crypto", mc); - if (err < 0) { - dev_err(mc->dev, "Cannot request IRQ for flow %d\n", i); - return err; - } - } - err =3D clk_prepare_enable(mc->busclk); if (err !=3D 0) { dev_err(&pdev->dev, "Cannot prepare_enable busclk\n"); @@ -292,7 +297,7 @@ static int meson_crypto_probe(struct platform_device *p= dev) error_alg: meson_unregister_algs(mc); error_flow: - meson_free_chanlist(mc, MAXFLOW - 1); + meson_free_chanlist(mc, mc->flow_cnt - 1); clk_disable_unprepare(mc->busclk); return err; } @@ -307,7 +312,7 @@ static void meson_crypto_remove(struct platform_device = *pdev) =20 meson_unregister_algs(mc); =20 - meson_free_chanlist(mc, MAXFLOW - 1); + meson_free_chanlist(mc, mc->flow_cnt - 1); =20 clk_disable_unprepare(mc->busclk); } diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index d68094ffb70a..9f1ef87333ae 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -22,8 +22,6 @@ #define MESON_OPMODE_ECB 0 #define MESON_OPMODE_CBC 1 =20 -#define MAXFLOW 2 - #define MAXDESC 64 =20 #define DESC_LAST BIT(18) @@ -62,6 +60,7 @@ struct meson_desc { * @keylen: keylen for this flow operation * @complete: completion for the current task on this flow * @status: set to 1 by interrupt if task is done + * @irq: IRQ number for amlogic-crypto * @t_phy: Physical address of task * @tl: pointer to the current ce_task for this flow * @stat_req: number of request done by this flow @@ -70,6 +69,7 @@ struct meson_flow { struct crypto_engine *engine; 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Fri, 8 Nov 2024 13:29:26 +0300 (MSK) From: Alexey Romanov To: , , , , , , , , , , , CC: , , , , , , "Alexey Romanov" Subject: [PATCH v10 02/22] crypto: amlogic - Add platform data Date: Fri, 8 Nov 2024 13:28:47 +0300 Message-ID: <20241108102907.1788584-3-avromanov@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108102907.1788584-1-avromanov@salutedevices.com> References: <20241108102907.1788584-1-avromanov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189039 [Nov 08 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: avromanov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_from_domain_doesnt_match_to}, smtp.sberdevices.ru:5.0.1,7.1.1;127.0.0.199:7.1.2;salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1, FromAlignment: s X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/08 08:34:00 #26834472 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" To support other Amlogic SoC's we have to use platform data: descriptors and status registers offsets are individual for each SoC series. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 2 +- drivers/crypto/amlogic/amlogic-gxl-core.c | 22 +++++++++++++++++---- drivers/crypto/amlogic/amlogic-gxl.h | 11 +++++++++++ 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index b19032f92415..7eff3ae7356f 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -225,7 +225,7 @@ static int meson_cipher(struct skcipher_request *areq) =20 reinit_completion(&mc->chanlist[flow].complete); mc->chanlist[flow].status =3D 0; - writel(mc->chanlist[flow].t_phy | 2, mc->base + (flow << 2)); + writel(mc->chanlist[flow].t_phy | 2, mc->base + ((mc->pdata->descs_reg + = flow) << 2)); wait_for_completion_interruptible_timeout(&mc->chanlist[flow].complete, msecs_to_jiffies(500)); if (mc->chanlist[flow].status =3D=3D 0) { diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index dc35d7304eb0..d7e455f73c04 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -18,6 +18,7 @@ #include #include #include +#include #include =20 #include "amlogic-gxl.h" @@ -30,9 +31,10 @@ static irqreturn_t meson_irq_handler(int irq, void *data) =20 for (flow =3D 0; flow < mc->flow_cnt; flow++) { if (mc->chanlist[flow].irq =3D=3D irq) { - p =3D readl(mc->base + ((0x04 + flow) << 2)); + p =3D readl(mc->base + ((mc->pdata->status_reg + flow) << 2)); if (p) { - writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2)); + writel_relaxed(0xF, mc->base + + ((mc->pdata->status_reg + flow) << 2)); mc->chanlist[flow].status =3D 1; complete(&mc->chanlist[flow].complete); return IRQ_HANDLED; @@ -254,6 +256,10 @@ static int meson_crypto_probe(struct platform_device *= pdev) if (!mc) return -ENOMEM; =20 + mc->pdata =3D of_device_get_match_data(&pdev->dev); + if (!mc->pdata) + return -EINVAL; + mc->dev =3D &pdev->dev; platform_set_drvdata(pdev, mc); =20 @@ -317,9 +323,17 @@ static void meson_crypto_remove(struct platform_device= *pdev) clk_disable_unprepare(mc->busclk); } =20 +static const struct meson_pdata meson_gxl_pdata =3D { + .descs_reg =3D 0x0, + .status_reg =3D 0x4, +}; + static const struct of_device_id meson_crypto_of_match_table[] =3D { - { .compatible =3D "amlogic,gxl-crypto", }, - {} + { + .compatible =3D "amlogic,gxl-crypto", + .data =3D &meson_gxl_pdata, + }, + {}, }; MODULE_DEVICE_TABLE(of, meson_crypto_of_match_table); =20 diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index 9f1ef87333ae..e0bc5c39bf2c 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -78,6 +78,16 @@ struct meson_flow { #endif }; =20 +/* + * struct meson_pdata - SoC series dependent data. + * @reg_descs: offset to descriptors register + * @reg_status: offset to status register + */ +struct meson_pdata { + u32 descs_reg; + u32 status_reg; +}; + /* * struct meson_dev - main container for all this driver information * @base: base address of amlogic-crypto @@ -93,6 +103,7 @@ struct meson_dev { void __iomem *base; struct clk *busclk; struct device *dev; + const struct meson_pdata *pdata; struct meson_flow *chanlist; atomic_t flow; int flow_cnt; --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6F5F1E2837; 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charset="utf-8" Amlogic crypto IP, which uses DMA crypto engine, doesn't take a clock input. Fixes: 48fe583fe541 ("crypto: amlogic - Add crypto accelerator for amlogic = GXL") Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-core.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index d7e455f73c04..90b539401b71 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -9,7 +9,6 @@ =20 #include #include -#include #include #include #include @@ -267,19 +266,6 @@ static int meson_crypto_probe(struct platform_device *= pdev) if (IS_ERR(mc->base)) return PTR_ERR(mc->base); =20 - mc->busclk =3D devm_clk_get(&pdev->dev, "blkmv"); - if (IS_ERR(mc->busclk)) { - err =3D PTR_ERR(mc->busclk); - dev_err(&pdev->dev, "Cannot get core clock err=3D%d\n", err); - return err; - } - - err =3D clk_prepare_enable(mc->busclk); - if (err !=3D 0) { - dev_err(&pdev->dev, "Cannot prepare_enable busclk\n"); - return err; - } - err =3D meson_allocate_chanlist(mc); if (err) goto error_flow; @@ -304,7 +290,6 @@ static int meson_crypto_probe(struct platform_device *p= dev) meson_unregister_algs(mc); error_flow: meson_free_chanlist(mc, mc->flow_cnt - 1); - clk_disable_unprepare(mc->busclk); return err; } =20 @@ -319,8 +304,6 @@ static void meson_crypto_remove(struct platform_device = *pdev) meson_unregister_algs(mc); =20 meson_free_chanlist(mc, mc->flow_cnt - 1); - - clk_disable_unprepare(mc->busclk); } =20 static const struct meson_pdata meson_gxl_pdata =3D { --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 491F61E2833; Fri, 8 Nov 2024 10:29:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.89.224.132 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731061779; 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Fri, 8 Nov 2024 13:29:33 +0300 (MSK) From: Alexey Romanov To: , , , , , , , , , , , CC: , , , , , , "Alexey Romanov" Subject: [PATCH v10 04/22] crypto: amlogic - Add MMIO helpers Date: Fri, 8 Nov 2024 13:28:49 +0300 Message-ID: <20241108102907.1788584-5-avromanov@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108102907.1788584-1-avromanov@salutedevices.com> References: <20241108102907.1788584-1-avromanov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189039 [Nov 08 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: avromanov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;smtp.sberdevices.ru:7.1.1,5.0.1;127.0.0.199:7.1.2, FromAlignment: s X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/08 08:34:00 #26834472 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" Add MMIO access helpers: meson_dma_start() and meson_dma_ready(). Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 2 +- drivers/crypto/amlogic/amlogic-gxl-core.c | 24 ++++++++++++++++----- drivers/crypto/amlogic/amlogic-gxl.h | 2 ++ 3 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index 7eff3ae7356f..1fe916b0a138 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -225,7 +225,7 @@ static int meson_cipher(struct skcipher_request *areq) =20 reinit_completion(&mc->chanlist[flow].complete); mc->chanlist[flow].status =3D 0; - writel(mc->chanlist[flow].t_phy | 2, mc->base + ((mc->pdata->descs_reg + = flow) << 2)); + meson_dma_start(mc, flow); wait_for_completion_interruptible_timeout(&mc->chanlist[flow].complete, msecs_to_jiffies(500)); if (mc->chanlist[flow].status =3D=3D 0) { diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 90b539401b71..e617dddf5e2b 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -22,18 +22,32 @@ =20 #include "amlogic-gxl.h" =20 +void meson_dma_start(struct meson_dev *mc, int flow) +{ + u32 offset =3D (mc->pdata->descs_reg + flow) << 2; + + writel(mc->chanlist[flow].t_phy | 2, mc->base + offset); +} + +static bool meson_dma_ready(struct meson_dev *mc, int flow) +{ + u32 offset =3D (mc->pdata->status_reg + flow) << 2; + u32 data =3D readl(mc->base + offset); + + if (data) + writel_relaxed(0xF, mc->base + offset); + + return data; +} + static irqreturn_t meson_irq_handler(int irq, void *data) { struct meson_dev *mc =3D (struct meson_dev *)data; int flow; - u32 p; =20 for (flow =3D 0; flow < mc->flow_cnt; flow++) { if (mc->chanlist[flow].irq =3D=3D irq) { - p =3D readl(mc->base + ((mc->pdata->status_reg + flow) << 2)); - if (p) { - writel_relaxed(0xF, mc->base + - ((mc->pdata->status_reg + flow) << 2)); + if (meson_dma_ready(mc, flow)) { mc->chanlist[flow].status =3D 1; complete(&mc->chanlist[flow].complete); return IRQ_HANDLED; diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index e0bc5c39bf2c..0ccf6542995f 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -161,6 +161,8 @@ struct meson_alg_template { #endif }; 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charset="utf-8" Move get_engine_number() function from cipher.c to core.c Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 9 ++------- drivers/crypto/amlogic/amlogic-gxl-core.c | 5 +++++ drivers/crypto/amlogic/amlogic-gxl.h | 2 ++ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index 1fe916b0a138..18e9e2d39b1f 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -17,11 +17,6 @@ #include #include "amlogic-gxl.h" =20 -static int get_engine_number(struct meson_dev *mc) -{ - return atomic_inc_return(&mc->flow) % mc->flow_cnt; -} - static bool meson_cipher_need_fallback(struct skcipher_request *areq) { struct scatterlist *src_sg =3D areq->src; @@ -282,7 +277,7 @@ int meson_skdecrypt(struct skcipher_request *areq) rctx->op_dir =3D MESON_DECRYPT; if (meson_cipher_need_fallback(areq)) return meson_cipher_do_fallback(areq); - e =3D get_engine_number(op->mc); + e =3D meson_get_engine_number(op->mc); engine =3D op->mc->chanlist[e].engine; rctx->flow =3D e; =20 @@ -300,7 +295,7 @@ int meson_skencrypt(struct skcipher_request *areq) rctx->op_dir =3D MESON_ENCRYPT; if (meson_cipher_need_fallback(areq)) return meson_cipher_do_fallback(areq); - e =3D get_engine_number(op->mc); + e =3D meson_get_engine_number(op->mc); engine =3D op->mc->chanlist[e].engine; rctx->flow =3D e; =20 diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index e617dddf5e2b..44e71e917e5e 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -22,6 +22,11 @@ =20 #include "amlogic-gxl.h" =20 +int meson_get_engine_number(struct meson_dev *mc) +{ + return atomic_inc_return(&mc->flow) % mc->flow_cnt; +} + void meson_dma_start(struct meson_dev *mc, int flow) { u32 offset =3D (mc->pdata->descs_reg + flow) << 2; diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index 0ccf6542995f..cb70277c3a31 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -161,6 +161,8 @@ struct meson_alg_template { #endif }; =20 +int meson_get_engine_number(struct meson_dev *mc); + void meson_dma_start(struct meson_dev *mc, int flow); =20 int meson_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42FFA1E411D; Fri, 8 Nov 2024 10:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.89.224.132 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731061781; cv=none; b=O9iOqvM78N4DFSNyIFZBxEEdJA/uVD2MvH4c2vOwAXmUnorAb4p+Rb7ybO9hngSjV55neXYPFnaLdUYr2tmtlEgsJlCJg29JlqnVN0AfAhYRiq6hf8DYdRsLKbthpZl9MoYhaUr4cHgKQIE0HjobF3P3nb3q/hg2rUP+77iGTa4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731061781; c=relaxed/simple; bh=yGAsqIt3+hE4ufw4XgUXmn0redvklmExhdj/fGOyTEo=; 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charset="utf-8" This field is used only to check for timeout. But there is more convenient way to achive the same goal. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 13 +++++++++---- drivers/crypto/amlogic/amlogic-gxl-core.c | 1 - drivers/crypto/amlogic/amlogic-gxl.h | 2 -- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index 18e9e2d39b1f..dc0b100c5de2 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -219,13 +219,18 @@ static int meson_cipher(struct skcipher_request *areq) } =20 reinit_completion(&mc->chanlist[flow].complete); - mc->chanlist[flow].status =3D 0; meson_dma_start(mc, flow); - wait_for_completion_interruptible_timeout(&mc->chanlist[flow].complete, - msecs_to_jiffies(500)); - if (mc->chanlist[flow].status =3D=3D 0) { + + err =3D wait_for_completion_interruptible_timeout(&mc->chanlist[flow].com= plete, + msecs_to_jiffies(500)); + if (err =3D=3D 0) { dev_err(mc->dev, "DMA timeout for flow %d\n", flow); err =3D -EINVAL; + } else if (err < 0) { + dev_err(mc->dev, "Waiting for DMA completion is failed (%d)\n", err); + } else { + /* No error */ + err =3D 0; } =20 dma_unmap_single(mc->dev, phykeyiv, keyivlen, DMA_TO_DEVICE); diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 44e71e917e5e..9259ad0417d1 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -53,7 +53,6 @@ static irqreturn_t meson_irq_handler(int irq, void *data) for (flow =3D 0; flow < mc->flow_cnt; flow++) { if (mc->chanlist[flow].irq =3D=3D irq) { if (meson_dma_ready(mc, flow)) { - mc->chanlist[flow].status =3D 1; complete(&mc->chanlist[flow].complete); return IRQ_HANDLED; } diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index cb70277c3a31..0dde7662ae37 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -59,7 +59,6 @@ struct meson_desc { * @engine: ptr to the crypto_engine for this flow * @keylen: keylen for this flow operation * @complete: completion for the current task on this flow - * @status: set to 1 by interrupt if task is done * @irq: IRQ number for amlogic-crypto * @t_phy: Physical address of task * @tl: pointer to the current ce_task for this flow @@ -68,7 +67,6 @@ struct meson_desc { struct meson_flow { struct crypto_engine *engine; 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charset="utf-8" Because that is proper place for them. In particular, it takes less of exported symbol between compiling entities. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 98 +++++++++++++++-- drivers/crypto/amlogic/amlogic-gxl-core.c | 110 ++++---------------- drivers/crypto/amlogic/amlogic-gxl.h | 14 +-- 3 files changed, 119 insertions(+), 103 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index dc0b100c5de2..bc3092a8a2c2 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -271,7 +271,7 @@ int meson_handle_cipher_request(struct crypto_engine *e= ngine, void *areq) return 0; } =20 -int meson_skdecrypt(struct skcipher_request *areq) +static int meson_skdecrypt(struct skcipher_request *areq) { struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); @@ -289,7 +289,7 @@ int meson_skdecrypt(struct skcipher_request *areq) return crypto_transfer_skcipher_request_to_engine(engine, areq); } =20 -int meson_skencrypt(struct skcipher_request *areq) +static int meson_skencrypt(struct skcipher_request *areq) { struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); @@ -307,7 +307,7 @@ int meson_skencrypt(struct skcipher_request *areq) return crypto_transfer_skcipher_request_to_engine(engine, areq); } =20 -int meson_cipher_init(struct crypto_tfm *tfm) +static int meson_cipher_init(struct crypto_tfm *tfm) { struct meson_cipher_tfm_ctx *op =3D crypto_tfm_ctx(tfm); struct meson_alg_template *algt; @@ -333,7 +333,7 @@ int meson_cipher_init(struct crypto_tfm *tfm) return 0; } =20 -void meson_cipher_exit(struct crypto_tfm *tfm) +static void meson_cipher_exit(struct crypto_tfm *tfm) { struct meson_cipher_tfm_ctx *op =3D crypto_tfm_ctx(tfm); =20 @@ -341,8 +341,8 @@ void meson_cipher_exit(struct crypto_tfm *tfm) crypto_free_skcipher(op->fallback_tfm); } =20 -int meson_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, - unsigned int keylen) +static int meson_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, + unsigned int keylen) { struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); struct meson_dev *mc =3D op->mc; @@ -369,3 +369,89 @@ int meson_aes_setkey(struct crypto_skcipher *tfm, cons= t u8 *key, =20 return crypto_skcipher_setkey(op->fallback_tfm, key, keylen); } + +static struct meson_alg_template algs[] =3D { +{ + .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .blockmode =3D MESON_OPMODE_CBC, + .alg.skcipher.base =3D { + .base =3D { + .cra_name =3D "cbc(aes)", + .cra_driver_name =3D "cbc-aes-gxl", + .cra_priority =3D 400, + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx), + .cra_module =3D THIS_MODULE, + .cra_alignmask =3D 0xf, + .cra_init =3D meson_cipher_init, + .cra_exit =3D meson_cipher_exit, + }, + .min_keysize =3D AES_MIN_KEY_SIZE, + .max_keysize =3D AES_MAX_KEY_SIZE, + .ivsize =3D AES_BLOCK_SIZE, + .setkey =3D meson_aes_setkey, + .encrypt =3D meson_skencrypt, + .decrypt =3D meson_skdecrypt, + }, + .alg.skcipher.op =3D { + .do_one_request =3D meson_handle_cipher_request, + }, +}, +{ + .type =3D CRYPTO_ALG_TYPE_SKCIPHER, + .blockmode =3D MESON_OPMODE_ECB, + .alg.skcipher.base =3D { + .base =3D { + .cra_name =3D "ecb(aes)", + .cra_driver_name =3D "ecb-aes-gxl", + .cra_priority =3D 400, + .cra_blocksize =3D AES_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | + CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_ALG_NEED_FALLBACK, + .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx), + .cra_module =3D THIS_MODULE, + .cra_alignmask =3D 0xf, + .cra_init =3D meson_cipher_init, + .cra_exit =3D meson_cipher_exit, + }, + .min_keysize =3D AES_MIN_KEY_SIZE, + .max_keysize =3D AES_MAX_KEY_SIZE, + .setkey =3D meson_aes_setkey, + .encrypt =3D meson_skencrypt, + .decrypt =3D meson_skdecrypt, + }, + .alg.skcipher.op =3D { + .do_one_request =3D meson_handle_cipher_request, + }, +}, +}; + +int meson_cipher_register(struct meson_dev *mc) +{ + return meson_register_algs(mc, algs, ARRAY_SIZE(algs)); +} + +void meson_cipher_unregister(struct meson_dev *mc) +{ + meson_unregister_algs(mc, algs, ARRAY_SIZE(algs)); +} + +void meson_cipher_debugfs_show(struct seq_file *seq, void *v) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(algs); i++) { + seq_printf(seq, "%s %s %lu %lu\n", + algs[i].alg.skcipher.base.base.cra_driver_name, + algs[i].alg.skcipher.base.base.cra_name, +#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG + algs[i].stat_req, algs[i].stat_fb); +#else + 0ul, 0ul); +#endif + } +} diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 9259ad0417d1..106d4ee2e5e9 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -64,66 +64,6 @@ static irqreturn_t meson_irq_handler(int irq, void *data) return IRQ_HANDLED; } =20 -static struct meson_alg_template mc_algs[] =3D { -{ - .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .blockmode =3D MESON_OPMODE_CBC, - .alg.skcipher.base =3D { - .base =3D { - .cra_name =3D "cbc(aes)", - .cra_driver_name =3D "cbc-aes-gxl", - .cra_priority =3D 400, - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | - CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_ALG_NEED_FALLBACK, - .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx), - .cra_module =3D THIS_MODULE, - .cra_alignmask =3D 0xf, - .cra_init =3D meson_cipher_init, - .cra_exit =3D meson_cipher_exit, - }, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .ivsize =3D AES_BLOCK_SIZE, - .setkey =3D meson_aes_setkey, - .encrypt =3D meson_skencrypt, - .decrypt =3D meson_skdecrypt, - }, - .alg.skcipher.op =3D { - .do_one_request =3D meson_handle_cipher_request, - }, -}, -{ - .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .blockmode =3D MESON_OPMODE_ECB, - .alg.skcipher.base =3D { - .base =3D { - .cra_name =3D "ecb(aes)", - .cra_driver_name =3D "ecb-aes-gxl", - .cra_priority =3D 400, - .cra_blocksize =3D AES_BLOCK_SIZE, - .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | - CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | - CRYPTO_ALG_NEED_FALLBACK, - .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx), - .cra_module =3D THIS_MODULE, - .cra_alignmask =3D 0xf, - .cra_init =3D meson_cipher_init, - .cra_exit =3D meson_cipher_exit, - }, - .min_keysize =3D AES_MIN_KEY_SIZE, - .max_keysize =3D AES_MAX_KEY_SIZE, - .setkey =3D meson_aes_setkey, - .encrypt =3D meson_skencrypt, - .decrypt =3D meson_skdecrypt, - }, - .alg.skcipher.op =3D { - .do_one_request =3D meson_handle_cipher_request, - }, -}, -}; - static int meson_debugfs_show(struct seq_file *seq, void *v) { struct meson_dev *mc __maybe_unused =3D seq->private; @@ -137,20 +77,8 @@ static int meson_debugfs_show(struct seq_file *seq, voi= d *v) 0ul); #endif =20 - for (i =3D 0; i < ARRAY_SIZE(mc_algs); i++) { - switch (mc_algs[i].type) { - case CRYPTO_ALG_TYPE_SKCIPHER: - seq_printf(seq, "%s %s %lu %lu\n", - mc_algs[i].alg.skcipher.base.base.cra_driver_name, - mc_algs[i].alg.skcipher.base.base.cra_name, -#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG - mc_algs[i].stat_req, mc_algs[i].stat_fb); -#else - 0ul, 0ul); -#endif - break; - } - } + meson_cipher_debugfs_show(seq, v); + return 0; } DEFINE_SHOW_ATTRIBUTE(meson_debugfs); @@ -227,19 +155,20 @@ static int meson_allocate_chanlist(struct meson_dev *= mc) return err; } =20 -static int meson_register_algs(struct meson_dev *mc) +int meson_register_algs(struct meson_dev *mc, struct meson_alg_template *a= lgs, + unsigned int count) { int err, i; =20 - for (i =3D 0; i < ARRAY_SIZE(mc_algs); i++) { - mc_algs[i].mc =3D mc; - switch (mc_algs[i].type) { + for (i =3D 0; i < count; i++) { + algs[i].mc =3D mc; + switch (algs[i].type) { case CRYPTO_ALG_TYPE_SKCIPHER: - err =3D crypto_engine_register_skcipher(&mc_algs[i].alg.skcipher); + err =3D crypto_engine_register_skcipher(&algs[i].alg.skcipher); if (err) { dev_err(mc->dev, "Fail to register %s\n", - mc_algs[i].alg.skcipher.base.base.cra_name); - mc_algs[i].mc =3D NULL; + algs[i].alg.skcipher.base.base.cra_name); + meson_unregister_algs(mc, algs, count); return err; } break; @@ -249,16 +178,17 @@ static int meson_register_algs(struct meson_dev *mc) return 0; } =20 -static void meson_unregister_algs(struct meson_dev *mc) +void meson_unregister_algs(struct meson_dev *mc, struct meson_alg_template= *algs, + unsigned int count) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(mc_algs); i++) { - if (!mc_algs[i].mc) + for (i =3D 0; i < count; i++) { + if (!algs[i].mc) continue; - switch (mc_algs[i].type) { + switch (algs[i].type) { case CRYPTO_ALG_TYPE_SKCIPHER: - crypto_engine_unregister_skcipher(&mc_algs[i].alg.skcipher); + crypto_engine_unregister_skcipher(&algs[i].alg.skcipher); break; } } @@ -288,9 +218,9 @@ static int meson_crypto_probe(struct platform_device *p= dev) if (err) goto error_flow; =20 - err =3D meson_register_algs(mc); + err =3D meson_cipher_register(mc); if (err) - goto error_alg; + goto error_flow; =20 if (IS_ENABLED(CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG)) { struct dentry *dbgfs_dir; @@ -304,8 +234,6 @@ static int meson_crypto_probe(struct platform_device *p= dev) } =20 return 0; -error_alg: - meson_unregister_algs(mc); error_flow: meson_free_chanlist(mc, mc->flow_cnt - 1); return err; @@ -319,7 +247,7 @@ static void meson_crypto_remove(struct platform_device = *pdev) debugfs_remove_recursive(mc->dbgfs_dir); #endif =20 - meson_unregister_algs(mc); + meson_cipher_unregister(mc); =20 meson_free_chanlist(mc, mc->flow_cnt - 1); } diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index 0dde7662ae37..f0ccd28545aa 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -163,10 +163,12 @@ int meson_get_engine_number(struct meson_dev *mc); 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Fri, 8 Nov 2024 13:29:41 +0300 (MSK) From: Alexey Romanov To: , , , , , , , , , , , CC: , , , , , , "Alexey Romanov" Subject: [PATCH v10 08/22] crypto: amlogic - Cleanup defines Date: Fri, 8 Nov 2024 13:28:53 +0300 Message-ID: <20241108102907.1788584-9-avromanov@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108102907.1788584-1-avromanov@salutedevices.com> References: <20241108102907.1788584-1-avromanov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189039 [Nov 08 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: avromanov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_from_domain_doesnt_match_to}, smtp.sberdevices.ru:5.0.1,7.1.1;127.0.0.199:7.1.2;salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1, FromAlignment: s X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/08 08:34:00 #26834472 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" It is bad to use hardcoded values directly in the code. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 24 ++++++++++----------- drivers/crypto/amlogic/amlogic-gxl.h | 16 ++++++++------ 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index bc3092a8a2c2..c662c4b86e97 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -141,8 +141,8 @@ static int meson_cipher(struct skcipher_request *areq) ivsize, 0); } } - if (keyivlen =3D=3D 24) - keyivlen =3D 32; + if (keyivlen =3D=3D AES_KEYSIZE_192) + keyivlen =3D AES_MAX_KEY_SIZE; =20 phykeyiv =3D dma_map_single(mc->dev, bkeyiv, keyivlen, DMA_TO_DEVICE); @@ -161,7 +161,7 @@ static int meson_cipher(struct skcipher_request *areq) todo =3D min(keyivlen - eat, 16u); desc->t_src =3D cpu_to_le32(phykeyiv + i * 16); desc->t_dst =3D cpu_to_le32(i * 16); - v =3D (MODE_KEY << 20) | DESC_OWN | 16; + v =3D DESC_MODE_KEY | DESC_OWN | 16; desc->t_status =3D cpu_to_le32(v); =20 eat +=3D todo; @@ -205,7 +205,7 @@ static int meson_cipher(struct skcipher_request *areq) desc->t_src =3D cpu_to_le32(sg_dma_address(src_sg)); desc->t_dst =3D cpu_to_le32(sg_dma_address(dst_sg)); todo =3D min(len, sg_dma_len(src_sg)); - v =3D (op->keymode << 20) | DESC_OWN | todo | (algt->blockmode << 26); + v =3D op->keymode | DESC_OWN | todo | algt->blockmode; if (rctx->op_dir) v |=3D DESC_ENCRYPTION; len -=3D todo; @@ -348,14 +348,14 @@ static int meson_aes_setkey(struct crypto_skcipher *t= fm, const u8 *key, struct meson_dev *mc =3D op->mc; =20 switch (keylen) { - case 128 / 8: - op->keymode =3D MODE_AES_128; + case AES_KEYSIZE_128: + op->keymode =3D DESC_MODE_AES_128; break; - case 192 / 8: - op->keymode =3D MODE_AES_192; + case AES_KEYSIZE_192: + op->keymode =3D DESC_MODE_AES_192; break; - case 256 / 8: - op->keymode =3D MODE_AES_256; + case AES_KEYSIZE_256: + op->keymode =3D DESC_MODE_AES_256; break; default: dev_dbg(mc->dev, "ERROR: Invalid keylen %u\n", keylen); @@ -373,7 +373,7 @@ static int meson_aes_setkey(struct crypto_skcipher *tfm= , const u8 *key, static struct meson_alg_template algs[] =3D { { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .blockmode =3D MESON_OPMODE_CBC, + .blockmode =3D DESC_OPMODE_CBC, .alg.skcipher.base =3D { .base =3D { .cra_name =3D "cbc(aes)", @@ -402,7 +402,7 @@ static struct meson_alg_template algs[] =3D { }, { .type =3D CRYPTO_ALG_TYPE_SKCIPHER, - .blockmode =3D MESON_OPMODE_ECB, + .blockmode =3D DESC_OPMODE_ECB, .alg.skcipher.base =3D { .base =3D { .cra_name =3D "ecb(aes)", diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index f0ccd28545aa..8f20903842ec 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -11,19 +11,21 @@ #include #include =20 -#define MODE_KEY 1 -#define MODE_AES_128 0x8 -#define MODE_AES_192 0x9 -#define MODE_AES_256 0xa - #define MESON_DECRYPT 0 #define MESON_ENCRYPT 1 =20 -#define MESON_OPMODE_ECB 0 -#define MESON_OPMODE_CBC 1 +#define DESC_MODE_KEY (0x1 << 20) +#define DESC_MODE_AES_128 (0x8 << 20) +#define DESC_MODE_AES_192 (0x9 << 20) +#define DESC_MODE_AES_256 (0xa << 20) =20 #define MAXDESC 64 =20 +#define DESC_OPMODE_ECB (0 << 26) +#define DESC_OPMODE_CBC (1 << 26) + +#define DESC_MAXLEN GENMASK(16, 0) + #define DESC_LAST BIT(18) #define DESC_ENCRYPTION BIT(28) #define DESC_OWN BIT(31) --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43AE31E7C17; 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Fri, 8 Nov 2024 13:29:43 +0300 (MSK) From: Alexey Romanov To: , , , , , , , , , , , CC: , , , , , , "Alexey Romanov" Subject: [PATCH v10 09/22] crypto: amlogic - Process more than MAXDESCS descriptors Date: Fri, 8 Nov 2024 13:28:54 +0300 Message-ID: <20241108102907.1788584-10-avromanov@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108102907.1788584-1-avromanov@salutedevices.com> References: <20241108102907.1788584-1-avromanov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189039 [Nov 08 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: avromanov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;smtp.sberdevices.ru:7.1.1,5.0.1;127.0.0.199:7.1.2, FromAlignment: s X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/08 08:34:00 #26834472 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" 1. The old alhorithm was not designed to process a large amount of memory, and therefore gave incorrect results. 2. Not all Amlogic SoC's use 3 KEY/IV descriptors. Add keyiv descriptors count parameter to platform data. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 448 +++++++++++++------- drivers/crypto/amlogic/amlogic-gxl-core.c | 1 + drivers/crypto/amlogic/amlogic-gxl.h | 2 + 3 files changed, 286 insertions(+), 165 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index c662c4b86e97..0d32d2e3ca3b 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -17,35 +17,41 @@ #include #include "amlogic-gxl.h" =20 -static bool meson_cipher_need_fallback(struct skcipher_request *areq) +static bool meson_cipher_need_fallback_sg(struct skcipher_request *areq, + struct scatterlist *sg) { - struct scatterlist *src_sg =3D areq->src; - struct scatterlist *dst_sg =3D areq->dst; + struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); + unsigned int blocksize =3D crypto_skcipher_blocksize(tfm); + unsigned int cryptlen =3D areq->cryptlen; + + while (cryptlen) { + unsigned int len =3D min(cryptlen, sg->length); + + if (!IS_ALIGNED(sg->offset, sizeof(u32))) + return true; + if (len % blocksize !=3D 0) + return true; + + cryptlen -=3D len; + sg =3D sg_next(sg); + } + + return false; +} =20 +static bool meson_cipher_need_fallback(struct skcipher_request *areq) +{ if (areq->cryptlen =3D=3D 0) return true; =20 - if (sg_nents(src_sg) !=3D sg_nents(dst_sg)) + if (meson_cipher_need_fallback_sg(areq, areq->src)) return true; =20 - /* KEY/IV descriptors use 3 desc */ - if (sg_nents(src_sg) > MAXDESC - 3 || sg_nents(dst_sg) > MAXDESC - 3) - return true; + if (areq->dst =3D=3D areq->src) + return false; =20 - while (src_sg && dst_sg) { - if ((src_sg->length % 16) !=3D 0) - return true; - if ((dst_sg->length % 16) !=3D 0) - return true; - if (src_sg->length !=3D dst_sg->length) - return true; - if (!IS_ALIGNED(src_sg->offset, sizeof(u32))) - return true; - if (!IS_ALIGNED(dst_sg->offset, sizeof(u32))) - return true; - src_sg =3D sg_next(src_sg); - dst_sg =3D sg_next(dst_sg); - } + if (meson_cipher_need_fallback_sg(areq, areq->dst)) + return true; =20 return false; } @@ -76,184 +82,296 @@ static int meson_cipher_do_fallback(struct skcipher_r= equest *areq) return err; } =20 -static int meson_cipher(struct skcipher_request *areq) +struct cipher_ctx { + struct { + dma_addr_t addr; + unsigned int len; + } keyiv; + + struct skcipher_request *areq; + struct scatterlist *src_sg; + struct scatterlist *dst_sg; + void *bkeyiv; + + unsigned int src_offset; + unsigned int dst_offset; + unsigned int cryptlen; + unsigned int tloffset; +}; + +static int meson_map_scatterlist(struct skcipher_request *areq, struct mes= on_dev *mc) { - struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); - struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(areq); - struct meson_dev *mc =3D op->mc; - struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); - struct meson_alg_template *algt; - int flow =3D rctx->flow; - unsigned int todo, eat, len; - struct scatterlist *src_sg =3D areq->src; - struct scatterlist *dst_sg =3D areq->dst; - struct meson_desc *desc; int nr_sgs, nr_sgd; - int i, err =3D 0; - unsigned int keyivlen, ivsize, offset, tloffset; - dma_addr_t phykeyiv; - void *backup_iv =3D NULL, *bkeyiv; - u32 v; - - algt =3D container_of(alg, struct meson_alg_template, alg.skcipher.base); - - dev_dbg(mc->dev, "%s %s %u %x IV(%u) key=3D%u flow=3D%d\n", __func__, - crypto_tfm_alg_name(areq->base.tfm), - areq->cryptlen, - rctx->op_dir, crypto_skcipher_ivsize(tfm), - op->keylen, flow); - -#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG - algt->stat_req++; - mc->chanlist[flow].stat_req++; -#endif - - /* - * The hardware expect a list of meson_desc structures. - * The 2 first structures store key - * The third stores IV - */ - bkeyiv =3D kzalloc(48, GFP_KERNEL | GFP_DMA); - if (!bkeyiv) - return -ENOMEM; - - memcpy(bkeyiv, op->key, op->keylen); - keyivlen =3D op->keylen; - - ivsize =3D crypto_skcipher_ivsize(tfm); - if (areq->iv && ivsize > 0) { - if (ivsize > areq->cryptlen) { - dev_err(mc->dev, "invalid ivsize=3D%d vs len=3D%d\n", ivsize, areq->cry= ptlen); - err =3D -EINVAL; - goto theend; - } - memcpy(bkeyiv + 32, areq->iv, ivsize); - keyivlen =3D 48; - if (rctx->op_dir =3D=3D MESON_DECRYPT) { - backup_iv =3D kzalloc(ivsize, GFP_KERNEL); - if (!backup_iv) { - err =3D -ENOMEM; - goto theend; - } - offset =3D areq->cryptlen - ivsize; - scatterwalk_map_and_copy(backup_iv, areq->src, offset, - ivsize, 0); - } - } - if (keyivlen =3D=3D AES_KEYSIZE_192) - keyivlen =3D AES_MAX_KEY_SIZE; - - phykeyiv =3D dma_map_single(mc->dev, bkeyiv, keyivlen, - DMA_TO_DEVICE); - err =3D dma_mapping_error(mc->dev, phykeyiv); - if (err) { - dev_err(mc->dev, "Cannot DMA MAP KEY IV\n"); - goto theend; - } - - tloffset =3D 0; - eat =3D 0; - i =3D 0; - while (keyivlen > eat) { - desc =3D &mc->chanlist[flow].tl[tloffset]; - memset(desc, 0, sizeof(struct meson_desc)); - todo =3D min(keyivlen - eat, 16u); - desc->t_src =3D cpu_to_le32(phykeyiv + i * 16); - desc->t_dst =3D cpu_to_le32(i * 16); - v =3D DESC_MODE_KEY | DESC_OWN | 16; - desc->t_status =3D cpu_to_le32(v); - - eat +=3D todo; - i++; - tloffset++; - } =20 if (areq->src =3D=3D areq->dst) { nr_sgs =3D dma_map_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_BIDIRECTIONAL); if (!nr_sgs) { dev_err(mc->dev, "Invalid SG count %d\n", nr_sgs); - err =3D -EINVAL; - goto theend; + return -EINVAL; } - nr_sgd =3D nr_sgs; } else { nr_sgs =3D dma_map_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); - if (!nr_sgs || nr_sgs > MAXDESC - 3) { + if (!nr_sgs) { dev_err(mc->dev, "Invalid SG count %d\n", nr_sgs); - err =3D -EINVAL; - goto theend; + return -EINVAL; } + nr_sgd =3D dma_map_sg(mc->dev, areq->dst, sg_nents(areq->dst), DMA_FROM_DEVICE); - if (!nr_sgd || nr_sgd > MAXDESC - 3) { + if (!nr_sgd) { + dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); dev_err(mc->dev, "Invalid SG count %d\n", nr_sgd); - err =3D -EINVAL; - goto theend; + return -EINVAL; } } =20 - src_sg =3D areq->src; - dst_sg =3D areq->dst; - len =3D areq->cryptlen; - while (src_sg) { - desc =3D &mc->chanlist[flow].tl[tloffset]; - memset(desc, 0, sizeof(struct meson_desc)); - - desc->t_src =3D cpu_to_le32(sg_dma_address(src_sg)); - desc->t_dst =3D cpu_to_le32(sg_dma_address(dst_sg)); - todo =3D min(len, sg_dma_len(src_sg)); - v =3D op->keymode | DESC_OWN | todo | algt->blockmode; - if (rctx->op_dir) - v |=3D DESC_ENCRYPTION; - len -=3D todo; - - if (!sg_next(src_sg)) - v |=3D DESC_LAST; - desc->t_status =3D cpu_to_le32(v); - tloffset++; - src_sg =3D sg_next(src_sg); - dst_sg =3D sg_next(dst_sg); + return 0; +} + +static void meson_unmap_scatterlist(struct skcipher_request *areq, struct = meson_dev *mc) +{ + if (areq->src =3D=3D areq->dst) { + dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_BIDIRECTIONAL); + } else { + dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); + dma_unmap_sg(mc->dev, areq->dst, sg_nents(areq->dst), DMA_FROM_DEVICE); } +} =20 - reinit_completion(&mc->chanlist[flow].complete); - meson_dma_start(mc, flow); +static void meson_setup_keyiv_descs(struct cipher_ctx *ctx) +{ + struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(ctx->areq); + struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(ctx->areq); + struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); + struct meson_alg_template *algt =3D container_of(alg, + struct meson_alg_template, alg.skcipher.base); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_dev *mc =3D op->mc; + unsigned int ivsize =3D crypto_skcipher_ivsize(tfm); + unsigned int blockmode =3D algt->blockmode; + int i; + + if (ctx->tloffset) + return; + + if (blockmode =3D=3D DESC_OPMODE_CBC) { + memcpy(ctx->bkeyiv + AES_MAX_KEY_SIZE, ctx->areq->iv, ivsize); + dma_sync_single_for_device(mc->dev, ctx->keyiv.addr, + ctx->keyiv.len, DMA_TO_DEVICE); + } + + for (i =3D 0; i < mc->pdata->setup_desc_cnt; i++) { + struct meson_desc *desc =3D + &mc->chanlist[rctx->flow].tl[ctx->tloffset]; + int offset =3D i * 16; + + desc->t_src =3D cpu_to_le32(ctx->keyiv.addr + offset); + desc->t_dst =3D cpu_to_le32(offset); + desc->t_status =3D cpu_to_le32(DESC_OWN | DESC_MODE_KEY | ctx->keyiv.len= ); + + ctx->tloffset++; + } +} =20 - err =3D wait_for_completion_interruptible_timeout(&mc->chanlist[flow].com= plete, +static bool meson_setup_data_descs(struct cipher_ctx *ctx) +{ + struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(ctx->areq); + struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(ctx->areq); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); + struct meson_alg_template *algt =3D container_of(alg, + struct meson_alg_template, + alg.skcipher.base); + struct meson_dev *mc =3D op->mc; + struct meson_desc *desc =3D &mc->chanlist[rctx->flow].tl[ctx->tloffset]; + unsigned int blocksize =3D crypto_skcipher_blocksize(tfm); + unsigned int blockmode =3D algt->blockmode; + unsigned int maxlen =3D rounddown(DESC_MAXLEN, blocksize); + unsigned int todo; + u32 v; + + ctx->tloffset++; + + todo =3D min(ctx->cryptlen, maxlen); + todo =3D min(todo, ctx->cryptlen); + todo =3D min(todo, sg_dma_len(ctx->src_sg) - ctx->src_offset); + todo =3D min(todo, sg_dma_len(ctx->dst_sg) - ctx->dst_offset); + + desc->t_src =3D cpu_to_le32(sg_dma_address(ctx->src_sg) + ctx->src_offset= ); + desc->t_dst =3D cpu_to_le32(sg_dma_address(ctx->dst_sg) + ctx->dst_offset= ); + + ctx->cryptlen -=3D todo; + ctx->src_offset +=3D todo; + ctx->dst_offset +=3D todo; + + v =3D DESC_OWN | blockmode | op->keymode | todo; + if (rctx->op_dir =3D=3D MESON_ENCRYPT) + v |=3D DESC_ENCRYPTION; + + if (!ctx->cryptlen || ctx->tloffset =3D=3D MAXDESC) + v |=3D DESC_LAST; + + desc->t_status =3D cpu_to_le32(v); + + return v & DESC_LAST; +} + +static int meson_kick_hardware(struct cipher_ctx *ctx) +{ + struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(ctx->areq); + struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(ctx->areq); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); + struct meson_alg_template *algt =3D container_of(alg, + struct meson_alg_template, + alg.skcipher.base); + struct meson_dev *mc =3D op->mc; + unsigned int ivsize =3D crypto_skcipher_ivsize(tfm); + unsigned int blockmode =3D algt->blockmode; + enum dma_data_direction new_iv_dir; + struct scatterlist *sg_head; + dma_addr_t new_iv_phys; + void *new_iv; + int err; + + if (blockmode =3D=3D DESC_OPMODE_CBC) { + struct scatterlist *sg_current; + unsigned int offset; + + if (rctx->op_dir =3D=3D MESON_ENCRYPT) { + sg_current =3D ctx->dst_sg; + sg_head =3D ctx->areq->dst; + offset =3D ctx->dst_offset; + new_iv_dir =3D DMA_FROM_DEVICE; + } else { + sg_current =3D ctx->src_sg; + sg_head =3D ctx->areq->src; + offset =3D ctx->src_offset; + new_iv_dir =3D DMA_TO_DEVICE; + } + + if (ctx->areq->src =3D=3D ctx->areq->dst) + new_iv_dir =3D DMA_BIDIRECTIONAL; + + offset -=3D ivsize; + new_iv =3D sg_virt(sg_current) + offset; + new_iv_phys =3D sg_dma_address(sg_current) + offset; + } + + if (blockmode =3D=3D DESC_OPMODE_CBC && + rctx->op_dir =3D=3D MESON_DECRYPT) { + dma_sync_sg_for_cpu(mc->dev, sg_head, + sg_nents(sg_head), new_iv_dir); + memcpy(ctx->areq->iv, new_iv, ivsize); + } + + reinit_completion(&mc->chanlist[rctx->flow].complete); + meson_dma_start(mc, rctx->flow); + err =3D wait_for_completion_interruptible_timeout(&mc->chanlist[rctx->flo= w].complete, msecs_to_jiffies(500)); if (err =3D=3D 0) { - dev_err(mc->dev, "DMA timeout for flow %d\n", flow); - err =3D -EINVAL; + dev_err(mc->dev, "DMA timeout for flow %d\n", rctx->flow); + return -EINVAL; } else if (err < 0) { dev_err(mc->dev, "Waiting for DMA completion is failed (%d)\n", err); - } else { - /* No error */ - err =3D 0; + return err; } =20 - dma_unmap_single(mc->dev, phykeyiv, keyivlen, DMA_TO_DEVICE); + if (blockmode =3D=3D DESC_OPMODE_CBC && + rctx->op_dir =3D=3D MESON_ENCRYPT) { + dma_sync_sg_for_cpu(mc->dev, sg_head, + sg_nents(sg_head), new_iv_dir); + memcpy(ctx->areq->iv, new_iv, ivsize); + } =20 - if (areq->src =3D=3D areq->dst) { - dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_BIDIRECTIONAL); - } else { - dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); - dma_unmap_sg(mc->dev, areq->dst, sg_nents(areq->dst), DMA_FROM_DEVICE); + ctx->tloffset =3D 0; + + return 0; +} + +static int meson_cipher(struct skcipher_request *areq) +{ + struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(areq); + struct meson_dev *mc =3D op->mc; + struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); + struct meson_alg_template *algt; + struct cipher_ctx ctx =3D { + .areq =3D areq, + .src_offset =3D 0, + .dst_offset =3D 0, + .src_sg =3D areq->src, + .dst_sg =3D areq->dst, + .cryptlen =3D areq->cryptlen, + }; + int err; + + dev_dbg(mc->dev, "%s %s %u %x IV(%u) key=3D%u ctx.flow=3D%d\n", __func__, + crypto_tfm_alg_name(areq->base.tfm), + areq->cryptlen, + rctx->op_dir, crypto_skcipher_ivsize(tfm), + op->keylen, rctx->flow); + + algt =3D container_of(alg, struct meson_alg_template, alg.skcipher.base); + +#ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG + algt->stat_req++; + mc->chanlist[rctx->flow].stat_req++; +#endif + + ctx.bkeyiv =3D kzalloc(48, GFP_KERNEL | GFP_DMA); + if (!ctx.bkeyiv) + return -ENOMEM; + + memcpy(ctx.bkeyiv, op->key, op->keylen); + ctx.keyiv.len =3D op->keylen; + if (ctx.keyiv.len =3D=3D AES_KEYSIZE_192) + ctx.keyiv.len =3D AES_MAX_KEY_SIZE; + + ctx.keyiv.addr =3D dma_map_single(mc->dev, ctx.bkeyiv, ctx.keyiv.len, + DMA_TO_DEVICE); + err =3D dma_mapping_error(mc->dev, ctx.keyiv.addr); + if (err) { + dev_err(mc->dev, "Cannot DMA MAP KEY IV\n"); + goto free_keyiv; } =20 - if (areq->iv && ivsize > 0) { - if (rctx->op_dir =3D=3D MESON_DECRYPT) { - memcpy(areq->iv, backup_iv, ivsize); - } else { - scatterwalk_map_and_copy(areq->iv, areq->dst, - areq->cryptlen - ivsize, - ivsize, 0); + err =3D meson_map_scatterlist(areq, mc); + if (err) + goto unmap_keyiv; + + ctx.tloffset =3D 0; + + while (ctx.cryptlen) { + meson_setup_keyiv_descs(&ctx); + + if (meson_setup_data_descs(&ctx)) { + err =3D meson_kick_hardware(&ctx); + if (err) + break; + } + + if (ctx.src_offset =3D=3D sg_dma_len(ctx.src_sg)) { + ctx.src_offset =3D 0; + ctx.src_sg =3D sg_next(ctx.src_sg); + } + + if (ctx.dst_offset =3D=3D sg_dma_len(ctx.dst_sg)) { + ctx.dst_offset =3D 0; + ctx.dst_sg =3D sg_next(ctx.dst_sg); } } -theend: - kfree_sensitive(bkeyiv); - kfree_sensitive(backup_iv); + + meson_unmap_scatterlist(areq, mc); + +unmap_keyiv: + dma_unmap_single(mc->dev, ctx.keyiv.addr, ctx.keyiv.len, DMA_TO_DEVICE); + +free_keyiv: + kfree_sensitive(ctx.bkeyiv); =20 return err; } diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 106d4ee2e5e9..c1c445239549 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -255,6 +255,7 @@ static void meson_crypto_remove(struct platform_device = *pdev) static const struct meson_pdata meson_gxl_pdata =3D { .descs_reg =3D 0x0, .status_reg =3D 0x4, + .setup_desc_cnt =3D 3, }; =20 static const struct of_device_id meson_crypto_of_match_table[] =3D { diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index 8f20903842ec..9fbe5ab44877 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -82,10 +82,12 @@ struct meson_flow { * struct meson_pdata - SoC series dependent data. * @reg_descs: offset to descriptors register * @reg_status: offset to status register + * @setup_desc_cnt: number of setup descriptor to configure. */ struct meson_pdata { u32 descs_reg; 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charset="utf-8" It makes no sense to allocate memory via kzalloc, we can use static buffer, speedup data processing and don't think about kfree() calls. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 52 +++++++++------------ drivers/crypto/amlogic/amlogic-gxl.h | 6 +-- 2 files changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index 0d32d2e3ca3b..622e179320ff 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -59,7 +59,7 @@ static bool meson_cipher_need_fallback(struct skcipher_re= quest *areq) static int meson_cipher_do_fallback(struct skcipher_request *areq) { struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(areq); int err; #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG @@ -91,7 +91,6 @@ struct cipher_ctx { struct skcipher_request *areq; struct scatterlist *src_sg; struct scatterlist *dst_sg; - void *bkeyiv; =20 unsigned int src_offset; unsigned int dst_offset; @@ -147,7 +146,7 @@ static void meson_setup_keyiv_descs(struct cipher_ctx *= ctx) struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); struct meson_alg_template *algt =3D container_of(alg, struct meson_alg_template, alg.skcipher.base); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct meson_dev *mc =3D op->mc; unsigned int ivsize =3D crypto_skcipher_ivsize(tfm); unsigned int blockmode =3D algt->blockmode; @@ -157,7 +156,7 @@ static void meson_setup_keyiv_descs(struct cipher_ctx *= ctx) return; =20 if (blockmode =3D=3D DESC_OPMODE_CBC) { - memcpy(ctx->bkeyiv + AES_MAX_KEY_SIZE, ctx->areq->iv, ivsize); + memcpy(op->keyiv + AES_MAX_KEY_SIZE, ctx->areq->iv, ivsize); dma_sync_single_for_device(mc->dev, ctx->keyiv.addr, ctx->keyiv.len, DMA_TO_DEVICE); } @@ -179,7 +178,7 @@ static bool meson_setup_data_descs(struct cipher_ctx *c= tx) { struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(ctx->areq); struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(ctx->areq); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); struct meson_alg_template *algt =3D container_of(alg, struct meson_alg_template, @@ -222,7 +221,7 @@ static int meson_kick_hardware(struct cipher_ctx *ctx) { struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(ctx->areq); struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(ctx->areq); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); struct meson_alg_template *algt =3D container_of(alg, struct meson_alg_template, @@ -294,7 +293,7 @@ static int meson_kick_hardware(struct cipher_ctx *ctx) static int meson_cipher(struct skcipher_request *areq) { struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(areq); struct meson_dev *mc =3D op->mc; struct skcipher_alg *alg =3D crypto_skcipher_alg(tfm); @@ -307,6 +306,7 @@ static int meson_cipher(struct skcipher_request *areq) .dst_sg =3D areq->dst, .cryptlen =3D areq->cryptlen, }; + unsigned int ivsize =3D crypto_skcipher_ivsize(tfm); int err; =20 dev_dbg(mc->dev, "%s %s %u %x IV(%u) key=3D%u ctx.flow=3D%d\n", __func__, @@ -322,21 +322,21 @@ static int meson_cipher(struct skcipher_request *areq) mc->chanlist[rctx->flow].stat_req++; #endif =20 - ctx.bkeyiv =3D kzalloc(48, GFP_KERNEL | GFP_DMA); - if (!ctx.bkeyiv) - return -ENOMEM; - - memcpy(ctx.bkeyiv, op->key, op->keylen); ctx.keyiv.len =3D op->keylen; if (ctx.keyiv.len =3D=3D AES_KEYSIZE_192) ctx.keyiv.len =3D AES_MAX_KEY_SIZE; =20 - ctx.keyiv.addr =3D dma_map_single(mc->dev, ctx.bkeyiv, ctx.keyiv.len, + if (algt->blockmode =3D=3D DESC_OPMODE_CBC) { + memcpy(op->keyiv + AES_MAX_KEY_SIZE, areq->iv, ivsize); + ctx.keyiv.len =3D AES_MAX_KEY_SIZE + ivsize; + } + + ctx.keyiv.addr =3D dma_map_single(mc->dev, op->keyiv, ctx.keyiv.len, DMA_TO_DEVICE); err =3D dma_mapping_error(mc->dev, ctx.keyiv.addr); if (err) { dev_err(mc->dev, "Cannot DMA MAP KEY IV\n"); - goto free_keyiv; + return err; } =20 err =3D meson_map_scatterlist(areq, mc); @@ -370,9 +370,6 @@ static int meson_cipher(struct skcipher_request *areq) unmap_keyiv: dma_unmap_single(mc->dev, ctx.keyiv.addr, ctx.keyiv.len, DMA_TO_DEVICE); =20 -free_keyiv: - kfree_sensitive(ctx.bkeyiv); - return err; } =20 @@ -392,7 +389,7 @@ int meson_handle_cipher_request(struct crypto_engine *e= ngine, void *areq) static int meson_skdecrypt(struct skcipher_request *areq) { struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(areq); struct crypto_engine *engine; int e; @@ -410,7 +407,7 @@ static int meson_skdecrypt(struct skcipher_request *are= q) static int meson_skencrypt(struct skcipher_request *areq) { struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct meson_cipher_req_ctx *rctx =3D skcipher_request_ctx(areq); struct crypto_engine *engine; int e; @@ -427,7 +424,7 @@ static int meson_skencrypt(struct skcipher_request *are= q) =20 static int meson_cipher_init(struct crypto_tfm *tfm) { - struct meson_cipher_tfm_ctx *op =3D crypto_tfm_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_tfm_ctx_dma(tfm); struct meson_alg_template *algt; const char *name =3D crypto_tfm_alg_name(tfm); struct crypto_skcipher *sktfm =3D __crypto_skcipher_cast(tfm); @@ -453,16 +450,15 @@ static int meson_cipher_init(struct crypto_tfm *tfm) =20 static void meson_cipher_exit(struct crypto_tfm *tfm) { - struct meson_cipher_tfm_ctx *op =3D crypto_tfm_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_tfm_ctx_dma(tfm); =20 - kfree_sensitive(op->key); crypto_free_skcipher(op->fallback_tfm); } =20 static int meson_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen) { - struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx(tfm); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); struct meson_dev *mc =3D op->mc; =20 switch (keylen) { @@ -479,11 +475,9 @@ static int meson_aes_setkey(struct crypto_skcipher *tf= m, const u8 *key, dev_dbg(mc->dev, "ERROR: Invalid keylen %u\n", keylen); return -EINVAL; } - kfree_sensitive(op->key); + + memcpy(op->keyiv, key, keylen); op->keylen =3D keylen; - op->key =3D kmemdup(key, keylen, GFP_KERNEL | GFP_DMA); - if (!op->key) - return -ENOMEM; =20 return crypto_skcipher_setkey(op->fallback_tfm, key, keylen); } @@ -501,7 +495,7 @@ static struct meson_alg_template algs[] =3D { .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_ALG_NEED_FALLBACK, - .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx), + .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx) + CRYPTO_DMA_PADDI= NG, .cra_module =3D THIS_MODULE, .cra_alignmask =3D 0xf, .cra_init =3D meson_cipher_init, @@ -530,7 +524,7 @@ static struct meson_alg_template algs[] =3D { .cra_flags =3D CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY | CRYPTO_ALG_NEED_FALLBACK, - .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx), + .cra_ctxsize =3D sizeof(struct meson_cipher_tfm_ctx) + CRYPTO_DMA_PADDI= NG, .cra_module =3D THIS_MODULE, .cra_alignmask =3D 0xf, .cra_init =3D meson_cipher_init, diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index 9fbe5ab44877..e2e843ea6c4c 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -127,15 +127,15 @@ struct meson_cipher_req_ctx { =20 /* * struct meson_cipher_tfm_ctx - context for a skcipher TFM - * @key: pointer to key data + * @keyiv: key data * @keylen: len of the key * @keymode: The keymode(type and size of key) associated with this TFM * @mc: pointer to the private data of driver handling this TFM * @fallback_tfm: pointer to the fallback TFM */ struct meson_cipher_tfm_ctx { - u32 *key; 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charset="utf-8" Introduce support for SHA1/SHA224/SHA256 hash algos. Tested via tcrypt and custom tests. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/Makefile | 2 +- drivers/crypto/amlogic/amlogic-gxl-core.c | 25 +- drivers/crypto/amlogic/amlogic-gxl-hasher.c | 507 ++++++++++++++++++++ drivers/crypto/amlogic/amlogic-gxl.h | 48 ++ 4 files changed, 580 insertions(+), 2 deletions(-) create mode 100644 drivers/crypto/amlogic/amlogic-gxl-hasher.c diff --git a/drivers/crypto/amlogic/Makefile b/drivers/crypto/amlogic/Makef= ile index 39057e62c13e..4b6b388b7880 100644 --- a/drivers/crypto/amlogic/Makefile +++ b/drivers/crypto/amlogic/Makefile @@ -1,2 +1,2 @@ obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) +=3D amlogic-gxl-crypto.o -amlogic-gxl-crypto-y :=3D amlogic-gxl-core.o amlogic-gxl-cipher.o +amlogic-gxl-crypto-y :=3D amlogic-gxl-core.o amlogic-gxl-cipher.o amlogic-= gxl-hasher.o diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index c1c445239549..706db22b9f65 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -19,6 +19,9 @@ #include #include #include +#include +#include +#include =20 #include "amlogic-gxl.h" =20 @@ -172,6 +175,15 @@ int meson_register_algs(struct meson_dev *mc, struct m= eson_alg_template *algs, return err; } break; + case CRYPTO_ALG_TYPE_AHASH: + err =3D crypto_engine_register_ahash(&algs[i].alg.ahash); + if (err) { + dev_err(mc->dev, "Fail to register %s\n", + algs[i].alg.ahash.base.halg.base.cra_name); + meson_unregister_algs(mc, algs, count); + return err; + } + break; } } =20 @@ -190,6 +202,9 @@ void meson_unregister_algs(struct meson_dev *mc, struct= meson_alg_template *algs case CRYPTO_ALG_TYPE_SKCIPHER: crypto_engine_unregister_skcipher(&algs[i].alg.skcipher); break; + case CRYPTO_ALG_TYPE_AHASH: + crypto_engine_unregister_ahash(&algs[i].alg.ahash); + break; } } } @@ -227,13 +242,20 @@ static int meson_crypto_probe(struct platform_device = *pdev) =20 dbgfs_dir =3D debugfs_create_dir("gxl-crypto", NULL); debugfs_create_file("stats", 0444, dbgfs_dir, mc, &meson_debugfs_fops); - #ifdef CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG mc->dbgfs_dir =3D dbgfs_dir; #endif } =20 + err =3D meson_hasher_register(mc); + if (err) + goto error_hasher; + return 0; + +error_hasher: + meson_cipher_unregister(mc); + error_flow: meson_free_chanlist(mc, mc->flow_cnt - 1); return err; @@ -256,6 +278,7 @@ static const struct meson_pdata meson_gxl_pdata =3D { .descs_reg =3D 0x0, .status_reg =3D 0x4, .setup_desc_cnt =3D 3, + .hasher_supported =3D false, }; =20 static const struct of_device_id meson_crypto_of_match_table[] =3D { diff --git a/drivers/crypto/amlogic/amlogic-gxl-hasher.c b/drivers/crypto/a= mlogic/amlogic-gxl-hasher.c new file mode 100644 index 000000000000..ffc1b23438be --- /dev/null +++ b/drivers/crypto/amlogic/amlogic-gxl-hasher.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hardware asynchronous hasher for Amlogic SoC's. + * + * Copyright (c) 2023, SaluteDevices. All Rights Reserved. + * + * Author: Alexey Romanov + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "amlogic-gxl.h" + +static int meson_sha_init(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + + memset(rctx, 0, sizeof(struct meson_hasher_req_ctx)); + + rctx->flow =3D meson_get_engine_number(tctx->mc); + rctx->begin_req =3D true; + + return 0; +} + +static int meson_sha_update(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_engine *engine =3D tctx->mc->chanlist[rctx->flow].engine; + + return crypto_transfer_hash_request_to_engine(engine, req); +} + +static int meson_sha_final(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_engine *engine =3D tctx->mc->chanlist[rctx->flow].engine; + + rctx->final_req =3D true; + + return crypto_transfer_hash_request_to_engine(engine, req); +} + +static int meson_sha_digest(struct ahash_request *req) +{ + struct crypto_wait wait; + int ret; + + crypto_init_wait(&wait); + ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_SLEEP | + CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, &wait); + + meson_sha_init(req); + + ret =3D crypto_wait_req(meson_sha_update(req), &wait); + if (ret) + return ret; + + return crypto_wait_req(meson_sha_final(req), &wait); +} + +static int meson_hasher_req_map(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_dev *mc =3D tctx->mc; + int ret; + + if (!req->nbytes) + return 0; + + ret =3D dma_map_sg(mc->dev, req->src, sg_nents(req->src), DMA_TO_DEVICE); + if (!ret) { + dev_err(mc->dev, "Cannot DMA MAP request data\n"); + return -ENOMEM; + } + + return 0; +} + +static void meson_hasher_req_unmap(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_dev *mc =3D tctx->mc; + + if (!req->nbytes) + return; + + dma_unmap_sg(mc->dev, req->src, sg_nents(req->src), DMA_TO_DEVICE); +} + +struct hasher_ctx { + struct crypto_async_request *areq; + + unsigned int tloffset; + unsigned int nbytes; + unsigned int todo; + + dma_addr_t state_addr; + dma_addr_t src_addr; + unsigned int src_offset; + struct scatterlist *src_sg; +}; + +static bool meson_final(struct hasher_ctx *ctx) +{ + struct ahash_request *req =3D ahash_request_cast(ctx->areq); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + + return !ctx->nbytes && rctx->final_req; +} + +static int meson_fill_partial_buffer(struct hasher_ctx *ctx, unsigned int = len) +{ + struct ahash_request *req =3D ahash_request_cast(ctx->areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + struct meson_dev *mc =3D tctx->mc; + unsigned int blocksize =3D crypto_ahash_blocksize(tfm); + unsigned int copy; + + if (len) { + copy =3D min(blocksize - rctx->partial_size, len); + memcpy(rctx->partial + rctx->partial_size, + sg_virt(ctx->src_sg) + ctx->src_offset, copy); + + rctx->partial_size +=3D copy; + ctx->nbytes -=3D copy; + ctx->src_offset +=3D copy; + } + + if (rctx->partial_size =3D=3D blocksize || meson_final(ctx)) { + rctx->partial_addr =3D dma_map_single(mc->dev, + rctx->partial, + rctx->partial_size, + DMA_TO_DEVICE); + if (dma_mapping_error(mc->dev, rctx->partial_addr)) { + dev_err(mc->dev, "Cannot DMA MAP SHA partial buffer\n"); + return -ENOMEM; + } + + rctx->partial_mapped =3D true; + ctx->todo =3D rctx->partial_size; + ctx->src_addr =3D rctx->partial_addr; + } + + return 0; +} + +static unsigned int meson_setup_data_descs(struct hasher_ctx *ctx) +{ + struct ahash_request *req =3D ahash_request_cast(ctx->areq); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_dev *mc =3D tctx->mc; + struct meson_flow *flow =3D &mc->chanlist[rctx->flow]; + struct hash_alg_common *alg =3D crypto_hash_alg_common(tfm); + struct meson_alg_template *algt =3D container_of(alg, + struct meson_alg_template, alg.ahash.base.halg); + struct meson_desc *desc =3D &flow->tl[ctx->tloffset]; + u32 v; + + ctx->tloffset++; + + v =3D DESC_OWN | DESC_ENCRYPTION | DESC_OPMODE_SHA | + ctx->todo | algt->blockmode; + if (rctx->begin_req) { + rctx->begin_req =3D false; + v |=3D DESC_BEGIN; + } + + if (!ctx->nbytes && rctx->final_req) { + rctx->final_req =3D false; + v |=3D DESC_END; + } + + if (!ctx->nbytes || ctx->tloffset =3D=3D MAXDESC || rctx->partial_mapped) + v |=3D DESC_LAST; + + desc->t_src =3D cpu_to_le32(ctx->src_addr); + desc->t_dst =3D cpu_to_le32(ctx->state_addr); + desc->t_status =3D cpu_to_le32(v); + + return v & DESC_LAST; +} + +static int meson_kick_hardware(struct hasher_ctx *ctx) +{ + struct ahash_request *req =3D ahash_request_cast(ctx->areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_dev *mc =3D tctx->mc; + struct meson_flow *flow =3D &mc->chanlist[rctx->flow]; + int ret; + + reinit_completion(&flow->complete); + meson_dma_start(mc, rctx->flow); + + ret =3D wait_for_completion_timeout(&flow->complete, + msecs_to_jiffies(500)); + if (ret =3D=3D 0) { + dev_err(mc->dev, "DMA timeout for flow %d\n", rctx->flow); + return -EINVAL; + } else if (ret < 0) { + dev_err(mc->dev, "Waiting for DMA completion is failed (%d)\n", ret); + return ret; + } + + if (rctx->partial_mapped) { + dma_unmap_single(mc->dev, rctx->partial_addr, + rctx->partial_size, + DMA_TO_DEVICE); + rctx->partial_size =3D 0; + rctx->partial_mapped =3D false; + } + + ctx->tloffset =3D 0; + + return 0; +} + +static void meson_setup_state_descs(struct hasher_ctx *ctx) +{ + struct ahash_request *req =3D ahash_request_cast(ctx->areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_dev *mc =3D tctx->mc; + struct meson_desc *desc; + int i; + + if (ctx->tloffset || rctx->begin_req) + return; + + for (i =3D 0; i < mc->pdata->setup_desc_cnt; i++) { + int offset =3D i * 16; + + desc =3D &mc->chanlist[rctx->flow].tl[ctx->tloffset]; + desc->t_src =3D cpu_to_le32(ctx->state_addr + offset); + desc->t_dst =3D cpu_to_le32(offset); + desc->t_status =3D cpu_to_le32(MESON_SHA_BUFFER_SIZE | + DESC_MODE_KEY | DESC_OWN); + + ctx->tloffset++; + } +} + +static int meson_hasher_do_one_request(struct crypto_engine *engine, void = *areq) +{ + struct ahash_request *req =3D ahash_request_cast(areq); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct meson_hasher_tfm_ctx *tctx =3D crypto_ahash_ctx_dma(tfm); + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + struct meson_dev *mc =3D tctx->mc; + struct hasher_ctx ctx =3D { + .tloffset =3D 0, + .src_offset =3D 0, + .nbytes =3D rctx->final_req ? 0 : req->nbytes, + .src_sg =3D req->src, + .areq =3D areq, + }; + unsigned int blocksize =3D crypto_ahash_blocksize(tfm); + unsigned int digest_size =3D crypto_ahash_digestsize(tfm); + bool final_req =3D rctx->final_req; + int ret; + + ctx.state_addr =3D dma_map_single(mc->dev, rctx->state, + sizeof(rctx->state), DMA_BIDIRECTIONAL); + ret =3D dma_mapping_error(mc->dev, ctx.state_addr); + if (ret) { + dev_err(mc->dev, "Cannot DMA MAP SHA state buffer"); + goto fail_map_single; + } + + ret =3D meson_hasher_req_map(req); + if (ret) + goto fail_map_req; + + for (;;) { + unsigned int len =3D ctx.src_sg ? + min(sg_dma_len(ctx.src_sg) - ctx.src_offset, ctx.nbytes) : 0; + + ctx.src_addr =3D 0; + ctx.todo =3D 0; + + if (!rctx->final_req && !ctx.nbytes) + break; + + meson_setup_state_descs(&ctx); + + if (rctx->partial_size && rctx->partial_size < blocksize) { + ret =3D meson_fill_partial_buffer(&ctx, len); + if (ret) + goto fail; + } else if (len && len < blocksize) { + memcpy(rctx->partial, sg_virt(ctx.src_sg) + ctx.src_offset, len); + + rctx->partial_size =3D len; + ctx.nbytes -=3D len; + ctx.src_offset +=3D len; + } else if (len) { + ctx.src_addr =3D sg_dma_address(ctx.src_sg) + ctx.src_offset; + ctx.todo =3D min(rounddown(DESC_MAXLEN, blocksize), + rounddown(len, blocksize)); + ctx.nbytes -=3D ctx.todo; + ctx.src_offset +=3D ctx.todo; + } + + if (ctx.src_sg && ctx.src_offset =3D=3D sg_dma_len(ctx.src_sg)) { + ctx.src_offset =3D 0; + ctx.src_sg =3D sg_next(ctx.src_sg); + } + + if (!ctx.todo && ctx.nbytes) + continue; + + if (!ctx.todo && !rctx->final_req && !ctx.tloffset) + continue; + + if (meson_setup_data_descs(&ctx)) { + ret =3D meson_kick_hardware(&ctx); + if (ret) + goto fail; + } + } + +fail: + meson_hasher_req_unmap(req); + +fail_map_req: + dma_unmap_single(mc->dev, ctx.state_addr, sizeof(rctx->state), + DMA_BIDIRECTIONAL); + +fail_map_single: + if (final_req && ret =3D=3D 0) + memcpy(req->result, rctx->state, digest_size); + + local_bh_disable(); + crypto_finalize_hash_request(engine, req, ret); + local_bh_enable(); + + return ret; +} + +static int meson_hasher_export(struct ahash_request *req, void *out) +{ + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + + memcpy(out, rctx, sizeof(*rctx)); + return 0; +} + +static int meson_hasher_import(struct ahash_request *req, const void *in) +{ + struct meson_hasher_req_ctx *rctx =3D ahash_request_ctx(req); + + memcpy(rctx, in, sizeof(*rctx)); + return 0; +} + +static int meson_hasher_init(struct crypto_tfm *tfm) +{ + struct meson_hasher_tfm_ctx *tctx =3D crypto_tfm_ctx_dma(tfm); + struct crypto_ahash *atfm =3D __crypto_ahash_cast(tfm); + struct hash_alg_common *alg =3D crypto_hash_alg_common(atfm); + struct meson_alg_template *algt =3D container_of(alg, + struct meson_alg_template, alg.ahash.base.halg); + + crypto_ahash_set_reqsize(atfm, crypto_ahash_statesize(atfm)); + + memset(tctx, 0, sizeof(struct meson_hasher_tfm_ctx)); + + tctx->mc =3D algt->mc; + + return 0; +} + +static struct meson_alg_template mc_algs[] =3D { +{ + .type =3D CRYPTO_ALG_TYPE_AHASH, + .blockmode =3D DESC_MODE_SHA1, + .alg.ahash.base =3D { + .halg =3D { + .base =3D { + .cra_name =3D "sha1", + .cra_driver_name =3D "sha1-gxl", + .cra_priority =3D 400, + .cra_blocksize =3D SHA1_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC, + .cra_ctxsize =3D sizeof(struct meson_hasher_tfm_ctx) + + CRYPTO_DMA_PADDING, + .cra_module =3D THIS_MODULE, + .cra_alignmask =3D 0, + .cra_init =3D meson_hasher_init, + }, + .digestsize =3D SHA1_DIGEST_SIZE, + .statesize =3D sizeof(struct meson_hasher_req_ctx), + }, + .init =3D meson_sha_init, + .update =3D meson_sha_update, + .final =3D meson_sha_final, + .digest =3D meson_sha_digest, + .export =3D meson_hasher_export, + .import =3D meson_hasher_import, + }, + .alg.ahash.op =3D { + .do_one_request =3D meson_hasher_do_one_request, + }, +}, +{ + .type =3D CRYPTO_ALG_TYPE_AHASH, + .blockmode =3D DESC_MODE_SHA224, + .alg.ahash.base =3D { + .halg =3D { + .base =3D { + .cra_name =3D "sha224", + .cra_driver_name =3D "sha224-gxl", + .cra_priority =3D 400, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC, + .cra_ctxsize =3D sizeof(struct meson_hasher_tfm_ctx) + + CRYPTO_DMA_PADDING, + .cra_module =3D THIS_MODULE, + .cra_alignmask =3D 0, + .cra_init =3D meson_hasher_init, + }, + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct meson_hasher_req_ctx), + }, + .init =3D meson_sha_init, + .update =3D meson_sha_update, + .final =3D meson_sha_final, + .digest =3D meson_sha_digest, + .export =3D meson_hasher_export, + .import =3D meson_hasher_import, + }, + .alg.ahash.op =3D { + .do_one_request =3D meson_hasher_do_one_request, + }, +}, +{ + .type =3D CRYPTO_ALG_TYPE_AHASH, + .blockmode =3D DESC_MODE_SHA256, + .alg.ahash.base =3D { + .halg =3D { + .base =3D { + .cra_name =3D "sha256", + .cra_driver_name =3D "sha256-gxl", + .cra_priority =3D 400, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_flags =3D CRYPTO_ALG_ASYNC, + .cra_ctxsize =3D sizeof(struct meson_hasher_tfm_ctx) + + CRYPTO_DMA_PADDING, + .cra_module =3D THIS_MODULE, + .cra_alignmask =3D 0, + .cra_init =3D meson_hasher_init, + }, + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct meson_hasher_req_ctx), + }, + .init =3D meson_sha_init, + .update =3D meson_sha_update, + .final =3D meson_sha_final, + .digest =3D meson_sha_digest, + .export =3D meson_hasher_export, + .import =3D meson_hasher_import, + }, + .alg.ahash.op =3D { + .do_one_request =3D meson_hasher_do_one_request, + }, +}, +}; + +int meson_hasher_register(struct meson_dev *mc) +{ + if (!mc->pdata->hasher_supported) { + pr_info("amlogic-gxl-hasher: hasher not supported at current platform"); + return 0; + } + + return meson_register_algs(mc, mc_algs, ARRAY_SIZE(mc_algs)); +} + +void meson_hasher_unregister(struct meson_dev *mc) +{ + if (!mc->pdata->hasher_supported) + return; + + meson_unregister_algs(mc, mc_algs, ARRAY_SIZE(mc_algs)); +} diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/= amlogic-gxl.h index e2e843ea6c4c..3380583813a8 100644 --- a/drivers/crypto/amlogic/amlogic-gxl.h +++ b/drivers/crypto/amlogic/amlogic-gxl.h @@ -5,6 +5,7 @@ * Copyright (C) 2018-2019 Corentin LABBE */ #include +#include #include #include #include @@ -23,13 +24,22 @@ =20 #define DESC_OPMODE_ECB (0 << 26) #define DESC_OPMODE_CBC (1 << 26) +#define DESC_OPMODE_SHA (0 << 26) =20 #define DESC_MAXLEN GENMASK(16, 0) =20 +#define DESC_MODE_SHA1 (0x5 << 20) +#define DESC_MODE_SHA224 (0x7 << 20) +#define DESC_MODE_SHA256 (0x6 << 20) + #define DESC_LAST BIT(18) +#define DESC_BEGIN BIT(24) +#define DESC_END BIT(25) #define DESC_ENCRYPTION BIT(28) #define DESC_OWN BIT(31) =20 +#define MESON_SHA_BUFFER_SIZE (SHA256_DIGEST_SIZE + 16) + /* * struct meson_desc - Descriptor for DMA operations * Note that without datasheet, some are unknown @@ -83,11 +93,13 @@ struct meson_flow { * @reg_descs: offset to descriptors register * @reg_status: offset to status register * @setup_desc_cnt: number of setup descriptor to configure. + * @hasher_supported: indecates whether hasher is supported. */ struct meson_pdata { u32 descs_reg; u32 status_reg; u32 setup_desc_cnt; + bool hasher_supported; }; =20 /* @@ -141,6 +153,38 @@ struct meson_cipher_tfm_ctx { struct crypto_skcipher *fallback_tfm; }; =20 +/* + * struct meson_hasher_req_ctx - context for a hasher request + * @state: state data + * @partial: partial buffer data. Contains sent data which + * size < blocksize + * @partial_size: size of the partial buffer + * @partial_addr: physical address of partial buffer + * @partial_mapped: indicates is partial buffer currently mapped or not + * @flags: request flags (for example, is this final req or not) + * @flow: the flow to use for this request + */ +struct meson_hasher_req_ctx { + u8 state[SHA256_DIGEST_SIZE + 16] ____cacheline_aligned; + u8 partial[SHA256_BLOCK_SIZE] ____cacheline_aligned; + unsigned int partial_size ____cacheline_aligned; + dma_addr_t partial_addr; + bool partial_mapped; + + bool begin_req; + bool final_req; + int flow; +}; + +/* + * struct meson_hasher_tfm_ctx - context for a hasher TFM + * @enginectx: crypto_engine used by this TFM + * @mc: pointer to the private data of driver handling this TFM + */ +struct meson_hasher_tfm_ctx { + struct meson_dev *mc; +}; + /* * struct meson_alg_template - crypto_alg template * @type: the CRYPTO_ALG_TYPE for this template @@ -155,6 +199,7 @@ struct meson_alg_template { u32 blockmode; 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charset="utf-8" Unforunately, not all Amlogic SoC's have a 192-bit key support for AES algo. In this case, use fallback. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-cipher.c | 7 +++++++ drivers/crypto/amlogic/amlogic-gxl-core.c | 1 + drivers/crypto/amlogic/amlogic-gxl.h | 2 ++ 3 files changed, 10 insertions(+) diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/a= mlogic/amlogic-gxl-cipher.c index 622e179320ff..65aa5cea81a8 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c +++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c @@ -41,6 +41,13 @@ static bool meson_cipher_need_fallback_sg(struct skciphe= r_request *areq, =20 static bool meson_cipher_need_fallback(struct skcipher_request *areq) { + struct crypto_skcipher *tfm =3D crypto_skcipher_reqtfm(areq); + struct meson_cipher_tfm_ctx *op =3D crypto_skcipher_ctx_dma(tfm); + struct meson_dev *mc =3D op->mc; + + if (op->keymode =3D=3D DESC_MODE_AES_192 && !mc->pdata->support_192bit_ke= y) + return true; + if (areq->cryptlen =3D=3D 0) return true; =20 diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 706db22b9f65..0f4b3db85031 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -279,6 +279,7 @@ static const struct meson_pdata meson_gxl_pdata =3D { .status_reg =3D 0x4, .setup_desc_cnt =3D 3, .hasher_supported =3D false, + .support_192bit_key =3D true, }; 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charset="utf-8" Tested via tcrypt module and with custom tests. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 0f4b3db85031..6529ae24b75f 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -282,11 +282,23 @@ static const struct meson_pdata meson_gxl_pdata =3D { .support_192bit_key =3D true, }; =20 +static const struct meson_pdata meson_g12a_pdata =3D { + .descs_reg =3D 0x0, + .status_reg =3D 0x8, + .setup_desc_cnt =3D 1, + .hasher_supported =3D true, + .support_192bit_key =3D false, +}; + static const struct of_device_id meson_crypto_of_match_table[] =3D { { .compatible =3D "amlogic,gxl-crypto", .data =3D &meson_gxl_pdata, }, + { + .compatible =3D "amlogic,g12a-crypto", + .data =3D &meson_g12a_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, meson_crypto_of_match_table); --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70E301E9072; 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Fri, 8 Nov 2024 13:29:48 +0300 (MSK) From: Alexey Romanov To: , , , , , , , , , , , CC: , , , , , , "Alexey Romanov" Subject: [PATCH v10 14/22] crypto: amlogic - Add support for AXG-series Date: Fri, 8 Nov 2024 13:28:59 +0300 Message-ID: <20241108102907.1788584-15-avromanov@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108102907.1788584-1-avromanov@salutedevices.com> References: <20241108102907.1788584-1-avromanov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189039 [Nov 08 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: avromanov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;smtp.sberdevices.ru:7.1.1,5.0.1;127.0.0.199:7.1.2, FromAlignment: s X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/08 08:34:00 #26834472 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" Tested via tcrypt module and with custom tests. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 6529ae24b75f..9452f05d2f10 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -290,6 +290,14 @@ static const struct meson_pdata meson_g12a_pdata =3D { .support_192bit_key =3D false, }; =20 +static const struct meson_pdata meson_axg_pdata =3D { + .descs_reg =3D 0x0, + .status_reg =3D 0x8, + .setup_desc_cnt =3D 3, + .hasher_supported =3D true, + .support_192bit_key =3D true, +}; + static const struct of_device_id meson_crypto_of_match_table[] =3D { { .compatible =3D "amlogic,gxl-crypto", @@ -299,6 +307,10 @@ static const struct of_device_id meson_crypto_of_match= _table[] =3D { .compatible =3D "amlogic,g12a-crypto", .data =3D &meson_g12a_pdata, }, + { + .compatible =3D "amlogic,axg-crypto", + .data =3D &meson_axg_pdata, + }, {}, }; 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charset="utf-8" This platform data also can be used for S4 as fallback. Tested via tcrypt module and with custom tests. Signed-off-by: Alexey Romanov --- drivers/crypto/amlogic/amlogic-gxl-core.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/aml= ogic/amlogic-gxl-core.c index 9452f05d2f10..55a35697c0d7 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -298,6 +298,14 @@ static const struct meson_pdata meson_axg_pdata =3D { .support_192bit_key =3D true, }; =20 +static const struct meson_pdata meson_a1_pdata =3D { + .descs_reg =3D 0x0, + .status_reg =3D 0x8, + .setup_desc_cnt =3D 1, + .hasher_supported =3D true, + .support_192bit_key =3D false, +}; + static const struct of_device_id meson_crypto_of_match_table[] =3D { { .compatible =3D "amlogic,gxl-crypto", @@ -311,6 +319,14 @@ static const struct of_device_id meson_crypto_of_match= _table[] =3D { .compatible =3D "amlogic,axg-crypto", .data =3D &meson_axg_pdata, }, + { + .compatible =3D "amlogic,a1-crypto", + .data =3D &meson_a1_pdata, + }, + { + .compatible =3D "amlogic,s4-crypto", + .data =3D &meson_a1_pdata, + }, {}, }; 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h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=PXcB6I+rzSxQAAvtHbaR16CeAftbse6o8hi0PuIbOH88PaFQcoT6ADPEfNShiSkOk iGmScSFj4qfj/Jl9sBGFJwuZkVnTbNGYgMW9oW73aMSGh2NHOTx+af1IA7YT12f2E2 EWqlFXtMMMlFLtDCLrnkFxHIfr8qiRSQZwT0kSHBbkbQgVEHiugFPCgbyw9glpIUMa sCt31K3yh0J6wcrUimC/kz+PGA9Q1HS0FhOzuvAgbzckAsU7234LBE63tHDRlQUJ/C FDkXTBA3ZCvfXlvJtx9e/OeUOJBT1eg1BPwP+6PNFe+tUQNCIE1MRcHsoYxfgjf9sS MtvvbZAnSVKNw== Received: from smtp.sberdevices.ru (p-i-exch-sc-m01.sberdevices.ru [172.16.192.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.sberdevices.ru (Postfix) with ESMTPS; Fri, 8 Nov 2024 13:29:50 +0300 (MSK) From: Alexey Romanov To: , , , , , , , , , , , CC: , , , , , , "Alexey Romanov" Subject: [PATCH v10 16/22] dt-bindings: crypto: amlogic,gxl-crypto: correct clk and interrupt lines Date: Fri, 8 Nov 2024 13:29:01 +0300 Message-ID: <20241108102907.1788584-17-avromanov@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108102907.1788584-1-avromanov@salutedevices.com> References: <20241108102907.1788584-1-avromanov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m2.sberdevices.ru (172.24.196.120) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 189039 [Nov 08 2024] X-KSMG-AntiSpam-Version: 6.1.1.7 X-KSMG-AntiSpam-Envelope-From: avromanov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 41 0.3.41 623e98d5198769c015c72f45fabbb9f77bdb702b, {Tracking_from_domain_doesnt_match_to}, smtp.sberdevices.ru:5.0.1,7.1.1;127.0.0.199:7.1.2;salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1, FromAlignment: s X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/11/08 08:34:00 #26834472 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" GXL and newer SoC's uses the DMA engine (not blkmv) for crypto HW. Crypto HW doesn't actually use the blkmv clk. At RTL level, crypto engine is hard-wired to a clk81 (CLKID_CLK81). Drop clock-names field from schema: name "blkmv" is invalid and "clk81" is confusing and sounds like something global. Also, GXL crypto IP isn't connected to the second interrupt line. This binding is useless, there are no users of this line. We must remove it from dt-bindings. Fixes: 7f7d115dfb51 ("dt-bindings: crypto: Add DT bindings documentation fo= r amlogic-crypto") Signed-off-by: Alexey Romanov --- .../devicetree/bindings/crypto/amlogic,gxl-crypto.yaml | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.ya= ml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml index 948e11ebe4ee..fdc39797a2a9 100644 --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml @@ -20,20 +20,15 @@ properties: interrupts: items: - description: Interrupt for flow 0 - - description: Interrupt for flow 1 =20 clocks: maxItems: 1 =20 - clock-names: - const: blkmv - required: - compatible - reg - interrupts - clocks - - clock-names =20 additionalProperties: false =20 @@ -46,7 +41,6 @@ examples: crypto: crypto-engine@c883e000 { compatible =3D "amlogic,gxl-crypto"; reg =3D <0xc883e000 0x36>; - interrupts =3D , ; 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charset="utf-8" Now crypto module available at G12A/G12B/S4/A1/SM1/AXG. 1. Add new compatibles: - amlogic,g12a-crypto - amlogic,axg-crypto - amlogic,a1-crypto - amlogic,s4-crypto (uses a1-crypto as fallback) Difference between this compatibles: * Different registers offset and the number of setup descriptors. * GXL doesn't support hashing like the others. * G12A/B and A1/S4 crypto HW don't support 192 AES key. * GXL, G12A/B and AXG require a reverse IV key before processing. 2. Add power-domains in schema, which is required only for A1. This is specific vendor design: in old SoC's power domain for crypto HW was not configurable, but in A1-series it is configurable. Signed-off-by: Alexey Romanov --- .../bindings/crypto/amlogic,gxl-crypto.yaml | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.ya= ml b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml index fdc39797a2a9..106a9d1fed69 100644 --- a/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/amlogic,gxl-crypto.yaml @@ -11,8 +11,16 @@ maintainers: =20 properties: compatible: - items: - - const: amlogic,gxl-crypto + oneOf: + - items: + - enum: + - amlogic,s4-crypto + - const: amlogic,a1-crypto + - enum: + - amlogic,gxl-crypto + - amlogic,axg-crypto + - amlogic,g12a-crypto + - amlogic,a1-crypto =20 reg: maxItems: 1 @@ -24,12 +32,24 @@ properties: clocks: maxItems: 1 =20 + power-domains: + maxItems: 1 + required: - compatible - reg - interrupts - clocks =20 +allOf: + - if: + properties: + compatible: + const: amlogic,a1-crypto + then: + required: + - power-domains + additionalProperties: false =20 examples: --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CB0B1E32C3; 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charset="utf-8" GXL and newer SoC's uses the DMA engine (not blkmv) for crypto HW. Crypto HW doesn't actually use the blkmv clk. At RTL level, crypto engine is hard weired to clk81 (CLKID_CLK81). And remove clock-names field: according to the new dt-binding, it is no longer required. Also, GXL crypto IP isn't to seconnd interrput line. So we must remove it from dt-bindings. Fixes: c4a0457eb858 ("ARM64: dts: amlogic: adds crypto hardware node") Signed-off-by: Alexey Romanov --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/d= ts/amlogic/meson-gxl.dtsi index f58d1790de1c..628d30fd5fcb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -68,10 +68,8 @@ acodec: audio-controller@c8832000 { crypto: crypto@c883e000 { compatible =3D "amlogic,gxl-crypto"; reg =3D <0x0 0xc883e000 0x0 0x36>; - interrupts =3D , - ; - clocks =3D <&clkc CLKID_BLKMV>; - clock-names =3D "blkmv"; + interrupts =3D ; + clocks =3D <&clkc CLKID_CLK81>; status =3D "okay"; }; }; --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BC001EF0B9; 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charset="utf-8" This patch adds a crypto node declaration. With the Amlogic crypto driver we can use HW implementation of SHA1/224/256 and AES algo. Signed-off-by: Alexey Romanov --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-a1.dtsi index 1eba0afb3fd9..5ffb45503e57 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -100,6 +100,12 @@ spifc: spi@fd000400 { status =3D "disabled"; }; =20 + clk81: clk81 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <64000000>; + }; + apb: bus@fe000000 { compatible =3D "simple-bus"; reg =3D <0x0 0xfe000000 0x0 0x1000000>; @@ -664,6 +670,14 @@ sd_emmc: mmc@10000 { power-domains =3D <&pwrc PWRC_SD_EMMC_ID>; status =3D "disabled"; }; + + crypto: crypto@6000 { + compatible =3D "amlogic,a1-crypto"; + reg =3D <0x0 0x6000 0x0 0x48>; + interrupts =3D ; + clocks =3D <&clk81>; + power-domains =3D <&pwrc PWRC_DMA_ID>; + }; }; =20 usb: usb@fe004400 { --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 089711F12ED; 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charset="utf-8" This patch adds a crypto node declaration for Amlogic S4-series. With the Amlogic crypto driver we can use HW implementation of SHA1/224/256 and AES algo. Signed-off-by: Alexey Romanov --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-s4.dtsi index 957577d986c0..39a226d75a3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -95,6 +95,12 @@ gic: interrupt-controller@fff01000 { interrupts =3D ; }; =20 + clk81: clk81 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <166000000>; + }; + apb4: bus@fe000000 { compatible =3D "simple-bus"; reg =3D <0x0 0xfe000000 0x0 0x480000>; @@ -586,6 +592,13 @@ mux { =20 }; =20 + crypto: crypto@440400 { + compatible =3D "amlogic,s4-crypto", "amlogic,a1-crypto"; + reg =3D <0x0 0x440400 0x0 0x48>; + interrupts =3D ; + clocks =3D <&clk81>; + }; + gpio_intc: interrupt-controller@4080 { compatible =3D "amlogic,meson-s4-gpio-intc", "amlogic,meson-gpio-intc"; --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B0C71F1312; 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charset="utf-8" This patch adds a crypto node declaration for Amlogic G12-series. With the Amlogic crypto driver we can use HW implementation of SHA1/224/256 and AES algo. Signed-off-by: Alexey Romanov --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64= /boot/dts/amlogic/meson-g12-common.dtsi index 49b51c54013f..97c5c8464948 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1733,6 +1733,13 @@ internal_ephy: ethernet-phy@8 { }; }; }; + + crypto: crypto@3e000 { + compatible =3D "amlogic,g12a-crypto"; + reg =3D <0x0 0x3e000 0x0 0x48>; + interrupts =3D ; + clocks =3D <&clkc CLKID_CLK81>; + }; }; =20 aobus: bus@ff800000 { --=20 2.34.1 From nobody Sun Nov 24 00:03:57 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7361F1F4704; Fri, 8 Nov 2024 10:29:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" This patch adds a crypto node declaration. With the Amlogic crypto driver we can use HW implementation of SHA1/224/256 and AES algo. Signed-off-by: Alexey Romanov --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/d= ts/amlogic/meson-axg.dtsi index e9b22868983d..20a5fff3cda5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -294,6 +294,13 @@ ethmac: ethernet@ff3f0000 { status =3D "disabled"; }; =20 + crypto: crypto@ff63e000 { + compatible =3D "amlogic,axg-crypto"; + reg =3D <0x0 0xff63e000 0x0 0x48>; + interrupts =3D ; + clocks =3D <&clkc CLKID_CLK81>; + }; + pcie_phy: phy@ff644000 { compatible =3D "amlogic,axg-pcie-phy"; reg =3D <0x0 0xff644000 0x0 0x1c>; --=20 2.34.1