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charset="utf-8" Add SPDIF IPG clk. The SPDIF IPG clock and root clock share same clock gate. Signed-off-by: Shengjiu Wang Reviewed-by: Frank Li Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/imx93-clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/= clock/imx93-clock.h index 6c685067288b..c393fad3a346 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -209,5 +209,6 @@ #define IMX91_CLK_ENET2_REGULAR 204 #define IMX91_CLK_ENET2_REGULAR_GATE 205 #define IMX91_CLK_ENET1_QOS_TSN_GATE 206 +#define IMX93_CLK_SPDIF_IPG 207 =20 #endif --=20 2.34.1 From nobody Sat Nov 23 23:56:04 2024 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2065.outbound.protection.outlook.com [40.107.105.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1AC61E22EE; Fri, 8 Nov 2024 09:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Split IMX93_CLK_SPDIF_IPG from IMX93_CLK_SPDIF_GATE because the IMX93_CLK_SPDIF_GATE controls the gate of IPG clock and root clock. Without this change, disabling IMX93_CLK_SPDIF_GATE would also disable the IPG clock, causing register access failures. Signed-off-by: Shengjiu Wang Reviewed-by: Frank Li --- drivers/clk/imx/clk-imx93.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 58a516dd385b..eb818db008fb 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -15,7 +15,7 @@ =20 #include "clk.h" =20 -#define IMX93_CLK_END 207 +#define IMX93_CLK_END 208 =20 #define PLAT_IMX93 BIT(0) #define PLAT_IMX91 BIT(1) @@ -38,6 +38,7 @@ static u32 share_count_sai2; static u32 share_count_sai3; static u32 share_count_mub; static u32 share_count_pdm; +static u32 share_count_spdif; =20 static const char * const a55_core_sels[] =3D {"a55_alt", "arm_pll"}; static const char *parent_names[MAX_SEL][4] =3D { @@ -252,7 +253,8 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, - { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, + { IMX93_CLK_SPDIF_IPG, "spdif_ipg_clk", "bus_wakeup_root", 0x9c00, 0, &s= hare_count_spdif}, + { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, 0, &share_count_= spdif}, { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLA= T_IMX93, }, { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL= , PLAT_IMX93, }, --=20 2.34.1 From nobody Sat Nov 23 23:56:04 2024 Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2046.outbound.protection.outlook.com [40.107.103.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA2451E32CA; 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Received: from AM0PR04MB7044.eurprd04.prod.outlook.com (2603:10a6:208:191::20) by GV1PR04MB9216.eurprd04.prod.outlook.com (2603:10a6:150:2b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.19; Fri, 8 Nov 2024 09:58:24 +0000 Received: from AM0PR04MB7044.eurprd04.prod.outlook.com ([fe80::7be0:296:768c:e891]) by AM0PR04MB7044.eurprd04.prod.outlook.com ([fe80::7be0:296:768c:e891%6]) with mapi id 15.20.8137.019; Fri, 8 Nov 2024 09:58:24 +0000 From: Shengjiu Wang To: abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, imx@lists.linux.dev, shengjiu.wang@gmail.com Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock Date: Fri, 8 Nov 2024 18:07:59 +0800 Message-Id: <20241108100759.682260-4-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241108100759.682260-1-shengjiu.wang@nxp.com> References: <20241108100759.682260-1-shengjiu.wang@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SG2PR06CA0213.apcprd06.prod.outlook.com (2603:1096:4:68::21) To AM0PR04MB7044.eurprd04.prod.outlook.com (2603:10a6:208:191::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM0PR04MB7044:EE_|GV1PR04MB9216:EE_ X-MS-Office365-Filtering-Correlation-Id: 66b1bd4b-e17d-49c4-1fb2-08dcffdbe277 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|366016|52116014|921020|38350700014; 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charset="utf-8" IMX93_CLK_BUS_WAKEUP is not accurate IPG clock, which missed the clock gate part. IMX93_CLK_SPDIF_IPG is the correct clock. Fixes: 1c4a4f7362fd ("arm64: dts: imx93: Add audio device nodes") Signed-off-by: Shengjiu Wang Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts= /freescale/imx93.dtsi index 688488de8cd2..56766fdb0b1e 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -925,7 +925,7 @@ xcvr: xcvr@42680000 { reg-names =3D "ram", "regs", "rxfifo", "txfifo"; interrupts =3D , ; - clocks =3D <&clk IMX93_CLK_BUS_WAKEUP>, + clocks =3D <&clk IMX93_CLK_SPDIF_IPG>, <&clk IMX93_CLK_SPDIF_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUD_XCVR_GATE>; --=20 2.34.1