From nobody Wed Dec 17 10:25:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 410365473E; Fri, 8 Nov 2024 09:16:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731057400; cv=none; b=gFx5klkVw3yPBSVNbUBS4zURiw6UmUAqrexE97iJBzlk37rWIUfDEH58vUijn4cUEEoWe12gGYClwKnU9/dPAexz5Sv3mF7u0zGtkExpuq2EOZtJBvMnL6cuPPyAOTRecIbtiDdh6mlm2lbRTqq35OgSq777KB/ILtgYNnpDh2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731057400; c=relaxed/simple; bh=xh6P2cgEcFDwQtyiWnMsHhk3bmNyrDfk2v0HwaVb07M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iaPXlrbKbyb6B3SOKfbNw2bYtC978pOWsJEv9jz/c3Y9Br7pZxcZ/mjJL4PUxM0H8lRntSspTGksbFpFzLDAIZdP26cx7H4n6sdb5LgcrOIJ0nYoHEy9SEe8qQYZFio76GRxjERe/UIkrGOedN2KSAOjMpW010Wv5NEWosTOSH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BC87C4CECD; Fri, 8 Nov 2024 09:16:37 +0000 (UTC) From: Huacai Chen To: Huacai Chen Cc: Xuerui Wang , loongarch@lists.linux.dev, Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-rt-devel@lists.linux.dev, Guo Ren , Jiaxun Yang , linux-kernel@vger.kernel.org, Huacai Chen Subject: [PATCH 1/3] LoongArch: Reduce min_delta for the arch clockevent device Date: Fri, 8 Nov 2024 17:15:43 +0800 Message-ID: <20241108091545.4182229-2-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241108091545.4182229-1-chenhuacai@loongson.cn> References: <20241108091545.4182229-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now the min_delta is 0x600 (1536) for LoongArch's constant clockevent device. For a 100MHz hardware timer this means ~15us. This is a little big, especially for PREEMPT_RT enabled kernels. So reduce it to 1000 (we don't want too small values to affect performance). Signed-off-by: Huacai Chen --- arch/loongarch/kernel/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c index 46d7d40c87e3..e914b27a7c89 100644 --- a/arch/loongarch/kernel/time.c +++ b/arch/loongarch/kernel/time.c @@ -127,7 +127,7 @@ void sync_counter(void) int constant_clockevent_init(void) { unsigned int cpu =3D smp_processor_id(); - unsigned long min_delta =3D 0x600; + unsigned long min_delta =3D 1000; unsigned long max_delta =3D (1UL << 48) - 1; struct clock_event_device *cd; static int irq =3D 0, timer_irq_installed =3D 0; --=20 2.43.5 From nobody Wed Dec 17 10:25:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C70371E049C; Fri, 8 Nov 2024 09:17:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731057443; cv=none; b=fEKk3breNxR6rw6fxV1As5oBRkrdEF+IGFYIVGTgDKeiz387poJZbgPPQr3kg/KBHC+4SfhABpmd1GXPUZzMQd7SxbvpJB8/r7uDlrnh+RIk7N5bRv62+9o8HzRrezj+Ku91U8cohTQvJ4VwnXhCAXf7hsWco8Sn1fNNhv3zkYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731057443; c=relaxed/simple; bh=Bbcx8onFO1llkh1bzdef+8Wwk79wyxRsWbhQhNlkkZk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tzK0jGL1Cp4NNxlplAtHedUUKiXFF0iQ8hJBavX5OR6ulU1Rbh40Kg1TsdAapBppJntir7SKSH0wGU3t2iUwSOEZPL7rVZDgH4TP69YNwxKw04xtxxKiJtjJJPsgQoo8+l+zpa4HHOrS1kTVjvWn6ztSkXiRvnQupkSJwiaen4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB498C4CECD; Fri, 8 Nov 2024 09:17:20 +0000 (UTC) From: Huacai Chen To: Huacai Chen Cc: Xuerui Wang , loongarch@lists.linux.dev, Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-rt-devel@lists.linux.dev, Guo Ren , Jiaxun Yang , linux-kernel@vger.kernel.org, Huacai Chen Subject: [PATCH 2/3] LoongArch: Select HAVE_POSIX_CPU_TIMERS_TASK_WORK Date: Fri, 8 Nov 2024 17:15:44 +0800 Message-ID: <20241108091545.4182229-3-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241108091545.4182229-1-chenhuacai@loongson.cn> References: <20241108091545.4182229-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move POSIX CPU timer expiry and signal delivery into task context to allow PREEMPT_RT setups to coexist with KVM. Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index bb35c34f86d2..3734f5dd9a57 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -155,6 +155,7 @@ config LOONGARCH select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP + select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_PREEMPT_DYNAMIC_KEY select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RELIABLE_STACKTRACE if UNWINDER_ORC --=20 2.43.5 From nobody Wed Dec 17 10:25:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8233519413C; Fri, 8 Nov 2024 09:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731057466; cv=none; b=NWVtYBF04oPGSMTCKR/BOwNFXzZQez2vRvQgr058Qn/mboOBE0SLHdRhRdJH/nslDMrhdvrxYrNw1YpRteZeCIM7h4cmW4xnykF/UnqBRG03o7gGyUoxkEq0lj6ZrgAk/bjNAOX2LUwkXFBScakB1cNy+tHjaKbGAwJ4AbB2lYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731057466; c=relaxed/simple; bh=i1EUALcaoQLHIIQr6unzXd4MZBhm66Bp2f/Nm0feaU8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=olhHmYEzb3GUpKb7D5NKaijHNXmQ1JAGlNW/aUrmi47tJU9rTA2jArU/ZeR0+t77uSm4tuoqTuxBaSTA6rtb/Ub8V/bl6hFMKy5KtWaSOOY32xjU+xwLyF5DgGKaDwxApxeLU0RMRdABlIdEKqvSXspfEH1oFHOEgWeGMYCKHcs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C6D2C4CECD; Fri, 8 Nov 2024 09:17:43 +0000 (UTC) From: Huacai Chen To: Huacai Chen Cc: Xuerui Wang , loongarch@lists.linux.dev, Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-rt-devel@lists.linux.dev, Guo Ren , Jiaxun Yang , linux-kernel@vger.kernel.org, Huacai Chen Subject: [PATCH 3/3] LoongArch: Allow to enable PREEMPT_RT Date: Fri, 8 Nov 2024 17:15:45 +0800 Message-ID: <20241108091545.4182229-4-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20241108091545.4182229-1-chenhuacai@loongson.cn> References: <20241108091545.4182229-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is really time. LoongArch has all the required architecture related changes, that have been identified over time, in order to enable PREEMPT_RT. With the recent printk changes, the last known road block has been addressed. Allow to enable PREEMPT_RT on LoongArch. Below are the latency data from cyclictest on a 4-core Loongson-3A5000 machine, with a "make -j8" kernel building workload in the background. 1. PREEMPT kernel with default configuration: ./cyclictest -a -t -m -i200 -d0 -p99 policy: fifo: loadavg: 8.78 8.96 8.64 10/296 64800 T: 0 ( 4592) P:99 I:200 C:14838617 Min: 3 Act: 6 Avg: 8 Max: 844 T: 1 ( 4593) P:99 I:200 C:14838765 Min: 3 Act: 9 Avg: 8 Max: 909 T: 2 ( 4594) P:99 I:200 C:14838510 Min: 3 Act: 7 Avg: 8 Max: 832 T: 3 ( 4595) P:99 I:200 C:14838631 Min: 3 Act: 8 Avg: 8 Max: 931 2. PREEMPT_RT kernel with default configuration: ./cyclictest -a -t -m -i200 -d0 -p99 policy: fifo: loadavg: 10.38 10.47 10.35 9/336 77788 T: 0 ( 3941) P:99 I:200 C:19439626 Min: 3 Act: 12 Avg: 8 Max: 227 T: 1 ( 3942) P:99 I:200 C:19439624 Min: 2 Act: 11 Avg: 8 Max: 184 T: 2 ( 3943) P:99 I:200 C:19439623 Min: 3 Act: 4 Avg: 7 Max: 223 T: 3 ( 3944) P:99 I:200 C:19439623 Min: 2 Act: 10 Avg: 7 Max: 226 3. PREEMPT_RT kernel with tuned configuration: ./cyclictest -a -t -m -i200 -d0 -p99 policy: fifo: loadavg: 10.52 10.66 10.62 12/334 109397 T: 0 ( 4765) P:99 I:200 C:29335186 Min: 3 Act: 6 Avg: 8 Max: 62 T: 1 ( 4766) P:99 I:200 C:29335185 Min: 3 Act: 10 Avg: 8 Max: 52 T: 2 ( 4767) P:99 I:200 C:29335184 Min: 3 Act: 8 Avg: 8 Max: 64 T: 3 ( 4768) P:99 I:200 C:29335183 Min: 3 Act: 12 Avg: 8 Max: 53 Main instruments of tuned configuration include: Disable the boot rom space in BIOS for kernel, in order to avoid speculative access to low- speed memory; Disable CPUFreq scaling; Disable RTC synchronization in the ntpd/chronyd service. Signed-off-by: Huacai Chen --- arch/loongarch/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 3734f5dd9a57..26ed9d925e7f 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -66,6 +66,7 @@ config LOONGARCH select ARCH_SUPPORTS_LTO_CLANG select ARCH_SUPPORTS_LTO_CLANG_THIN select ARCH_SUPPORTS_NUMA_BALANCING + select ARCH_SUPPORTS_RT select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_CMPXCHG_LOCKREF select ARCH_USE_QUEUED_RWLOCKS --=20 2.43.5