From nobody Sat Nov 30 00:35:50 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADD9A19DF64; Fri, 8 Nov 2024 06:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047996; cv=none; b=D17UxJEazEX12T8OG3iwkWuJo3yA8Ix4Gb2PIIUWktWnNEuK9DlSVzmOJU9e8+U64mRVSqlVs1RDTUN3xugZ898A/sMFxi2DbIN3gYocZdCNAW8TLAQdhSHxahSPtPiJYoAkdrs7IsrtoS1VVPZTAKHhBdBsqLnJzTCC9WRwVJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047996; c=relaxed/simple; bh=ftHl8cvJxXClXUyb+pLcTha+k6Boj0naoJhKG2j7H5o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cJyq1OcL4qNeXdPbgW4ZA6JXGzMnc66VUp8UPJUjSO7xt0pCbZVjeAL7VlFsp5IY05ExqkXQl9jTY+fnkbHDhfr0VBw0AOL6Cv+rsfucCfXPQEb/tyithlpBw58O89PhlLXI8KVTHiPbZQ7TlXiOIsM662Ptx4j38dQU501RPvY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=SFKN9PIL; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SFKN9PIL" X-UUID: 40c6c8009d9c11efbd192953cf12861f-20241108 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=H7HqclB1EjyymZaIs5NdapuhMiQdBA7440+mZymKrGw=; b=SFKN9PILuj6x0mTzrjvzbjhlD8L+4s8tG1q7/2CegJdy7IxLdCzgxmOLUtSvgxR8xpcdkN1LKXcnxZ3q1r+cJdxxoq/HTTpQvBljSaxJqXUy0irE/eI+Ju/tqMxhQ/roO5sjA3RuanOg9z0t7Wb8sXFEVNYZtqdGDzGwyHSGLcc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42,REQID:1bf7bd15-5486-4664-b691-87261006050c,IP:0,U RL:0,TC:0,Content:18,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:18 X-CID-META: VersionHash:b0fcdc3,CLOUDID:76ffb8ca-91e6-4060-9516-6ba489b4e2dc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:4,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 40c6c8009d9c11efbd192953cf12861f-20241108 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1531420485; Fri, 08 Nov 2024 14:39:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 8 Nov 2024 14:39:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 8 Nov 2024 14:39:48 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v2 1/4] cpufreq: mediatek: CCI support SoC , the transition_delay set to 10 ms Date: Fri, 8 Nov 2024 14:39:39 +0800 Message-ID: <20241108063942.19744-2-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> References: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SoC with CCI architecture should set transition_delay to 10 ms because cpufreq need to call devfreq notifier in async mode. if delay less than 10 ms, it may get wrong OPP-level in devfreq passive governor. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-= cpufreq.c index 663f61565cf7..f63183154e9a 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -597,6 +597,9 @@ static int mtk_cpufreq_init(struct cpufreq_policy *poli= cy) policy->driver_data =3D info; policy->clk =3D info->cpu_clk; =20 + if (info->soc_data->ccifreq_supported) + policy->transition_delay_us =3D 10000; + return 0; } =20 --=20 2.45.2 From nobody Sat Nov 30 00:35:50 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CAFF1D0E31; Fri, 8 Nov 2024 06:39:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047999; cv=none; b=KnpdwYAW1ZcNXyPA5IU8vH4js5z5HuqGjY8aWLF6KhODelFgeZmHR5V7xZQ7qsz9EgwYiO5vO9WlhLmVMM5FnTNqlsoRYG+16kmAxVSZCEcuWIon+v9Ja08Ked86AnFB9uu73vvXcs6MMWExzhYm+tWHKDHVi00GAvioG/pjm60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047999; c=relaxed/simple; bh=9TZjTWvaB7JyzHpmRZtPm8NMcm/KbfTIN+KV4Yqr+/U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mpbLwZNCZTJLDZsfK9nlQu2eI7VR+QaLhAGcaqySnw9t79PvFP1EfdMSklg0PZhVzkMoG4AOcNtUoGYVdCDONn6Y3Pq4HDbluurVcfWEZ0zYk70iUwpV0AbcJ8+0mPb0RjObkCqVtAHlobRneFdNwtKK50QrOIFjDsQedfPaJ7Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=K7Mc2Ndg; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="K7Mc2Ndg" X-UUID: 41116a049d9c11efbd192953cf12861f-20241108 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=fZzOBJyGR/2ugctt1qnXoWEeJcymzZlDZvjwEAiy2rY=; b=K7Mc2NdgXx3oJSf3978b5tDpGeNEUbq/kDmfOE34thx/rEnKx892REt0X9Jbi3ol9hx4RQeZcU08DdCaki5U35AtKIwoOtaTkfu9obBVXKCskzAt9hGYnjLUSgEXU2l0K4ujZoYgGfyVJJTO8lzW2NHWCm/Xb7+IpRfpUCBfNyo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42,REQID:192fe834-eecd-4aca-9d08-762a66606d35,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:b0fcdc3,CLOUDID:e466d31b-4f51-4e1d-bb6a-1fd98b6b19d2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 41116a049d9c11efbd192953cf12861f-20241108 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 646693054; Fri, 08 Nov 2024 14:39:50 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 8 Nov 2024 14:39:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 8 Nov 2024 14:39:48 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , "Kyungmin Park" , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v2 2/4] cpufreq: mediatek: using global lock avoid race condition Date: Fri, 8 Nov 2024 14:39:40 +0800 Message-ID: <20241108063942.19744-3-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> References: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.125600-8.000000 X-TMASE-MatchedRID: 2aTVZGXuTB8sJluZlyHlY8AmcZEx8XHJnQkHrAHoKqb8rSaNLblw6hG5 9Y7tVhgxvNRgKxmpoNYwyeDC17g6+B2P280ZiGmROdTVX41pez3BDQIKmpUdLAqiCYa6w8tvMG4 kjAsJeaAWra7pA1ewApurMMf0bt5Mup2UZ4H9upSk3yyn4uPtLU9nxZsOR/FTuqWf6Nh7tmFASA ka3p+8QkyDxZlLLvUwcV5MmhPtBFQM8jMXjBF+sBRFJJyf5BJe3QfwsVk0UbvdirxFVpmK9U5+L K/FQ32MzLexlFBo/3EJGanVe2V1AgN77mZJF+nGoxMg92LXk6M= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.125600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7423304FBCBAB8CF36A280E21E56FD3531BDAF052ED00A63F9444ADC805B115F2000:8 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In mtk_cpufreq_set_target() is re-enter function but the mutex lock decalre in mtk_cpu_dvfs_info structure for each policy. It should change to global variable for critical session avoid race condition with 2 or more policy. add mtk_cpufreq_get() replace cpufreq_generic_get() and use global lock avoid return wrong clock. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 39 ++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-= cpufreq.c index f63183154e9a..6b3cd2b803bf 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -49,8 +49,6 @@ struct mtk_cpu_dvfs_info { bool need_voltage_tracking; int vproc_on_boot; int pre_vproc; - /* Avoid race condition for regulators between notify and policy */ - struct mutex reg_lock; struct notifier_block opp_nb; unsigned int opp_cpu; unsigned long current_freq; @@ -59,6 +57,9 @@ struct mtk_cpu_dvfs_info { bool ccifreq_bound; }; =20 +/* Avoid race condition for regulators between notify and policy */ +static DEFINE_MUTEX(mtk_policy_lock); + static struct platform_device *cpufreq_pdev; =20 static LIST_HEAD(dvfs_info_list); @@ -209,12 +210,12 @@ static int mtk_cpufreq_set_target(struct cpufreq_poli= cy *policy, long freq_hz, pre_freq_hz; int vproc, pre_vproc, inter_vproc, target_vproc, ret; =20 + mutex_lock(&mtk_policy_lock); + inter_vproc =3D info->intermediate_voltage; =20 pre_freq_hz =3D clk_get_rate(cpu_clk); =20 - mutex_lock(&info->reg_lock); - if (unlikely(info->pre_vproc <=3D 0)) pre_vproc =3D regulator_get_voltage(info->proc_reg); else @@ -308,7 +309,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy= *policy, info->current_freq =3D freq_hz; =20 out: - mutex_unlock(&info->reg_lock); + mutex_unlock(&mtk_policy_lock); =20 return ret; } @@ -316,19 +317,20 @@ static int mtk_cpufreq_set_target(struct cpufreq_poli= cy *policy, static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, unsigned long event, void *data) { - struct dev_pm_opp *opp =3D data; + struct dev_pm_opp *opp; struct dev_pm_opp *new_opp; struct mtk_cpu_dvfs_info *info; unsigned long freq, volt; struct cpufreq_policy *policy; int ret =3D 0; =20 + mutex_lock(&mtk_policy_lock); + opp =3D data; info =3D container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); =20 if (event =3D=3D OPP_EVENT_ADJUST_VOLTAGE) { freq =3D dev_pm_opp_get_freq(opp); =20 - mutex_lock(&info->reg_lock); if (info->current_freq =3D=3D freq) { volt =3D dev_pm_opp_get_voltage(opp); ret =3D mtk_cpufreq_set_voltage(info, volt); @@ -336,7 +338,6 @@ static int mtk_cpufreq_opp_notifier(struct notifier_blo= ck *nb, dev_err(info->cpu_dev, "failed to scale voltage: %d\n", ret); } - mutex_unlock(&info->reg_lock); } else if (event =3D=3D OPP_EVENT_DISABLE) { freq =3D dev_pm_opp_get_freq(opp); =20 @@ -361,6 +362,7 @@ static int mtk_cpufreq_opp_notifier(struct notifier_blo= ck *nb, } } } + mutex_unlock(&mtk_policy_lock); =20 return notifier_from_errno(ret); } @@ -495,7 +497,6 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_i= nfo *info, int cpu) info->intermediate_voltage =3D dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); =20 - mutex_init(&info->reg_lock); info->current_freq =3D clk_get_rate(info->cpu_clk); =20 info->opp_cpu =3D cpu; @@ -610,13 +611,31 @@ static void mtk_cpufreq_exit(struct cpufreq_policy *p= olicy) dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table); } =20 +static unsigned int mtk_cpufreq_get(unsigned int cpu) +{ + struct mtk_cpu_dvfs_info *info; + unsigned long current_freq; + + mutex_lock(&mtk_policy_lock); + info =3D mtk_cpu_dvfs_info_lookup(cpu); + if (!info) { + mutex_unlock(&mtk_policy_lock); + return 0; + } + + current_freq =3D info->current_freq / 1000; + mutex_unlock(&mtk_policy_lock); + + return current_freq; +} + static struct cpufreq_driver mtk_cpufreq_driver =3D { .flags =3D CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY | CPUFREQ_IS_COOLING_DEV, .verify =3D cpufreq_generic_frequency_table_verify, .target_index =3D mtk_cpufreq_set_target, - .get =3D cpufreq_generic_get, + .get =3D mtk_cpufreq_get, .init =3D mtk_cpufreq_init, .exit =3D mtk_cpufreq_exit, .register_em =3D cpufreq_register_em_with_opp, --=20 2.45.2 From nobody Sat Nov 30 00:35:50 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3AC61CCB49; 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Fri, 08 Nov 2024 14:39:50 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 8 Nov 2024 14:39:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 8 Nov 2024 14:39:48 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v2 3/4] cpufreq: mediatek: Add CPUFREQ_ASYNC_NOTIFICATION flag Date: Fri, 8 Nov 2024 14:39:41 +0800 Message-ID: <20241108063942.19744-4-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> References: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUFREQ_ASYNC_NOTIFICATION flages for cpufreq policy because some of process will get CPU frequency by cpufreq sysfs node. It may get wrong frequency then call cpufreq_out_of_sync() to fixed frequency. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-= cpufreq.c index 6b3cd2b803bf..3369bdd9a348 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -209,12 +209,16 @@ static int mtk_cpufreq_set_target(struct cpufreq_poli= cy *policy, struct dev_pm_opp *opp; long freq_hz, pre_freq_hz; int vproc, pre_vproc, inter_vproc, target_vproc, ret; + struct cpufreq_freqs freqs; =20 mutex_lock(&mtk_policy_lock); =20 inter_vproc =3D info->intermediate_voltage; + pre_freq_hz =3D policy->cur * 1000; =20 - pre_freq_hz =3D clk_get_rate(cpu_clk); + freqs.old =3D policy->cur; + freqs.new =3D freq_table[index].frequency; + cpufreq_freq_transition_begin(policy, &freqs); =20 if (unlikely(info->pre_vproc <=3D 0)) pre_vproc =3D regulator_get_voltage(info->proc_reg); @@ -309,6 +313,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy= *policy, info->current_freq =3D freq_hz; =20 out: + cpufreq_freq_transition_end(policy, &freqs, false); mutex_unlock(&mtk_policy_lock); =20 return ret; @@ -632,6 +637,7 @@ static unsigned int mtk_cpufreq_get(unsigned int cpu) static struct cpufreq_driver mtk_cpufreq_driver =3D { .flags =3D CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY | + CPUFREQ_ASYNC_NOTIFICATION | CPUFREQ_IS_COOLING_DEV, .verify =3D cpufreq_generic_frequency_table_verify, .target_index =3D mtk_cpufreq_set_target, --=20 2.45.2 From nobody Sat Nov 30 00:35:50 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 613E61CF7B6; Fri, 8 Nov 2024 06:39:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047997; cv=none; b=DxZRuqbEsA3dT7IAq7UjVSxSXxjWpnJ+jKvU9Fm24gEXQVMlFAYFAPNFwiTYRQg6jeHTDJkbsxTdNd383IH0BZr5Lzh6nKDoBUumk6j/J/0WDBvHk770CcZ+erMlCQhfHv5Es3C1WxG6aLo4+XguYXtKBr//nFNGQYGPT/qndmQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731047997; c=relaxed/simple; bh=ueT+ccky2jPcZMmNDBe7fttcASXZUBPn8YOGTnygoSM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CRcHMC5ZCsXpMMgI5uO1BsS6MPgC99nTG7YhvnF8s1/xeBeQUkJ+bFI9HNQy+82eaxY697mmSlLjLGdzm7Zv4zegph5eST+wK+zJldgeQhwigiuJxcTqAd0b9oiiGskXmsDI+EwSHFIjoVOdNT1rIXS4jmg6yzdbUjcxAue1Ye0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=B0te3za8; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="B0te3za8" X-UUID: 40c9f3049d9c11efbd192953cf12861f-20241108 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=HUfXCWBMH14NMLsYilX9Z6Z+VvsztsPB6r7RvqOT/YM=; b=B0te3za8+DxBtynEL5rppTJ/gmGnsjvFEu0LoHFVeWFOLqOfsUIDTLMe6n8s1A4DaWx7dHxAs5S64UUxrnbtzeymHniu31g34hesUYooZ6XuvlMpSqlBgKV/qvx3FmKqqADkXBIAHLJ6tLtReAyYp0Qg9nINMzkktaJgdfp8UZA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42,REQID:5695cee6-98fc-4df6-8ec1-4a44534a3c04,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:b0fcdc3,CLOUDID:a266d31b-4f51-4e1d-bb6a-1fd98b6b19d2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 40c9f3049d9c11efbd192953cf12861f-20241108 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1064750681; Fri, 08 Nov 2024 14:39:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 8 Nov 2024 14:39:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 8 Nov 2024 14:39:49 +0800 From: Mark Tseng To: "Rafael J . Wysocki" , Viresh Kumar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Subject: [PATCH v2 4/4] cpufreq: mediatek: data safety protect Date: Fri, 8 Nov 2024 14:39:42 +0800 Message-ID: <20241108063942.19744-5-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> References: <20241108063942.19744-1-chun-jen.tseng@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" get policy data in global lock session avoid get wrong data. Signed-off-by: Mark Tseng --- drivers/cpufreq/mediatek-cpufreq.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-= cpufreq.c index 3369bdd9a348..3303b6d72ea7 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -201,11 +201,11 @@ static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info= *info) static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { - struct cpufreq_frequency_table *freq_table =3D policy->freq_table; - struct clk *cpu_clk =3D policy->clk; - struct clk *armpll =3D clk_get_parent(cpu_clk); - struct mtk_cpu_dvfs_info *info =3D policy->driver_data; - struct device *cpu_dev =3D info->cpu_dev; + struct cpufreq_frequency_table *freq_table; + struct clk *cpu_clk; + struct clk *armpll; + struct mtk_cpu_dvfs_info *info; + struct device *cpu_dev; struct dev_pm_opp *opp; long freq_hz, pre_freq_hz; int vproc, pre_vproc, inter_vproc, target_vproc, ret; @@ -213,6 +213,11 @@ static int mtk_cpufreq_set_target(struct cpufreq_polic= y *policy, =20 mutex_lock(&mtk_policy_lock); =20 + freq_table =3D policy->freq_table; + cpu_clk =3D policy->clk; + armpll =3D clk_get_parent(cpu_clk); + info =3D policy->driver_data; + cpu_dev =3D info->cpu_dev; inter_vproc =3D info->intermediate_voltage; pre_freq_hz =3D policy->cur * 1000; =20 --=20 2.45.2