From nobody Sun Nov 24 05:54:35 2024 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 102D213CF82 for ; Fri, 8 Nov 2024 04:09:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038988; cv=none; b=GffubMBc0ysVu/eaPUnJO4l5cDytf9WUCz5q2i+MtaXCZoyCYybWXpPMKZCZMFYYqAgN5eQgpMyuVA9bdon0eu7V3lU3vcWc0nqWMpPQyy32QupVsnSt7NZHiL35xk0f7S6JDu9/25gjxad9ORrl1IklAaVvt6MtaWC/RUYfGII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038988; c=relaxed/simple; bh=obyV78oUjWVeKRdPHEazO9TW3s8naiInq747cCOT01Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Lm6gqIubcuLm+KPT4B0HxxstmHKn7TGQcz4a0XRQrzBucw7qYDRFWM2fILD56waqDUAoH6tpAFc89i32M+A4IZ9p5i38fuaQp9vnNacFbK1jKe2oDYTO303AuZkoOMPw0SP640UeVsdJUbjIBfuvvzctoGVtHsOVIUjS0HDxoUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=N1EKDyUO; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="N1EKDyUO" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MbeZ8022679; Thu, 7 Nov 2024 20:07:32 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=2 vBA9/YIjtC9NXvu1JNHv6kTYHCKQnYXVoCmc4mw7mw=; b=N1EKDyUO5i393bkRi 8nYFezF17Ifsr9oQ3mahp2e1uZdflglCAz5elBGa1yfiG9q/8BMr4JxMXQZNnSC2 UUYvHogG0K8Kv98jnxecj2CKzMHKzf1j+yyIUNLL0X+ITTfBhqCOScoxxqGyxemT hkOPv2yj63masvHiE3DnN2Wr9P2uj6yztPmjoda2NJlgKp4CcE6iwAeeaFBMUBSP +Zr/86Up59zOi7qgRW07rvO6WsukemJR4HWTo8SCjCC0kY3XmIdxQ91d+P+Ml6jo nwq1c9jjA5cy3ZB/HQRXJf7oibJ9is+QWeFBzDt7BAjB2QTQ/c0NjexwvXuq9Fqj l8gvg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42s6gu8m2q-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 20:07:31 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 20:06:46 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 20:06:46 -0800 Received: from IPBU-BLR-SERVER1.marvell.com (IPBU-BLR-SERVER1.marvell.com [10.28.8.41]) by maili.marvell.com (Postfix) with ESMTP id 958F05B6926; Thu, 7 Nov 2024 20:06:43 -0800 (PST) From: Gowthami Thiagarajan To: , , , CC: , , , , Gowthami Thiagarajan Subject: [PATCH v10 5/5] perf/marvell : Odyssey LLC-TAD performance monitor support Date: Fri, 8 Nov 2024 09:36:19 +0530 Message-ID: <20241108040619.753343-6-gthiagarajan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241108040619.753343-1-gthiagarajan@marvell.com> References: <20241108040619.753343-1-gthiagarajan@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: IDRVywGm_Ra8IZHu8LtpM_G_u9d_UC4S X-Proofpoint-GUID: IDRVywGm_Ra8IZHu8LtpM_G_u9d_UC4S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" Each TAD provides eight 64-bit counters for monitoring cache behavior.The driver always configures the same counter for all the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of running the workload. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications. The performance events reflect various internal or interface activities. By combining the values from multiple performance counters, cache performance can be measured in terms such as: cache miss rate, cache allocations, interface retry rate, internal resource occupancy, etc. Each supported counter's event and formatting information is exposed to sysfs at /sys/devices/tad/. Use perf tool stat command to measure the pmu events. For instance: perf stat -e tad_hit_ltg,tad_hit_dtg Signed-off-by: Gowthami Thiagarajan --- Documentation/admin-guide/perf/index.rst | 1 + .../admin-guide/perf/mrvl-odyssey-tad-pmu.rst | 37 +++++++++++++++++++ drivers/perf/marvell_cn10k_tad_pmu.c | 35 ++++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100644 Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index f9be610b2e6d..0aecdc3e4efa 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -15,6 +15,7 @@ Performance monitor support qcom_l3_pmu starfive_starlink_pmu mrvl-odyssey-ddr-pmu + mrvl-odyssey-tad-pmu arm-ccn arm-cmn arm-ni diff --git a/Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst b/Docu= mentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst new file mode 100644 index 000000000000..ad1975b14087 --- /dev/null +++ b/Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst @@ -0,0 +1,37 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Marvell Odyssey LLC-TAD Performance Monitoring Unit (PMU UNCORE) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Each TAD provides eight 64-bit counters for monitoring +cache behavior.The driver always configures the same counter for +all the TADs. The user would end up effectively reserving one of +eight counters in every TAD to look across all TADs. +The occurrences of events are aggregated and presented to the user +at the end of running the workload. The driver does not provide a +way for the user to partition TADs so that different TADs are used for +different applications. + +The performance events reflect various internal or interface activities. +By combining the values from multiple performance counters, cache +performance can be measured in terms such as: cache miss rate, cache +allocations, interface retry rate, internal resource occupancy, etc. + +The PMU driver exposes the available events and format options under sysfs= :: + + /sys/bus/event_source/devices/tad/events/ + /sys/bus/event_source/devices/tad/format/ + +Examples:: + + $ perf list | grep tad + tad/tad_alloc_any/ [Kernel PMU eve= nt] + tad/tad_alloc_dtg/ [Kernel PMU eve= nt] + tad/tad_alloc_ltg/ [Kernel PMU eve= nt] + tad/tad_hit_any/ [Kernel PMU eve= nt] + tad/tad_hit_dtg/ [Kernel PMU eve= nt] + tad/tad_hit_ltg/ [Kernel PMU eve= nt] + tad/tad_req_msh_in_exlmn/ [Kernel PMU eve= nt] + tad/tad_tag_rd/ [Kernel PMU eve= nt] + tad/tad_tot_cycle/ [Kernel PMU eve= nt] + + $ perf stat -e tad_alloc_dtg,tad_alloc_ltg,tad_alloc_any,tad_hit_dtg,ta= d_hit_ltg,tad_hit_any,tad_tag_rd diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index 15f9f67cb3bd..29976b435417 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -39,6 +39,7 @@ struct tad_pmu { =20 enum mrvl_tad_pmu_version { TAD_PMU_V1 =3D 1, + TAD_PMU_V2, }; =20 struct tad_pmu_data { @@ -222,6 +223,24 @@ static const struct attribute_group tad_pmu_events_att= r_group =3D { .attrs =3D tad_pmu_event_attrs, }; =20 +static struct attribute *ody_tad_pmu_event_attrs[] =3D { + TAD_PMU_EVENT_ATTR(tad_req_msh_in_exlmn, 0x3), + TAD_PMU_EVENT_ATTR(tad_alloc_dtg, 0x1a), + TAD_PMU_EVENT_ATTR(tad_alloc_ltg, 0x1b), + TAD_PMU_EVENT_ATTR(tad_alloc_any, 0x1c), + TAD_PMU_EVENT_ATTR(tad_hit_dtg, 0x1d), + TAD_PMU_EVENT_ATTR(tad_hit_ltg, 0x1e), + TAD_PMU_EVENT_ATTR(tad_hit_any, 0x1f), + TAD_PMU_EVENT_ATTR(tad_tag_rd, 0x20), + TAD_PMU_EVENT_ATTR(tad_tot_cycle, 0xFF), + NULL +}; + +static const struct attribute_group ody_tad_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D ody_tad_pmu_event_attrs, +}; + PMU_FORMAT_ATTR(event, "config:0-7"); =20 static struct attribute *tad_pmu_format_attrs[] =3D { @@ -260,6 +279,13 @@ static const struct attribute_group *tad_pmu_attr_grou= ps[] =3D { NULL }; =20 +static const struct attribute_group *ody_tad_pmu_attr_groups[] =3D { + &ody_tad_pmu_events_attr_group, + &tad_pmu_format_attr_group, + &tad_pmu_cpumask_attr_group, + NULL +}; + static int tad_pmu_probe(struct platform_device *pdev) { const struct tad_pmu_data *dev_data; @@ -350,6 +376,8 @@ static int tad_pmu_probe(struct platform_device *pdev) =20 if (version =3D=3D TAD_PMU_V1) tad_pmu->pmu.attr_groups =3D tad_pmu_attr_groups; + else + tad_pmu->pmu.attr_groups =3D ody_tad_pmu_attr_groups; =20 tad_pmu->cpu =3D raw_smp_processor_id(); =20 @@ -385,6 +413,12 @@ static const struct tad_pmu_data tad_pmu_data =3D { }; #endif =20 +#ifdef CONFIG_ACPI +static const struct tad_pmu_data tad_pmu_v2_data =3D { + .id =3D TAD_PMU_V2, +}; +#endif + #ifdef CONFIG_OF static const struct of_device_id tad_pmu_of_match[] =3D { { .compatible =3D "marvell,cn10k-tad-pmu", .data =3D &tad_pmu_data }, @@ -395,6 +429,7 @@ static const struct of_device_id tad_pmu_of_match[] =3D= { #ifdef CONFIG_ACPI static const struct acpi_device_id tad_pmu_acpi_match[] =3D { {"MRVL000B", (kernel_ulong_t)&tad_pmu_data}, + {"MRVL000D", (kernel_ulong_t)&tad_pmu_v2_data}, {}, }; MODULE_DEVICE_TABLE(acpi, tad_pmu_acpi_match); --=20 2.25.1