From nobody Sun Nov 24 02:41:08 2024 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81C523BBEA for ; Fri, 8 Nov 2024 04:09:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038988; cv=none; b=iVsDMrFo6Qq3Z0bwydrKUtGaPfvHf6z27cvic7da07jxDqMaRNq8sYTW4kF4wZ6PVAt0qIFtLa0UoiwI38R+IK5v8zfF7ogYZu+EZVKCkxf+YM0FfyIyMIR6ZPFihrOcbIqf436ukhOrbmt/BncTbQ5VWbxHEpJcgrWYQNmKwd4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038988; c=relaxed/simple; bh=CzpaGIoLqAXKYgtuG87044g0qnQbh0onVsDAmLaAVQY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SQunGu3PjpTZ/pxbhxL80FmbDX7zvBIeS/iypkihqGGFRC+DWLZLiEwwt6GUEq2HmCRInEiGFeDY6DBoY+OiK8y8TH2kLErmrqPT1w0L121LdlhBkBepI/SXdyZBsUDs9h/9hMdo+rp5MvWpZX1beI1EBIWxCqpfJoPdQvatoW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=XcopX1zj; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="XcopX1zj" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MbeZ6022679; Thu, 7 Nov 2024 20:07:32 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=o fkcuWOh8PDxhCG8cbcHxtId4AQt8wG85bsA35KSDpI=; b=XcopX1zj8wy7Rq6Yj DPr95MFLn1tfBSVMWtM6ZKADowAbOX0+2WZdKApE/6LeafzRQUEC/WsRhI/iYmJF 3HlHKyvHLA+PsR/D01YhR3ve5/XMqMmgkUCXw2t9staeyP+6glLxUoKT7sirwBYB 53Qk+ypa1AxX2yed2ZCrx7kIcnp91wcp1OVWZUJ103AMBb4aXpol9HrwF4WavLdB WwjF2wfg3nv8qvqfWxrPjxGrb9u4lVtkaBxLBO4anhhuhWutXHJbNUEyK0puhFqf Ve0i6TcO4JTkWf8kR2FckhF/LzbGNHjzkSW0xsENxeux6qOhS/ysWtC4Ugen89S3 YY67g== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42s6gu8m30-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 20:07:31 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 20:06:29 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 20:06:29 -0800 Received: from IPBU-BLR-SERVER1.marvell.com (IPBU-BLR-SERVER1.marvell.com [10.28.8.41]) by maili.marvell.com (Postfix) with ESMTP id D7B525B6926; Thu, 7 Nov 2024 20:06:26 -0800 (PST) From: Gowthami Thiagarajan To: , , , CC: , , , , Gowthami Thiagarajan Subject: [PATCH v10 1/5] perf/marvell: Refactor to extract platform data - no functional change Date: Fri, 8 Nov 2024 09:36:15 +0530 Message-ID: <20241108040619.753343-2-gthiagarajan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241108040619.753343-1-gthiagarajan@marvell.com> References: <20241108040619.753343-1-gthiagarajan@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: zJ3fjDKT7iVRG8VWeo3HHqGmaN3cmjFt X-Proofpoint-GUID: zJ3fjDKT7iVRG8VWeo3HHqGmaN3cmjFt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" Introduce a refactor to the Marvell DDR pmu driver to extract platform data ("pdata") from the existing driver. Prepare for the upcoming support of the next version of the Performance Monitoring Unit (PMU) in this driver. Make no functional changes, this refactor solely improves code organization and prepares for future enhancements. While at it, fix a typo. Signed-off-by: Gowthami Thiagarajan --- drivers/perf/marvell_cn10k_ddr_pmu.c | 162 +++++++++++++++++++-------- 1 file changed, 113 insertions(+), 49 deletions(-) diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn= 10k_ddr_pmu.c index 94f1ebcd2a27..efac4cef4050 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -/* Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver +/* + * Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver * - * Copyright (C) 2021 Marvell. + * Copyright (C) 2021-2024 Marvell. */ =20 #include @@ -14,24 +15,24 @@ #include =20 /* Performance Counters Operating Mode Control Registers */ -#define DDRC_PERF_CNT_OP_MODE_CTRL 0x8020 -#define OP_MODE_CTRL_VAL_MANNUAL 0x1 +#define CN10K_DDRC_PERF_CNT_OP_MODE_CTRL 0x8020 +#define OP_MODE_CTRL_VAL_MANUAL 0x1 =20 /* Performance Counters Start Operation Control Registers */ -#define DDRC_PERF_CNT_START_OP_CTRL 0x8028 +#define CN10K_DDRC_PERF_CNT_START_OP_CTRL 0x8028 #define START_OP_CTRL_VAL_START 0x1ULL #define START_OP_CTRL_VAL_ACTIVE 0x2 =20 /* Performance Counters End Operation Control Registers */ -#define DDRC_PERF_CNT_END_OP_CTRL 0x8030 +#define CN10K_DDRC_PERF_CNT_END_OP_CTRL 0x8030 #define END_OP_CTRL_VAL_END 0x1ULL =20 /* Performance Counters End Status Registers */ -#define DDRC_PERF_CNT_END_STATUS 0x8038 +#define CN10K_DDRC_PERF_CNT_END_STATUS 0x8038 #define END_STATUS_VAL_END_TIMER_MODE_END 0x1 =20 /* Performance Counters Configuration Registers */ -#define DDRC_PERF_CFG_BASE 0x8040 +#define CN10K_DDRC_PERF_CFG_BASE 0x8040 =20 /* 8 Generic event counter + 2 fixed event counters */ #define DDRC_PERF_NUM_GEN_COUNTERS 8 @@ -42,13 +43,14 @@ DDRC_PERF_NUM_FIX_COUNTERS) =20 /* Generic event counter registers */ -#define DDRC_PERF_CFG(n) (DDRC_PERF_CFG_BASE + 8 * (n)) +#define DDRC_PERF_CFG(base, n) ((base) + 8 * (n)) #define EVENT_ENABLE BIT_ULL(63) =20 /* Two dedicated event counters for DDR reads and writes */ #define EVENT_DDR_READS 101 #define EVENT_DDR_WRITES 100 =20 +#define DDRC_PERF_REG(base, n) ((base) + 8 * (n)) /* * programmable events IDs in programmable event counters. * DO NOT change these event-id numbers, they are used to @@ -102,28 +104,29 @@ #define EVENT_HIF_RD_OR_WR 1 =20 /* Event counter value registers */ -#define DDRC_PERF_CNT_VALUE_BASE 0x8080 -#define DDRC_PERF_CNT_VALUE(n) (DDRC_PERF_CNT_VALUE_BASE + 8 * (n)) +#define CN10K_DDRC_PERF_CNT_VALUE_BASE 0x8080 =20 /* Fixed event counter enable/disable register */ -#define DDRC_PERF_CNT_FREERUN_EN 0x80C0 +#define CN10K_DDRC_PERF_CNT_FREERUN_EN 0x80C0 #define DDRC_PERF_FREERUN_WRITE_EN 0x1 #define DDRC_PERF_FREERUN_READ_EN 0x2 =20 /* Fixed event counter control register */ -#define DDRC_PERF_CNT_FREERUN_CTRL 0x80C8 +#define CN10K_DDRC_PERF_CNT_FREERUN_CTRL 0x80C8 #define DDRC_FREERUN_WRITE_CNT_CLR 0x1 #define DDRC_FREERUN_READ_CNT_CLR 0x2 =20 -/* Fixed event counter value register */ -#define DDRC_PERF_CNT_VALUE_WR_OP 0x80D0 -#define DDRC_PERF_CNT_VALUE_RD_OP 0x80D8 #define DDRC_PERF_CNT_VALUE_OVERFLOW BIT_ULL(48) #define DDRC_PERF_CNT_MAX_VALUE GENMASK_ULL(48, 0) =20 +/* Fixed event counter value register */ +#define CN10K_DDRC_PERF_CNT_VALUE_WR_OP 0x80D0 +#define CN10K_DDRC_PERF_CNT_VALUE_RD_OP 0x80D8 + struct cn10k_ddr_pmu { struct pmu pmu; void __iomem *base; + const struct ddr_pmu_platform_data *p_data; unsigned int cpu; struct device *dev; int active_events; @@ -134,6 +137,23 @@ struct cn10k_ddr_pmu { =20 #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu) =20 +struct ddr_pmu_platform_data { + u64 counter_overflow_val; + u64 counter_max_val; + u64 cnt_base; + u64 cfg_base; + u64 cnt_op_mode_ctrl; + u64 cnt_start_op_ctrl; + u64 cnt_end_op_ctrl; + u64 cnt_end_status; + u64 cnt_freerun_en; + u64 cnt_freerun_ctrl; + u64 cnt_freerun_clr; + u64 cnt_value_wr_op; + u64 cnt_value_rd_op; + bool is_cn10k; +}; + static ssize_t cn10k_ddr_pmu_event_show(struct device *dev, struct device_attribute *attr, char *page) @@ -354,6 +374,7 @@ static int cn10k_ddr_perf_event_init(struct perf_event = *event) static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu, int counter, bool enable) { + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; u32 reg; u64 val; =20 @@ -363,7 +384,7 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_= ddr_pmu *pmu, } =20 if (counter < DDRC_PERF_NUM_GEN_COUNTERS) { - reg =3D DDRC_PERF_CFG(counter); + reg =3D DDRC_PERF_CFG(p_data->cfg_base, counter); val =3D readq_relaxed(pmu->base + reg); =20 if (enable) @@ -373,7 +394,8 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_= ddr_pmu *pmu, =20 writeq_relaxed(val, pmu->base + reg); } else { - val =3D readq_relaxed(pmu->base + DDRC_PERF_CNT_FREERUN_EN); + val =3D readq_relaxed(pmu->base + + p_data->cnt_freerun_en); if (enable) { if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) val |=3D DDRC_PERF_FREERUN_READ_EN; @@ -385,27 +407,33 @@ static void cn10k_ddr_perf_counter_enable(struct cn10= k_ddr_pmu *pmu, else val &=3D ~DDRC_PERF_FREERUN_WRITE_EN; } - writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_EN); + writeq_relaxed(val, pmu->base + + p_data->cnt_freerun_en); } } =20 static u64 cn10k_ddr_perf_read_counter(struct cn10k_ddr_pmu *pmu, int coun= ter) { + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; u64 val; =20 if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) - return readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE_RD_OP); + return readq_relaxed(pmu->base + + p_data->cnt_value_rd_op); =20 if (counter =3D=3D DDRC_PERF_WRITE_COUNTER_IDX) - return readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE_WR_OP); + return readq_relaxed(pmu->base + + p_data->cnt_value_wr_op); =20 - val =3D readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE(counter)); + val =3D readq_relaxed(pmu->base + + DDRC_PERF_REG(p_data->cnt_base, counter)); return val; } =20 static void cn10k_ddr_perf_event_update(struct perf_event *event) { struct cn10k_ddr_pmu *pmu =3D to_cn10k_ddr_pmu(event->pmu); + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; struct hw_perf_event *hwc =3D &event->hw; u64 prev_count, new_count, mask; =20 @@ -414,7 +442,7 @@ static void cn10k_ddr_perf_event_update(struct perf_eve= nt *event) new_count =3D cn10k_ddr_perf_read_counter(pmu, hwc->idx); } while (local64_xchg(&hwc->prev_count, new_count) !=3D prev_count); =20 - mask =3D DDRC_PERF_CNT_MAX_VALUE; + mask =3D p_data->counter_max_val; =20 local64_add((new_count - prev_count) & mask, &event->count); } @@ -435,6 +463,7 @@ static void cn10k_ddr_perf_event_start(struct perf_even= t *event, int flags) static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags) { struct cn10k_ddr_pmu *pmu =3D to_cn10k_ddr_pmu(event->pmu); + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; struct hw_perf_event *hwc =3D &event->hw; u8 config =3D event->attr.config; int counter, ret; @@ -454,7 +483,7 @@ static int cn10k_ddr_perf_event_add(struct perf_event *= event, int flags) =20 if (counter < DDRC_PERF_NUM_GEN_COUNTERS) { /* Generic counters, configure event id */ - reg_offset =3D DDRC_PERF_CFG(counter); + reg_offset =3D DDRC_PERF_CFG(p_data->cfg_base, counter); ret =3D ddr_perf_get_event_bitmap(config, &val); if (ret) return ret; @@ -467,7 +496,7 @@ static int cn10k_ddr_perf_event_add(struct perf_event *= event, int flags) else val =3D DDRC_FREERUN_WRITE_CNT_CLR; =20 - writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_CTRL); + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl); } =20 hwc->state |=3D PERF_HES_STOPPED; @@ -512,17 +541,19 @@ static void cn10k_ddr_perf_event_del(struct perf_even= t *event, int flags) static void cn10k_ddr_perf_pmu_enable(struct pmu *pmu) { struct cn10k_ddr_pmu *ddr_pmu =3D to_cn10k_ddr_pmu(pmu); + const struct ddr_pmu_platform_data *p_data =3D ddr_pmu->p_data; =20 writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base + - DDRC_PERF_CNT_START_OP_CTRL); + p_data->cnt_start_op_ctrl); } =20 static void cn10k_ddr_perf_pmu_disable(struct pmu *pmu) { struct cn10k_ddr_pmu *ddr_pmu =3D to_cn10k_ddr_pmu(pmu); + const struct ddr_pmu_platform_data *p_data =3D ddr_pmu->p_data; =20 writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base + - DDRC_PERF_CNT_END_OP_CTRL); + p_data->cnt_end_op_ctrl); } =20 static void cn10k_ddr_perf_event_update_all(struct cn10k_ddr_pmu *pmu) @@ -549,6 +580,7 @@ static void cn10k_ddr_perf_event_update_all(struct cn10= k_ddr_pmu *pmu) =20 static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pm= u) { + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; struct perf_event *event; struct hw_perf_event *hwc; u64 prev_count, new_count; @@ -586,7 +618,7 @@ static irqreturn_t cn10k_ddr_pmu_overflow_handler(struc= t cn10k_ddr_pmu *pmu) continue; =20 value =3D cn10k_ddr_perf_read_counter(pmu, i); - if (value =3D=3D DDRC_PERF_CNT_MAX_VALUE) { + if (value =3D=3D p_data->counter_max_val) { pr_info("Counter-(%d) reached max value\n", i); cn10k_ddr_perf_event_update_all(pmu); cn10k_ddr_perf_pmu_disable(&pmu->pmu); @@ -629,11 +661,32 @@ static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu= , struct hlist_node *node) return 0; } =20 +#if defined(CONFIG_ACPI) || defined(CONFIG_OF) +static const struct ddr_pmu_platform_data cn10k_ddr_pmu_pdata =3D { + .counter_overflow_val =3D BIT_ULL(48), + .counter_max_val =3D GENMASK_ULL(48, 0), + .cnt_base =3D CN10K_DDRC_PERF_CNT_VALUE_BASE, + .cfg_base =3D CN10K_DDRC_PERF_CFG_BASE, + .cnt_op_mode_ctrl =3D CN10K_DDRC_PERF_CNT_OP_MODE_CTRL, + .cnt_start_op_ctrl =3D CN10K_DDRC_PERF_CNT_START_OP_CTRL, + .cnt_end_op_ctrl =3D CN10K_DDRC_PERF_CNT_END_OP_CTRL, + .cnt_end_status =3D CN10K_DDRC_PERF_CNT_END_STATUS, + .cnt_freerun_en =3D CN10K_DDRC_PERF_CNT_FREERUN_EN, + .cnt_freerun_ctrl =3D CN10K_DDRC_PERF_CNT_FREERUN_CTRL, + .cnt_freerun_clr =3D 0, + .cnt_value_wr_op =3D CN10K_DDRC_PERF_CNT_VALUE_WR_OP, + .cnt_value_rd_op =3D CN10K_DDRC_PERF_CNT_VALUE_RD_OP, + .is_cn10k =3D TRUE, +}; +#endif + static int cn10k_ddr_perf_probe(struct platform_device *pdev) { + const struct ddr_pmu_platform_data *dev_data; struct cn10k_ddr_pmu *ddr_pmu; struct resource *res; void __iomem *base; + bool is_cn10k; char *name; int ret; =20 @@ -644,30 +697,41 @@ static int cn10k_ddr_perf_probe(struct platform_devic= e *pdev) ddr_pmu->dev =3D &pdev->dev; platform_set_drvdata(pdev, ddr_pmu); =20 + dev_data =3D device_get_match_data(&pdev->dev); + if (!dev_data) { + dev_err(&pdev->dev, "Error: No device match data found\n"); + return -ENODEV; + } + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); =20 ddr_pmu->base =3D base; =20 - /* Setup the PMU counter to work in manual mode */ - writeq_relaxed(OP_MODE_CTRL_VAL_MANNUAL, ddr_pmu->base + - DDRC_PERF_CNT_OP_MODE_CTRL); - - ddr_pmu->pmu =3D (struct pmu) { - .module =3D THIS_MODULE, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, - .task_ctx_nr =3D perf_invalid_context, - .attr_groups =3D cn10k_attr_groups, - .event_init =3D cn10k_ddr_perf_event_init, - .add =3D cn10k_ddr_perf_event_add, - .del =3D cn10k_ddr_perf_event_del, - .start =3D cn10k_ddr_perf_event_start, - .stop =3D cn10k_ddr_perf_event_stop, - .read =3D cn10k_ddr_perf_event_update, - .pmu_enable =3D cn10k_ddr_perf_pmu_enable, - .pmu_disable =3D cn10k_ddr_perf_pmu_disable, - }; + ddr_pmu->p_data =3D dev_data; + is_cn10k =3D ddr_pmu->p_data->is_cn10k; + + if (is_cn10k) { + /* Setup the PMU counter to work in manual mode */ + writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base + + ddr_pmu->p_data->cnt_op_mode_ctrl); + + ddr_pmu->pmu =3D (struct pmu) { + .module =3D THIS_MODULE, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr =3D perf_invalid_context, + .attr_groups =3D cn10k_attr_groups, + .event_init =3D cn10k_ddr_perf_event_init, + .add =3D cn10k_ddr_perf_event_add, + .del =3D cn10k_ddr_perf_event_del, + .start =3D cn10k_ddr_perf_event_start, + .stop =3D cn10k_ddr_perf_event_stop, + .read =3D cn10k_ddr_perf_event_update, + .pmu_enable =3D cn10k_ddr_perf_pmu_enable, + .pmu_disable =3D cn10k_ddr_perf_pmu_disable, + }; + } =20 /* Choose this cpu to collect perf data */ ddr_pmu->cpu =3D raw_smp_processor_id(); @@ -688,7 +752,7 @@ static int cn10k_ddr_perf_probe(struct platform_device = *pdev) if (ret) goto error; =20 - pr_info("CN10K DDR PMU Driver for ddrc@%llx\n", res->start); + pr_info("DDR PMU Driver for ddrc@%llx\n", res->start); return 0; error: cpuhp_state_remove_instance_nocalls( @@ -710,7 +774,7 @@ static void cn10k_ddr_perf_remove(struct platform_devic= e *pdev) =20 #ifdef CONFIG_OF static const struct of_device_id cn10k_ddr_pmu_of_match[] =3D { - { .compatible =3D "marvell,cn10k-ddr-pmu", }, + { .compatible =3D "marvell,cn10k-ddr-pmu", .data =3D &cn10k_ddr_pmu_pdata= }, { }, }; MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); @@ -718,7 +782,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); =20 #ifdef CONFIG_ACPI static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] =3D { - {"MRVL000A", 0}, + {"MRVL000A", (kernel_ulong_t)&cn10k_ddr_pmu_pdata }, {}, }; MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match); --=20 2.25.1 From nobody Sun Nov 24 02:41:08 2024 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8262C3BBEA for ; Fri, 8 Nov 2024 04:07:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038869; cv=none; b=LiWvL86vEQa78qOiSdZ+IrBnh1TNf0gpdYKEWuaq5jv8dKuDM8eCXcemkkIkZ0Ryg2KERYNFCj8Pt6BbWsU4x+mU+Uo2AK4iYQhXNHFp7luj6f8DyVYIkYJQroX1JvD5gqmgnTzpQXZq7wRnSvnlII6c+RxQW0PiK6FXYtVYvfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038869; c=relaxed/simple; bh=E4KcD6sj5fX2nQMQbXYww0kcWWe1VrmTl1dUMbkqiE8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VaLxshtFoywM2dKF3GcF1Zr9eWVzG680LGgh5r4OrZ1Au8YRxevc0m3CfyGoaAQTeP7naD1jkO+Lhvx6dIxwR2KrF8LkLFzogAI6hxS/+Ne+vBRplllLpp2JsRlewadm6QFpDvsu7h/tboSaQL76rfRLVocJx2miyX7euWRYRV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=MkczBdxh; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="MkczBdxh" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MbeZC022679; Thu, 7 Nov 2024 20:07:33 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=o V9fg5QbZH9KY2cVOi3dNLkO7JfK17uh2ZE8AgYK5wU=; b=MkczBdxhigXHZbdmF ml+7Iv2VpDReouMbkwSC/dat277pA5pNRgOxdll/0NRVJHizsJCeIOVdBvMXIFWP prMR7quL/gDPBd8TJnhe/qWPW5F8zdtBVNsjeefKDxtu0ZUHr3fxsdcwTMfnJ1TY hd/t5JNifIE2tr6vAAsbfF7qLu6Jf5tpn82fzhwJC0OENNqOIz9DyIgWdxmcnrH0 Pv0EQFcYT68nzKryUAySk1I6paQvr5qqqnZVjcVvr1lxzCmvJrhlP/1PWEr3DWuR C6Am7jcczJZv2/bJW262nmgECPvXJTCC3HXzDuLuYmaw1ysgp/COo1QtDxT6LjsN i691w== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42s6gu8m30-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 20:07:33 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 20:06:33 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 20:06:33 -0800 Received: from IPBU-BLR-SERVER1.marvell.com (IPBU-BLR-SERVER1.marvell.com [10.28.8.41]) by maili.marvell.com (Postfix) with ESMTP id D47F85B6926; Thu, 7 Nov 2024 20:06:30 -0800 (PST) From: Gowthami Thiagarajan To: , , , CC: , , , , Gowthami Thiagarajan , Jonathan Cameron Subject: [PATCH v10 2/5] perf/marvell: Refactor to extract PMU operations Date: Fri, 8 Nov 2024 09:36:16 +0530 Message-ID: <20241108040619.753343-3-gthiagarajan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241108040619.753343-1-gthiagarajan@marvell.com> References: <20241108040619.753343-1-gthiagarajan@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: R-2qhBaiz9FH0SJBfb2QkEE3Xwqvix_V X-Proofpoint-GUID: R-2qhBaiz9FH0SJBfb2QkEE3Xwqvix_V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" Introduce a refactor to the Marvell DDR PMU driver to extract PMU operations ("pmu ops") from the existing driver. Reviewed-by: Jonathan Cameron Signed-off-by: Gowthami Thiagarajan --- drivers/perf/marvell_cn10k_ddr_pmu.c | 105 +++++++++++++++++++++------ 1 file changed, 83 insertions(+), 22 deletions(-) diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn= 10k_ddr_pmu.c index efac4cef4050..45da37e702a2 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -127,6 +127,7 @@ struct cn10k_ddr_pmu { struct pmu pmu; void __iomem *base; const struct ddr_pmu_platform_data *p_data; + const struct ddr_pmu_ops *ops; unsigned int cpu; struct device *dev; int active_events; @@ -135,6 +136,16 @@ struct cn10k_ddr_pmu { struct hlist_node node; }; =20 +struct ddr_pmu_ops { + void (*enable_read_freerun_counter)(struct cn10k_ddr_pmu *pmu, + bool enable); + void (*enable_write_freerun_counter)(struct cn10k_ddr_pmu *pmu, + bool enable); + void (*clear_read_freerun_counter)(struct cn10k_ddr_pmu *pmu); + void (*clear_write_freerun_counter)(struct cn10k_ddr_pmu *pmu); + void (*pmu_overflow_handler)(struct cn10k_ddr_pmu *pmu, int evt_idx); +}; + #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu) =20 struct ddr_pmu_platform_data { @@ -375,6 +386,7 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_= ddr_pmu *pmu, int counter, bool enable) { const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + const struct ddr_pmu_ops *ops =3D pmu->ops; u32 reg; u64 val; =20 @@ -394,21 +406,10 @@ static void cn10k_ddr_perf_counter_enable(struct cn10= k_ddr_pmu *pmu, =20 writeq_relaxed(val, pmu->base + reg); } else { - val =3D readq_relaxed(pmu->base + - p_data->cnt_freerun_en); - if (enable) { - if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) - val |=3D DDRC_PERF_FREERUN_READ_EN; - else - val |=3D DDRC_PERF_FREERUN_WRITE_EN; - } else { - if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) - val &=3D ~DDRC_PERF_FREERUN_READ_EN; - else - val &=3D ~DDRC_PERF_FREERUN_WRITE_EN; - } - writeq_relaxed(val, pmu->base + - p_data->cnt_freerun_en); + if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) + ops->enable_read_freerun_counter(pmu, enable); + else + ops->enable_write_freerun_counter(pmu, enable); } } =20 @@ -464,6 +465,7 @@ static int cn10k_ddr_perf_event_add(struct perf_event *= event, int flags) { struct cn10k_ddr_pmu *pmu =3D to_cn10k_ddr_pmu(event->pmu); const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + const struct ddr_pmu_ops *ops =3D pmu->ops; struct hw_perf_event *hwc =3D &event->hw; u8 config =3D event->attr.config; int counter, ret; @@ -492,11 +494,9 @@ static int cn10k_ddr_perf_event_add(struct perf_event = *event, int flags) } else { /* fixed event counter, clear counter value */ if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) - val =3D DDRC_FREERUN_READ_CNT_CLR; + ops->clear_read_freerun_counter(pmu); else - val =3D DDRC_FREERUN_WRITE_CNT_CLR; - - writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl); + ops->clear_write_freerun_counter(pmu); } =20 hwc->state |=3D PERF_HES_STOPPED; @@ -578,9 +578,63 @@ static void cn10k_ddr_perf_event_update_all(struct cn1= 0k_ddr_pmu *pmu) } } =20 +static void ddr_pmu_enable_read_freerun(struct cn10k_ddr_pmu *pmu, bool en= able) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D readq_relaxed(pmu->base + p_data->cnt_freerun_en); + if (enable) + val |=3D DDRC_PERF_FREERUN_READ_EN; + else + val &=3D ~DDRC_PERF_FREERUN_READ_EN; + + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_en); +} + +static void ddr_pmu_enable_write_freerun(struct cn10k_ddr_pmu *pmu, bool e= nable) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D readq_relaxed(pmu->base + p_data->cnt_freerun_en); + if (enable) + val |=3D DDRC_PERF_FREERUN_WRITE_EN; + else + val &=3D ~DDRC_PERF_FREERUN_WRITE_EN; + + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_en); +} + +static void ddr_pmu_read_clear_freerun(struct cn10k_ddr_pmu *pmu) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D DDRC_FREERUN_READ_CNT_CLR; + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl); +} + +static void ddr_pmu_write_clear_freerun(struct cn10k_ddr_pmu *pmu) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D DDRC_FREERUN_WRITE_CNT_CLR; + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl); +} + +static void ddr_pmu_overflow_hander(struct cn10k_ddr_pmu *pmu, int evt_idx) +{ + cn10k_ddr_perf_event_update_all(pmu); + cn10k_ddr_perf_pmu_disable(&pmu->pmu); + cn10k_ddr_perf_pmu_enable(&pmu->pmu); +} + static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pm= u) { const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + const struct ddr_pmu_ops *ops =3D pmu->ops; struct perf_event *event; struct hw_perf_event *hwc; u64 prev_count, new_count; @@ -620,9 +674,7 @@ static irqreturn_t cn10k_ddr_pmu_overflow_handler(struc= t cn10k_ddr_pmu *pmu) value =3D cn10k_ddr_perf_read_counter(pmu, i); if (value =3D=3D p_data->counter_max_val) { pr_info("Counter-(%d) reached max value\n", i); - cn10k_ddr_perf_event_update_all(pmu); - cn10k_ddr_perf_pmu_disable(&pmu->pmu); - cn10k_ddr_perf_pmu_enable(&pmu->pmu); + ops->pmu_overflow_handler(pmu, i); } } =20 @@ -661,6 +713,14 @@ static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu,= struct hlist_node *node) return 0; } =20 +static const struct ddr_pmu_ops ddr_pmu_ops =3D { + .enable_read_freerun_counter =3D ddr_pmu_enable_read_freerun, + .enable_write_freerun_counter =3D ddr_pmu_enable_write_freerun, + .clear_read_freerun_counter =3D ddr_pmu_read_clear_freerun, + .clear_write_freerun_counter =3D ddr_pmu_write_clear_freerun, + .pmu_overflow_handler =3D ddr_pmu_overflow_hander, +}; + #if defined(CONFIG_ACPI) || defined(CONFIG_OF) static const struct ddr_pmu_platform_data cn10k_ddr_pmu_pdata =3D { .counter_overflow_val =3D BIT_ULL(48), @@ -713,6 +773,7 @@ static int cn10k_ddr_perf_probe(struct platform_device = *pdev) is_cn10k =3D ddr_pmu->p_data->is_cn10k; =20 if (is_cn10k) { + ddr_pmu->ops =3D &ddr_pmu_ops; /* Setup the PMU counter to work in manual mode */ writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base + ddr_pmu->p_data->cnt_op_mode_ctrl); --=20 2.25.1 From nobody Sun Nov 24 02:41:08 2024 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D16254962C for ; Fri, 8 Nov 2024 04:07:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038869; cv=none; b=l5TAQMlwHprkjtTaP7LXZkgyw0WqY0/gTYA6ltForpH2SgyrfTK/KopCXPD7iM7foMwy1WShgudjEpqcjj/0x+0qu5Tb+Ff7pO8pU4HR2MIU4HMv9QjYbNJQsaaPsB63oPJ/vi9d15P3N44jnLI5oZ4xQoNfL9jBkeKY3GFdWBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038869; c=relaxed/simple; bh=eFd37pcj2aOE3wcO0t7ugBichuuYPkWVr5V59XKmnn4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pGo2rQmt/tZjLmiCRZJOBhRGGNBYFAVjmDR3vDihFJea0ii13yfm9EPFDzj9QVH5Bak1YQ1flwhml8pfo6EMe6JDdWRaYe5ainYp6H+vRJ3enoDmoms5ILXaNsuqAqWXySPQt6tDwQJGGhDpNyqDfDLpw3sbH9lR8bS+MBqRZ5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=bjEN4Ug+; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="bjEN4Ug+" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MbeZ5022679; Thu, 7 Nov 2024 20:07:31 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=m AtqfK18bqkWqQhnv6yYiL7WiABU3MORyiAWLFBdySI=; b=bjEN4Ug+MdbUtfse7 UkoU/WuxhgEhJGYhwDUN5dPB8Kc/sutTP8X/VqkzQ8YBveOxKnsApJ2m3JbBgiAz 5tWPUJ12E3PMdEkfpEaKCTkG9zPulFgAwNJ/Py4IP3mA5vL7J3tidFF6AwlBx2+A sNQE6yB8sfKC6yA5j9j7oVE3Ecn2GZwDA4r6jbhcVjD3kP93okFYlvs1fxAnODDn imguFJPGf/O1gHdpbLz3d0g9lBaBOk5YcCoCZnD3BctvUcCz8ymWpHaekv2IqXj1 NeQZNkov5YobDH2qZPvPquT7E2ummZQnnwXsaSAK5hbSLrJG2nzdrkZMQOusfhPn wF9MA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42s6gu8m2q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 20:07:31 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 20:06:37 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 20:06:37 -0800 Received: from IPBU-BLR-SERVER1.marvell.com (IPBU-BLR-SERVER1.marvell.com [10.28.8.41]) by maili.marvell.com (Postfix) with ESMTP id 11B3B5B6926; Thu, 7 Nov 2024 20:06:34 -0800 (PST) From: Gowthami Thiagarajan To: , , , CC: , , , , Gowthami Thiagarajan Subject: [PATCH v10 3/5] perf/marvell: Odyssey DDR Performance monitor support Date: Fri, 8 Nov 2024 09:36:17 +0530 Message-ID: <20241108040619.753343-4-gthiagarajan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241108040619.753343-1-gthiagarajan@marvell.com> References: <20241108040619.753343-1-gthiagarajan@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 6n1B4zL2lKsBr8_nF7jf3rKjRaCuAiy1 X-Proofpoint-GUID: 6n1B4zL2lKsBr8_nF7jf3rKjRaCuAiy1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" Odyssey DRAM Subsystem supports eight counters for monitoring performance and software can program those counters to monitor any of the defined performance events. Supported performance events include those counted at the interface between the DDR controller and the PHY, interface between the DDR Controller and the CHI interconnect, or within the DDR Controller. Additionally DSS also supports two fixed performance event counters, one for ddr reads and the other for ddr writes. Signed-off-by: Gowthami Thiagarajan --- Documentation/admin-guide/perf/index.rst | 1 + .../admin-guide/perf/mrvl-odyssey-ddr-pmu.rst | 80 +++++ drivers/perf/marvell_cn10k_ddr_pmu.c | 273 +++++++++++++++++- 3 files changed, 349 insertions(+), 5 deletions(-) create mode 100644 Documentation/admin-guide/perf/mrvl-odyssey-ddr-pmu.rst diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 8502bc174640..f9be610b2e6d 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -14,6 +14,7 @@ Performance monitor support qcom_l2_pmu qcom_l3_pmu starfive_starlink_pmu + mrvl-odyssey-ddr-pmu arm-ccn arm-cmn arm-ni diff --git a/Documentation/admin-guide/perf/mrvl-odyssey-ddr-pmu.rst b/Docu= mentation/admin-guide/perf/mrvl-odyssey-ddr-pmu.rst new file mode 100644 index 000000000000..2e817593a4d9 --- /dev/null +++ b/Documentation/admin-guide/perf/mrvl-odyssey-ddr-pmu.rst @@ -0,0 +1,80 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Odyssey DRAM Subsystem supports eight counters for monitoring performance +and software can program those counters to monitor any of the defined +performance events. Supported performance events include those counted +at the interface between the DDR controller and the PHY, interface between +the DDR Controller and the CHI interconnect, or within the DDR Controller. + +Additionally DSS also supports two fixed performance event counters, one +for ddr reads and the other for ddr writes. + +The counter will be operating in either manual or auto mode. + +The PMU driver exposes the available events and format options under sysfs= :: + + /sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/ + /sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/ + +Examples:: + + $ perf list | grep ddr + mrvl_ddr_pmu_<>/ddr_act_bypass_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_bsm_alloc/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_bsm_starvation/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_cam_active_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_cam_mwr/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_cam_read/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_cam_wr_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_cam_write/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_capar_error/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_crit_ref/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_ddr_reads/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_ddr_writes/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_dfi_cmd_is_retry/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_dfi_cycles/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_dfi_parity_poison/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_dfi_rd_data_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_dfi_wr_data_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_dqsosc_mpc/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_dqsosc_mrr/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_enter_mpsm/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_enter_powerdown/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_enter_selfref/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_hif_pri_rdaccess/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_hif_rd_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_hif_rd_or_wr_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_hif_rmw_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_hif_wr_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_hpri_sched_rd_crit_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_load_mode/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_lpri_sched_rd_crit_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_precharge/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_precharge_for_other/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_precharge_for_rdwr/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_raw_hazard/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_rd_bypass_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_rd_crc_error/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_rd_uc_ecc_error/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_rdwr_transitions/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_refresh/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_retry_fifo_full/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_spec_ref/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_tcr_mrr/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_war_hazard/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_waw_hazard/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_win_limit_reached_rd/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_win_limit_reached_wr/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_wr_crc_error/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_wr_trxn_crit_access/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_write_combine/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_zqcl/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_zqlatch/ [Kernel PMU event] + mrvl_ddr_pmu_<>/ddr_zqstart/ [Kernel PMU event] + + $ perf stat -e ddr_cam_read,ddr_cam_write,ddr_cam_active_access,dd= r_cam + rd_or_wr_access,ddr_cam_rd_active_access,ddr_cam_mwr diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn= 10k_ddr_pmu.c index 45da37e702a2..ee327c545472 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -16,23 +16,28 @@ =20 /* Performance Counters Operating Mode Control Registers */ #define CN10K_DDRC_PERF_CNT_OP_MODE_CTRL 0x8020 +#define ODY_DDRC_PERF_CNT_OP_MODE_CTRL 0x20020 #define OP_MODE_CTRL_VAL_MANUAL 0x1 =20 /* Performance Counters Start Operation Control Registers */ #define CN10K_DDRC_PERF_CNT_START_OP_CTRL 0x8028 +#define ODY_DDRC_PERF_CNT_START_OP_CTRL 0x200A0 #define START_OP_CTRL_VAL_START 0x1ULL #define START_OP_CTRL_VAL_ACTIVE 0x2 =20 /* Performance Counters End Operation Control Registers */ #define CN10K_DDRC_PERF_CNT_END_OP_CTRL 0x8030 +#define ODY_DDRC_PERF_CNT_END_OP_CTRL 0x200E0 #define END_OP_CTRL_VAL_END 0x1ULL =20 /* Performance Counters End Status Registers */ #define CN10K_DDRC_PERF_CNT_END_STATUS 0x8038 +#define ODY_DDRC_PERF_CNT_END_STATUS 0x20120 #define END_STATUS_VAL_END_TIMER_MODE_END 0x1 =20 /* Performance Counters Configuration Registers */ #define CN10K_DDRC_PERF_CFG_BASE 0x8040 +#define ODY_DDRC_PERF_CFG_BASE 0x20160 =20 /* 8 Generic event counter + 2 fixed event counters */ #define DDRC_PERF_NUM_GEN_COUNTERS 8 @@ -56,6 +61,15 @@ * DO NOT change these event-id numbers, they are used to * program event bitmap in h/w. */ +#define EVENT_DFI_CMD_IS_RETRY 61 +#define EVENT_RD_UC_ECC_ERROR 60 +#define EVENT_RD_CRC_ERROR 59 +#define EVENT_CAPAR_ERROR 58 +#define EVENT_WR_CRC_ERROR 57 +#define EVENT_DFI_PARITY_POISON 56 +#define EVENT_RETRY_FIFO_FULL 46 +#define EVENT_DFI_CYCLES 45 + #define EVENT_OP_IS_ZQLATCH 55 #define EVENT_OP_IS_ZQSTART 54 #define EVENT_OP_IS_TCR_MRR 53 @@ -105,6 +119,7 @@ =20 /* Event counter value registers */ #define CN10K_DDRC_PERF_CNT_VALUE_BASE 0x8080 +#define ODY_DDRC_PERF_CNT_VALUE_BASE 0x201C0 =20 /* Fixed event counter enable/disable register */ #define CN10K_DDRC_PERF_CNT_FREERUN_EN 0x80C0 @@ -113,15 +128,21 @@ =20 /* Fixed event counter control register */ #define CN10K_DDRC_PERF_CNT_FREERUN_CTRL 0x80C8 +#define ODY_DDRC_PERF_CNT_FREERUN_CTRL 0x20240 #define DDRC_FREERUN_WRITE_CNT_CLR 0x1 #define DDRC_FREERUN_READ_CNT_CLR 0x2 =20 +/* Fixed event counter clear register, defined only for Odyssey */ +#define ODY_DDRC_PERF_CNT_FREERUN_CLR 0x20248 + #define DDRC_PERF_CNT_VALUE_OVERFLOW BIT_ULL(48) #define DDRC_PERF_CNT_MAX_VALUE GENMASK_ULL(48, 0) =20 /* Fixed event counter value register */ #define CN10K_DDRC_PERF_CNT_VALUE_WR_OP 0x80D0 #define CN10K_DDRC_PERF_CNT_VALUE_RD_OP 0x80D8 +#define ODY_DDRC_PERF_CNT_VALUE_WR_OP 0x20250 +#define ODY_DDRC_PERF_CNT_VALUE_RD_OP 0x20258 =20 struct cn10k_ddr_pmu { struct pmu pmu; @@ -163,6 +184,7 @@ struct ddr_pmu_platform_data { u64 cnt_value_wr_op; u64 cnt_value_rd_op; bool is_cn10k; + bool is_ody; }; =20 static ssize_t cn10k_ddr_pmu_event_show(struct device *dev, @@ -240,6 +262,85 @@ static struct attribute *cn10k_ddr_perf_events_attrs[]= =3D { NULL }; =20 +static struct attribute *odyssey_ddr_perf_events_attrs[] =3D { + /* Programmable */ + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_or_wr_access, EVENT_HIF_RD_OR_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_wr_access, EVENT_HIF_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_access, EVENT_HIF_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rmw_access, EVENT_HIF_RMW), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_pri_rdaccess, EVENT_HIF_HI_PRI_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_bypass_access, EVENT_READ_BYPASS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_act_bypass_access, EVENT_ACT_BYPASS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_wr_data_access, + EVENT_DFI_WR_DATA_CYCLES), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_rd_data_access, + EVENT_DFI_RD_DATA_CYCLES), + CN10K_DDR_PMU_EVENT_ATTR(ddr_hpri_sched_rd_crit_access, + EVENT_HPR_XACT_WHEN_CRITICAL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_lpri_sched_rd_crit_access, + EVENT_LPR_XACT_WHEN_CRITICAL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_trxn_crit_access, + EVENT_WR_XACT_WHEN_CRITICAL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_active_access, EVENT_OP_IS_ACTIVATE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_or_wr_access, + EVENT_OP_IS_RD_OR_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_active_access, + EVENT_OP_IS_RD_ACTIVATE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_read, EVENT_OP_IS_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_write, EVENT_OP_IS_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_mwr, EVENT_OP_IS_MWR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge, EVENT_OP_IS_PRECHARGE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_rdwr, + EVENT_PRECHARGE_FOR_RDWR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_other, + EVENT_PRECHARGE_FOR_OTHER), + CN10K_DDR_PMU_EVENT_ATTR(ddr_rdwr_transitions, EVENT_RDWR_TRANSITIONS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_write_combine, EVENT_WRITE_COMBINE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_war_hazard, EVENT_WAR_HAZARD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_raw_hazard, EVENT_RAW_HAZARD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_waw_hazard, EVENT_WAW_HAZARD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_selfref, EVENT_OP_IS_ENTER_SELFREF), + CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_powerdown, + EVENT_OP_IS_ENTER_POWERDOWN), + CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_mpsm, EVENT_OP_IS_ENTER_MPSM), + CN10K_DDR_PMU_EVENT_ATTR(ddr_refresh, EVENT_OP_IS_REFRESH), + CN10K_DDR_PMU_EVENT_ATTR(ddr_crit_ref, EVENT_OP_IS_CRIT_REF), + CN10K_DDR_PMU_EVENT_ATTR(ddr_spec_ref, EVENT_OP_IS_SPEC_REF), + CN10K_DDR_PMU_EVENT_ATTR(ddr_load_mode, EVENT_OP_IS_LOAD_MODE), + CN10K_DDR_PMU_EVENT_ATTR(ddr_zqcl, EVENT_OP_IS_ZQCL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_wr_access, EVENT_OP_IS_ZQCS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cycles, EVENT_DFI_CYCLES), + CN10K_DDR_PMU_EVENT_ATTR(ddr_retry_fifo_full, + EVENT_RETRY_FIFO_FULL), + CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_alloc, EVENT_BSM_ALLOC), + CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_starvation, EVENT_BSM_STARVATION), + CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd, + EVENT_VISIBLE_WIN_LIMIT_REACHED_RD), + CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_wr, + EVENT_VISIBLE_WIN_LIMIT_REACHED_WR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mpc, EVENT_OP_IS_DQSOSC_MPC), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mrr, EVENT_OP_IS_DQSOSC_MRR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_tcr_mrr, EVENT_OP_IS_TCR_MRR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_zqstart, EVENT_OP_IS_ZQSTART), + CN10K_DDR_PMU_EVENT_ATTR(ddr_zqlatch, EVENT_OP_IS_ZQLATCH), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_parity_poison, + EVENT_DFI_PARITY_POISON), + CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_crc_error, EVENT_WR_CRC_ERROR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_capar_error, EVENT_CAPAR_ERROR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_crc_error, EVENT_RD_CRC_ERROR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_uc_ecc_error, EVENT_RD_UC_ECC_ERROR), + CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cmd_is_retry, EVENT_DFI_CMD_IS_RETRY), + /* Free run event counters */ + CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_reads, EVENT_DDR_READS), + CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_writes, EVENT_DDR_WRITES), + NULL +}; + +static struct attribute_group odyssey_ddr_perf_events_attr_group =3D { + .name =3D "events", + .attrs =3D odyssey_ddr_perf_events_attrs, +}; + static struct attribute_group cn10k_ddr_perf_events_attr_group =3D { .name =3D "events", .attrs =3D cn10k_ddr_perf_events_attrs, @@ -285,6 +386,13 @@ static const struct attribute_group *cn10k_attr_groups= [] =3D { NULL, }; =20 +static const struct attribute_group *odyssey_attr_groups[] =3D { + &odyssey_ddr_perf_events_attr_group, + &cn10k_ddr_perf_format_attr_group, + &cn10k_ddr_perf_cpumask_attr_group, + NULL +}; + /* Default poll timeout is 100 sec, which is very sufficient for * 48 bit counter incremented max at 5.6 GT/s, which may take many * hours to overflow. @@ -297,9 +405,18 @@ static ktime_t cn10k_ddr_pmu_timer_period(void) return ms_to_ktime((u64)cn10k_ddr_pmu_poll_period_sec * USEC_PER_SEC); } =20 -static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap) +static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap, + struct cn10k_ddr_pmu *ddr_pmu) { + int err =3D 0; + switch (eventid) { + case EVENT_DFI_PARITY_POISON ...EVENT_DFI_CMD_IS_RETRY: + if (!ddr_pmu->p_data->is_ody) { + err =3D -EINVAL; + break; + } + fallthrough; case EVENT_HIF_RD_OR_WR ... EVENT_WAW_HAZARD: case EVENT_OP_IS_REFRESH ... EVENT_OP_IS_ZQLATCH: *event_bitmap =3D (1ULL << (eventid - 1)); @@ -310,11 +427,12 @@ static int ddr_perf_get_event_bitmap(int eventid, u64= *event_bitmap) *event_bitmap =3D (0xFULL << (eventid - 1)); break; default: - pr_err("%s Invalid eventid %d\n", __func__, eventid); - return -EINVAL; + err =3D -EINVAL; } =20 - return 0; + if (err) + pr_err("%s Invalid eventid %d\n", __func__, eventid); + return err; } =20 static int cn10k_ddr_perf_alloc_counter(struct cn10k_ddr_pmu *pmu, @@ -382,11 +500,33 @@ static int cn10k_ddr_perf_event_init(struct perf_even= t *event) return 0; } =20 +static void cn10k_ddr_perf_counter_start(struct cn10k_ddr_pmu *ddr_pmu, + int counter) +{ + const struct ddr_pmu_platform_data *p_data =3D ddr_pmu->p_data; + u64 ctrl_reg =3D p_data->cnt_start_op_ctrl; + + writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base + + DDRC_PERF_REG(ctrl_reg, counter)); +} + +static void cn10k_ddr_perf_counter_stop(struct cn10k_ddr_pmu *ddr_pmu, + int counter) +{ + const struct ddr_pmu_platform_data *p_data =3D ddr_pmu->p_data; + u64 ctrl_reg =3D p_data->cnt_end_op_ctrl; + + writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base + + DDRC_PERF_REG(ctrl_reg, counter)); +} + static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu, int counter, bool enable) { const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 ctrl_reg =3D pmu->p_data->cnt_op_mode_ctrl; const struct ddr_pmu_ops *ops =3D pmu->ops; + bool is_ody =3D pmu->p_data->is_ody; u32 reg; u64 val; =20 @@ -405,6 +545,22 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k= _ddr_pmu *pmu, val &=3D ~EVENT_ENABLE; =20 writeq_relaxed(val, pmu->base + reg); + + if (is_ody) { + if (enable) { + /* + * Setup the PMU counter to work in + * manual mode + */ + reg =3D DDRC_PERF_REG(ctrl_reg, counter); + writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, + pmu->base + reg); + + cn10k_ddr_perf_counter_start(pmu, counter); + } else { + cn10k_ddr_perf_counter_stop(pmu, counter); + } + } } else { if (counter =3D=3D DDRC_PERF_READ_COUNTER_IDX) ops->enable_read_freerun_counter(pmu, enable); @@ -486,7 +642,7 @@ static int cn10k_ddr_perf_event_add(struct perf_event *= event, int flags) if (counter < DDRC_PERF_NUM_GEN_COUNTERS) { /* Generic counters, configure event id */ reg_offset =3D DDRC_PERF_CFG(p_data->cfg_base, counter); - ret =3D ddr_perf_get_event_bitmap(config, &val); + ret =3D ddr_perf_get_event_bitmap(config, &val, pmu); if (ret) return ret; =20 @@ -631,6 +787,66 @@ static void ddr_pmu_overflow_hander(struct cn10k_ddr_p= mu *pmu, int evt_idx) cn10k_ddr_perf_pmu_enable(&pmu->pmu); } =20 +static void ddr_pmu_ody_enable_read_freerun(struct cn10k_ddr_pmu *pmu, + bool enable) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D readq_relaxed(pmu->base + p_data->cnt_freerun_ctrl); + if (enable) + val |=3D DDRC_PERF_FREERUN_READ_EN; + else + val &=3D ~DDRC_PERF_FREERUN_READ_EN; + + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl); +} + +static void ddr_pmu_ody_enable_write_freerun(struct cn10k_ddr_pmu *pmu, + bool enable) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D readq_relaxed(pmu->base + p_data->cnt_freerun_ctrl); + if (enable) + val |=3D DDRC_PERF_FREERUN_WRITE_EN; + else + val &=3D ~DDRC_PERF_FREERUN_WRITE_EN; + + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_ctrl); +} + +static void ddr_pmu_ody_read_clear_freerun(struct cn10k_ddr_pmu *pmu) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D DDRC_FREERUN_READ_CNT_CLR; + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_clr); +} + +static void ddr_pmu_ody_write_clear_freerun(struct cn10k_ddr_pmu *pmu) +{ + const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; + u64 val; + + val =3D DDRC_FREERUN_WRITE_CNT_CLR; + writeq_relaxed(val, pmu->base + p_data->cnt_freerun_clr); +} + +static void ddr_pmu_ody_overflow_hander(struct cn10k_ddr_pmu *pmu, int evt= _idx) +{ + /* + * On reaching the maximum value of the counter, the counter freezes + * there. The particular event is updated and the respective counter + * is stopped and started again so that it starts counting from zero + */ + cn10k_ddr_perf_event_update(pmu->events[evt_idx]); + cn10k_ddr_perf_counter_stop(pmu, evt_idx); + cn10k_ddr_perf_counter_start(pmu, evt_idx); +} + static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pm= u) { const struct ddr_pmu_platform_data *p_data =3D pmu->p_data; @@ -740,6 +956,33 @@ static const struct ddr_pmu_platform_data cn10k_ddr_pm= u_pdata =3D { }; #endif =20 +static const struct ddr_pmu_ops ddr_pmu_ody_ops =3D { + .enable_read_freerun_counter =3D ddr_pmu_ody_enable_read_freerun, + .enable_write_freerun_counter =3D ddr_pmu_ody_enable_write_freerun, + .clear_read_freerun_counter =3D ddr_pmu_ody_read_clear_freerun, + .clear_write_freerun_counter =3D ddr_pmu_ody_write_clear_freerun, + .pmu_overflow_handler =3D ddr_pmu_ody_overflow_hander, +}; + +#ifdef CONFIG_ACPI +static const struct ddr_pmu_platform_data odyssey_ddr_pmu_pdata =3D { + .counter_overflow_val =3D 0, + .counter_max_val =3D GENMASK_ULL(63, 0), + .cnt_base =3D ODY_DDRC_PERF_CNT_VALUE_BASE, + .cfg_base =3D ODY_DDRC_PERF_CFG_BASE, + .cnt_op_mode_ctrl =3D ODY_DDRC_PERF_CNT_OP_MODE_CTRL, + .cnt_start_op_ctrl =3D ODY_DDRC_PERF_CNT_START_OP_CTRL, + .cnt_end_op_ctrl =3D ODY_DDRC_PERF_CNT_END_OP_CTRL, + .cnt_end_status =3D ODY_DDRC_PERF_CNT_END_STATUS, + .cnt_freerun_en =3D 0, + .cnt_freerun_ctrl =3D ODY_DDRC_PERF_CNT_FREERUN_CTRL, + .cnt_freerun_clr =3D ODY_DDRC_PERF_CNT_FREERUN_CLR, + .cnt_value_wr_op =3D ODY_DDRC_PERF_CNT_VALUE_WR_OP, + .cnt_value_rd_op =3D ODY_DDRC_PERF_CNT_VALUE_RD_OP, + .is_ody =3D TRUE, +}; +#endif + static int cn10k_ddr_perf_probe(struct platform_device *pdev) { const struct ddr_pmu_platform_data *dev_data; @@ -747,6 +990,7 @@ static int cn10k_ddr_perf_probe(struct platform_device = *pdev) struct resource *res; void __iomem *base; bool is_cn10k; + bool is_ody; char *name; int ret; =20 @@ -771,6 +1015,7 @@ static int cn10k_ddr_perf_probe(struct platform_device= *pdev) =20 ddr_pmu->p_data =3D dev_data; is_cn10k =3D ddr_pmu->p_data->is_cn10k; + is_ody =3D ddr_pmu->p_data->is_ody; =20 if (is_cn10k) { ddr_pmu->ops =3D &ddr_pmu_ops; @@ -794,6 +1039,23 @@ static int cn10k_ddr_perf_probe(struct platform_devic= e *pdev) }; } =20 + if (is_ody) { + ddr_pmu->ops =3D &ddr_pmu_ody_ops; + + ddr_pmu->pmu =3D (struct pmu) { + .module =3D THIS_MODULE, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr =3D perf_invalid_context, + .attr_groups =3D odyssey_attr_groups, + .event_init =3D cn10k_ddr_perf_event_init, + .add =3D cn10k_ddr_perf_event_add, + .del =3D cn10k_ddr_perf_event_del, + .start =3D cn10k_ddr_perf_event_start, + .stop =3D cn10k_ddr_perf_event_stop, + .read =3D cn10k_ddr_perf_event_update, + }; + } + /* Choose this cpu to collect perf data */ ddr_pmu->cpu =3D raw_smp_processor_id(); =20 @@ -844,6 +1106,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); #ifdef CONFIG_ACPI static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] =3D { {"MRVL000A", (kernel_ulong_t)&cn10k_ddr_pmu_pdata }, + {"MRVL000C", (kernel_ulong_t)&odyssey_ddr_pmu_pdata}, {}, }; MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match); --=20 2.25.1 From nobody Sun Nov 24 02:41:08 2024 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEC5013CF82 for ; Fri, 8 Nov 2024 04:07:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038870; cv=none; b=daSe0i+3OLnnareShGqrY+jKmEN+gfSb+OcFEsMDXQSc0sW7v6GvMtd3prhy8c25cUF4Rfs92/WKYu2OIE3ZbcxkkyIv+bxZkeFI9WVWIuyP355EokM5YxkScqChzY7O9OrnTQg/q2ZGVQxB6R0LFzFttHc0Lu2EhWAgnWfrUqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038870; c=relaxed/simple; bh=3BBhHHa6rIFNrt/IOTllf7MvQ5LwoRNz5BsSMPmhrYE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oDVvgo/Cd/zOiAPamnBA0snxrYhpuj5jeSTgMRFgHu+ImVxPM/vt916p9qihh2SGfGSOsuArdJKSlhgieFH3SOfkPmXDKqFdhDPhYq5GyBoQXsfcO+B9X7rHZzpdimFN+RYHZwDTBRXqdEIWxX4YdyGEw5ZwROk0GOsEGGFhHkg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=c8W9mpY7; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="c8W9mpY7" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MbeZF022679; Thu, 7 Nov 2024 20:07:34 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=b sh/TfKVaVmAQ/s79PFHSIvaGT8VuUklUA+F6C/IWJo=; b=c8W9mpY7p1joRnnLi vE9VUzggO+NwdPL3avggQyCbnPdi4oEkY4H3EET1ikp5nBAsKeYFeOVf1M1r9zAR 716MKOrM10bagmnfOhvV0SFslrHWNlUPI2Xv7+vKTQBLPkBoTqfjF8k8Pk5DbJGE /eJ68x1yCKaxpPQmhxY4img7ZdHD2Q+dO9j2r50EoUAzRjmKZ/PNg9COHpnRRkGU c2YKMmEuxPHhc6pG28mgyVtdhqLG87R73ZxGOyWIAN2bPdTfu7yJqtaV6qE9kvLV 2YwZvi3WOAd732CE+dCn8xMc+x8VouqVc9gN3DYk1WZky11gS741m+HaI21ddkyp 1JWRg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42s6gu8m30-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 20:07:34 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 20:06:41 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 20:06:41 -0800 Received: from IPBU-BLR-SERVER1.marvell.com (IPBU-BLR-SERVER1.marvell.com [10.28.8.41]) by maili.marvell.com (Postfix) with ESMTP id D10575B6926; Thu, 7 Nov 2024 20:06:38 -0800 (PST) From: Gowthami Thiagarajan To: , , , CC: , , , , Gowthami Thiagarajan Subject: [PATCH v10 4/5] perf/marvell : Refactor to extract platform data - no functional change Date: Fri, 8 Nov 2024 09:36:18 +0530 Message-ID: <20241108040619.753343-5-gthiagarajan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241108040619.753343-1-gthiagarajan@marvell.com> References: <20241108040619.753343-1-gthiagarajan@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 6wQ_zX72FbYDoaU_blzlT_dGD-0q6Slr X-Proofpoint-GUID: 6wQ_zX72FbYDoaU_blzlT_dGD-0q6Slr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" Refactor the Marvell TAD PMU driver to add versioning to the=20 existing driver. Make no functional changes, the behavior and performance of the driver remain unchanged. Signed-off-by: Gowthami Thiagarajan --- drivers/perf/marvell_cn10k_tad_pmu.c | 31 +++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index 9e635f355470..15f9f67cb3bd 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -37,6 +37,14 @@ struct tad_pmu { DECLARE_BITMAP(counters_map, TAD_MAX_COUNTERS); }; =20 +enum mrvl_tad_pmu_version { + TAD_PMU_V1 =3D 1, +}; + +struct tad_pmu_data { + int id; +}; + static int tad_pmu_cpuhp_state; =20 static void tad_pmu_event_counter_read(struct perf_event *event) @@ -254,6 +262,7 @@ static const struct attribute_group *tad_pmu_attr_group= s[] =3D { =20 static int tad_pmu_probe(struct platform_device *pdev) { + const struct tad_pmu_data *dev_data; struct device *dev =3D &pdev->dev; struct tad_region *regions; struct tad_pmu *tad_pmu; @@ -261,6 +270,7 @@ static int tad_pmu_probe(struct platform_device *pdev) u32 tad_pmu_page_size; u32 tad_page_size; u32 tad_cnt; + int version; int i, ret; char *name; =20 @@ -270,6 +280,13 @@ static int tad_pmu_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, tad_pmu); =20 + dev_data =3D device_get_match_data(&pdev->dev); + if (!dev_data) { + dev_err(&pdev->dev, "Error: No device match data found\n"); + return -ENODEV; + } + version =3D dev_data->id; + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Mem resource not found\n"); @@ -319,7 +336,6 @@ static int tad_pmu_probe(struct platform_device *pdev) tad_pmu->pmu =3D (struct pmu) { =20 .module =3D THIS_MODULE, - .attr_groups =3D tad_pmu_attr_groups, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, .task_ctx_nr =3D perf_invalid_context, @@ -332,6 +348,9 @@ static int tad_pmu_probe(struct platform_device *pdev) .read =3D tad_pmu_event_counter_read, }; =20 + if (version =3D=3D TAD_PMU_V1) + tad_pmu->pmu.attr_groups =3D tad_pmu_attr_groups; + tad_pmu->cpu =3D raw_smp_processor_id(); =20 /* Register pmu instance for cpu hotplug */ @@ -360,16 +379,22 @@ static void tad_pmu_remove(struct platform_device *pd= ev) perf_pmu_unregister(&pmu->pmu); } =20 +#if defined(CONFIG_OF) || defined(CONFIG_ACPI) +static const struct tad_pmu_data tad_pmu_data =3D { + .id =3D TAD_PMU_V1, +}; +#endif + #ifdef CONFIG_OF static const struct of_device_id tad_pmu_of_match[] =3D { - { .compatible =3D "marvell,cn10k-tad-pmu", }, + { .compatible =3D "marvell,cn10k-tad-pmu", .data =3D &tad_pmu_data }, {}, }; #endif =20 #ifdef CONFIG_ACPI static const struct acpi_device_id tad_pmu_acpi_match[] =3D { - {"MRVL000B", 0}, + {"MRVL000B", (kernel_ulong_t)&tad_pmu_data}, {}, }; MODULE_DEVICE_TABLE(acpi, tad_pmu_acpi_match); --=20 2.25.1 From nobody Sun Nov 24 02:41:08 2024 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 102D213CF82 for ; Fri, 8 Nov 2024 04:09:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038988; cv=none; b=GffubMBc0ysVu/eaPUnJO4l5cDytf9WUCz5q2i+MtaXCZoyCYybWXpPMKZCZMFYYqAgN5eQgpMyuVA9bdon0eu7V3lU3vcWc0nqWMpPQyy32QupVsnSt7NZHiL35xk0f7S6JDu9/25gjxad9ORrl1IklAaVvt6MtaWC/RUYfGII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731038988; c=relaxed/simple; bh=obyV78oUjWVeKRdPHEazO9TW3s8naiInq747cCOT01Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Lm6gqIubcuLm+KPT4B0HxxstmHKn7TGQcz4a0XRQrzBucw7qYDRFWM2fILD56waqDUAoH6tpAFc89i32M+A4IZ9p5i38fuaQp9vnNacFbK1jKe2oDYTO303AuZkoOMPw0SP640UeVsdJUbjIBfuvvzctoGVtHsOVIUjS0HDxoUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=N1EKDyUO; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="N1EKDyUO" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7MbeZ8022679; Thu, 7 Nov 2024 20:07:32 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=2 vBA9/YIjtC9NXvu1JNHv6kTYHCKQnYXVoCmc4mw7mw=; b=N1EKDyUO5i393bkRi 8nYFezF17Ifsr9oQ3mahp2e1uZdflglCAz5elBGa1yfiG9q/8BMr4JxMXQZNnSC2 UUYvHogG0K8Kv98jnxecj2CKzMHKzf1j+yyIUNLL0X+ITTfBhqCOScoxxqGyxemT hkOPv2yj63masvHiE3DnN2Wr9P2uj6yztPmjoda2NJlgKp4CcE6iwAeeaFBMUBSP +Zr/86Up59zOi7qgRW07rvO6WsukemJR4HWTo8SCjCC0kY3XmIdxQ91d+P+Ml6jo nwq1c9jjA5cy3ZB/HQRXJf7oibJ9is+QWeFBzDt7BAjB2QTQ/c0NjexwvXuq9Fqj l8gvg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42s6gu8m2q-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 20:07:31 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 20:06:46 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 20:06:46 -0800 Received: from IPBU-BLR-SERVER1.marvell.com (IPBU-BLR-SERVER1.marvell.com [10.28.8.41]) by maili.marvell.com (Postfix) with ESMTP id 958F05B6926; Thu, 7 Nov 2024 20:06:43 -0800 (PST) From: Gowthami Thiagarajan To: , , , CC: , , , , Gowthami Thiagarajan Subject: [PATCH v10 5/5] perf/marvell : Odyssey LLC-TAD performance monitor support Date: Fri, 8 Nov 2024 09:36:19 +0530 Message-ID: <20241108040619.753343-6-gthiagarajan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241108040619.753343-1-gthiagarajan@marvell.com> References: <20241108040619.753343-1-gthiagarajan@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: IDRVywGm_Ra8IZHu8LtpM_G_u9d_UC4S X-Proofpoint-GUID: IDRVywGm_Ra8IZHu8LtpM_G_u9d_UC4S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" Each TAD provides eight 64-bit counters for monitoring cache behavior.The driver always configures the same counter for all the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of running the workload. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications. The performance events reflect various internal or interface activities. By combining the values from multiple performance counters, cache performance can be measured in terms such as: cache miss rate, cache allocations, interface retry rate, internal resource occupancy, etc. Each supported counter's event and formatting information is exposed to sysfs at /sys/devices/tad/. Use perf tool stat command to measure the pmu events. For instance: perf stat -e tad_hit_ltg,tad_hit_dtg Signed-off-by: Gowthami Thiagarajan --- Documentation/admin-guide/perf/index.rst | 1 + .../admin-guide/perf/mrvl-odyssey-tad-pmu.rst | 37 +++++++++++++++++++ drivers/perf/marvell_cn10k_tad_pmu.c | 35 ++++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100644 Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index f9be610b2e6d..0aecdc3e4efa 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -15,6 +15,7 @@ Performance monitor support qcom_l3_pmu starfive_starlink_pmu mrvl-odyssey-ddr-pmu + mrvl-odyssey-tad-pmu arm-ccn arm-cmn arm-ni diff --git a/Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst b/Docu= mentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst new file mode 100644 index 000000000000..ad1975b14087 --- /dev/null +++ b/Documentation/admin-guide/perf/mrvl-odyssey-tad-pmu.rst @@ -0,0 +1,37 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Marvell Odyssey LLC-TAD Performance Monitoring Unit (PMU UNCORE) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Each TAD provides eight 64-bit counters for monitoring +cache behavior.The driver always configures the same counter for +all the TADs. The user would end up effectively reserving one of +eight counters in every TAD to look across all TADs. +The occurrences of events are aggregated and presented to the user +at the end of running the workload. The driver does not provide a +way for the user to partition TADs so that different TADs are used for +different applications. + +The performance events reflect various internal or interface activities. +By combining the values from multiple performance counters, cache +performance can be measured in terms such as: cache miss rate, cache +allocations, interface retry rate, internal resource occupancy, etc. + +The PMU driver exposes the available events and format options under sysfs= :: + + /sys/bus/event_source/devices/tad/events/ + /sys/bus/event_source/devices/tad/format/ + +Examples:: + + $ perf list | grep tad + tad/tad_alloc_any/ [Kernel PMU eve= nt] + tad/tad_alloc_dtg/ [Kernel PMU eve= nt] + tad/tad_alloc_ltg/ [Kernel PMU eve= nt] + tad/tad_hit_any/ [Kernel PMU eve= nt] + tad/tad_hit_dtg/ [Kernel PMU eve= nt] + tad/tad_hit_ltg/ [Kernel PMU eve= nt] + tad/tad_req_msh_in_exlmn/ [Kernel PMU eve= nt] + tad/tad_tag_rd/ [Kernel PMU eve= nt] + tad/tad_tot_cycle/ [Kernel PMU eve= nt] + + $ perf stat -e tad_alloc_dtg,tad_alloc_ltg,tad_alloc_any,tad_hit_dtg,ta= d_hit_ltg,tad_hit_any,tad_tag_rd diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index 15f9f67cb3bd..29976b435417 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -39,6 +39,7 @@ struct tad_pmu { =20 enum mrvl_tad_pmu_version { TAD_PMU_V1 =3D 1, + TAD_PMU_V2, }; =20 struct tad_pmu_data { @@ -222,6 +223,24 @@ static const struct attribute_group tad_pmu_events_att= r_group =3D { .attrs =3D tad_pmu_event_attrs, }; =20 +static struct attribute *ody_tad_pmu_event_attrs[] =3D { + TAD_PMU_EVENT_ATTR(tad_req_msh_in_exlmn, 0x3), + TAD_PMU_EVENT_ATTR(tad_alloc_dtg, 0x1a), + TAD_PMU_EVENT_ATTR(tad_alloc_ltg, 0x1b), + TAD_PMU_EVENT_ATTR(tad_alloc_any, 0x1c), + TAD_PMU_EVENT_ATTR(tad_hit_dtg, 0x1d), + TAD_PMU_EVENT_ATTR(tad_hit_ltg, 0x1e), + TAD_PMU_EVENT_ATTR(tad_hit_any, 0x1f), + TAD_PMU_EVENT_ATTR(tad_tag_rd, 0x20), + TAD_PMU_EVENT_ATTR(tad_tot_cycle, 0xFF), + NULL +}; + +static const struct attribute_group ody_tad_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D ody_tad_pmu_event_attrs, +}; + PMU_FORMAT_ATTR(event, "config:0-7"); =20 static struct attribute *tad_pmu_format_attrs[] =3D { @@ -260,6 +279,13 @@ static const struct attribute_group *tad_pmu_attr_grou= ps[] =3D { NULL }; =20 +static const struct attribute_group *ody_tad_pmu_attr_groups[] =3D { + &ody_tad_pmu_events_attr_group, + &tad_pmu_format_attr_group, + &tad_pmu_cpumask_attr_group, + NULL +}; + static int tad_pmu_probe(struct platform_device *pdev) { const struct tad_pmu_data *dev_data; @@ -350,6 +376,8 @@ static int tad_pmu_probe(struct platform_device *pdev) =20 if (version =3D=3D TAD_PMU_V1) tad_pmu->pmu.attr_groups =3D tad_pmu_attr_groups; + else + tad_pmu->pmu.attr_groups =3D ody_tad_pmu_attr_groups; =20 tad_pmu->cpu =3D raw_smp_processor_id(); =20 @@ -385,6 +413,12 @@ static const struct tad_pmu_data tad_pmu_data =3D { }; #endif =20 +#ifdef CONFIG_ACPI +static const struct tad_pmu_data tad_pmu_v2_data =3D { + .id =3D TAD_PMU_V2, +}; +#endif + #ifdef CONFIG_OF static const struct of_device_id tad_pmu_of_match[] =3D { { .compatible =3D "marvell,cn10k-tad-pmu", .data =3D &tad_pmu_data }, @@ -395,6 +429,7 @@ static const struct of_device_id tad_pmu_of_match[] =3D= { #ifdef CONFIG_ACPI static const struct acpi_device_id tad_pmu_acpi_match[] =3D { {"MRVL000B", (kernel_ulong_t)&tad_pmu_data}, + {"MRVL000D", (kernel_ulong_t)&tad_pmu_v2_data}, {}, }; MODULE_DEVICE_TABLE(acpi, tad_pmu_acpi_match); --=20 2.25.1