From nobody Sun Nov 24 05:00:26 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E96E2481DD for ; Fri, 8 Nov 2024 02:15:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731032104; cv=none; b=G7TcnvMT5QdMCzE4j1pJTmt2/4HxzYC3asZpBNphXivvwHviuSI++ZOlZqDuCxhblhAa1rR2eECrQbQRG6VaIZ20M2tBoV/bMZrVLnvrbIm5ExBHJD7bPA5VXY2O3Z/7N/eZZoaSmI/qAhKj3NKcZ1p1ZRfpiwhRgOAvDcx0RoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731032104; c=relaxed/simple; bh=rnccXpvvV6E9nMU3XuiFVBN1Y54SbbFLjDOdujr0Vg8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q2PtsYnbeXjmu3V+tDkPgBYLwLDM0bFMoLBpm50+ZqEe2iIIOq3weXL8GZOmVDUdEMfxBmLLKJ/YdZoJCYapcDhA5d3FKdP0qM/g1otFrUHElcWQVXN/TqSv506OGY/V7sSNTEpBVOK84gS7nvZZEIXjM13eigzoesWbJrmQdWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HiAmt215; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HiAmt215" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731032103; x=1762568103; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rnccXpvvV6E9nMU3XuiFVBN1Y54SbbFLjDOdujr0Vg8=; b=HiAmt215SjtizK76DvFLsmHLE6my9rFkBLR8fwGT0BjJOemDoAGB+KtF CZDUIwprSu7bApMgB4QYuwM+Jz4PLq9wx42g0qA+j2daVU5XcyXowhtO+ CeFTxoa/BW4la/eB0sgw8Lx84g/olzaMtXuIMqIzihuYBRmpjRS2UPCOC dsHKWmB91aYQrwyyA3gkVmaPkKFYvC6ONjSSlk9NUvimbOUu9912YkW17 xKKXlmp6RPOk5uK2N418IgvI/9MbLTEFxuGEIxuxNYMjBl+hq/eMhp1KQ 9TpdiyGPYPbXhRUsF+2ookmNaTGaBuA3u2JB+gtpiw/IgeTiF4u2ccSYm A==; X-CSE-ConnectionGUID: 9rgvER+6QJezQVyhyAJUOw== X-CSE-MsgGUID: xagFqE15QH+ahh7EIBJTdQ== X-IronPort-AV: E=McAfee;i="6700,10204,11249"; a="31007738" X-IronPort-AV: E=Sophos;i="6.12,136,1728975600"; d="scan'208";a="31007738" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 18:15:02 -0800 X-CSE-ConnectionGUID: /KE6/FgbRHSla2uvbYEdsA== X-CSE-MsgGUID: GG5RL0UeQySIT6/UAl6HLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,136,1728975600"; d="scan'208";a="116213732" Received: from allen-sbox.sh.intel.com ([10.239.159.30]) by fmviesa001.fm.intel.com with ESMTP; 07 Nov 2024 18:15:00 -0800 From: Lu Baolu To: Joerg Roedel Cc: Jason Gunthorpe , Kevin Tian , Yi Liu , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 02/13] iommu/vt-d: Add a helper to flush cache for updating present pasid entry Date: Fri, 8 Nov 2024 10:13:53 +0800 Message-ID: <20241108021406.173972-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241108021406.173972-1-baolu.lu@linux.intel.com> References: <20241108021406.173972-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Yi Liu Generalize the logic for flushing pasid-related cache upon changes to bits other than SSADE and P which requires a different flow according to VT-d spec. No functional change is intended. Reviewed-by: Lu Baolu Reviewed-by: Kevin Tian Signed-off-by: Yi Liu Link: https://lore.kernel.org/r/20241107122234.7424-3-yi.l.liu@intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/pasid.c | 52 ++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 31665fb62e1c..8d11701c2e76 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -287,6 +287,39 @@ static void pasid_flush_caches(struct intel_iommu *iom= mu, } } =20 +/* + * This function is supposed to be used after caller updates the fields + * except for the SSADE and P bit of a pasid table entry. It does the + * below: + * - Flush cacheline if needed + * - Flush the caches per Table 28 =E2=80=9DGuidance to Software for Inval= idations=E2=80=9C + * of VT-d spec 5.0. + */ +static void intel_pasid_flush_present(struct intel_iommu *iommu, + struct device *dev, + u32 pasid, u16 did, + struct pasid_entry *pte) +{ + if (!ecap_coherent(iommu->ecap)) + clflush_cache_range(pte, sizeof(*pte)); + + /* + * VT-d spec 5.0 table28 states guides for cache invalidation: + * + * - PASID-selective-within-Domain PASID-cache invalidation + * - PASID-selective PASID-based IOTLB invalidation + * - If (pasid is RID_PASID) + * - Global Device-TLB invalidation to affected functions + * Else + * - PASID-based Device-TLB invalidation (with S=3D1 and + * Addr[63:12]=3D0x7FFFFFFF_FFFFF) to affected functions + */ + pasid_cache_invalidation_with_pasid(iommu, did, pasid); + qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); + + devtlb_invalidation_with_pasid(iommu, dev, pasid); +} + /* * Set up the scalable mode pasid table entry for first only * translation type. @@ -526,24 +559,7 @@ void intel_pasid_setup_page_snoop_control(struct intel= _iommu *iommu, did =3D pasid_get_domain_id(pte); spin_unlock(&iommu->lock); =20 - if (!ecap_coherent(iommu->ecap)) - clflush_cache_range(pte, sizeof(*pte)); - - /* - * VT-d spec 3.4 table23 states guides for cache invalidation: - * - * - PASID-selective-within-Domain PASID-cache invalidation - * - PASID-selective PASID-based IOTLB invalidation - * - If (pasid is RID_PASID) - * - Global Device-TLB invalidation to affected functions - * Else - * - PASID-based Device-TLB invalidation (with S=3D1 and - * Addr[63:12]=3D0x7FFFFFFF_FFFFF) to affected functions - */ - pasid_cache_invalidation_with_pasid(iommu, did, pasid); - qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); - - devtlb_invalidation_with_pasid(iommu, dev, pasid); + intel_pasid_flush_present(iommu, dev, pasid, did, pte); } =20 /** --=20 2.43.0