From nobody Sun Nov 24 04:45:28 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F20711CF292; Fri, 8 Nov 2024 04:11:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731039063; cv=none; b=DWb/hmNv4Cv3ck5ROTBlmJ00hajkHDzBRRFYZA1ywCM4x5kpE9HMhsIFsqpOYN4Pfn0Ihg5ifdzpgW7+LalFrOiziHZ9tBEYT538kOLycxf22xWt/qLbbAlIHmD984yt9QjbJAgo2VQIHcjzf+novoRoO4Gx5u41lSBrX+2gIF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731039063; c=relaxed/simple; bh=q9hoVRImFMbgxE4HcTk/Vpj77eH7hY781HwIhE7HAv4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=VxHwrpBl5Uc9fyFxKwiMuw61JEDcOpoNQkCcn0MOUMug3/r66NFwe2fyNVx/8QHSvZgsS4PfQ0Kzzrw5YfsHYVx9AbzxooXMx4T5jBugYurz8V1hxPfjOPkrsLEZGNsY0de2wqgLGJj2ohy5M6wk6nvQ/cWl9gxio/8LzGbJwb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=msd5eKVt; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="msd5eKVt" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7Mb2bU030659; Fri, 8 Nov 2024 04:10:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= M9OGsaPPQIZ4mVWrMSoWVbICdS/QGG7nJlTXLwpwBVk=; b=msd5eKVtnDoRVrH2 FLUr/outRKrl5ghUCXkykaDThaW8ulmbXm596QOSRlyy9ZtwMbZ5AEaomvbdU0vh TH8qObMyOehC6pWtRS3E92R9Ld4WZHo5AMUD8cbnUg3UfUAwOuCvjFuzumm3yL25 0ksj47tfXUEbiqB8eZC8m5GzwRcZB0GvFqGGBc4HOHCnNhjYlyVrJtBiYs8KX2tN A2/+wOPmptvXVlGqBvEEGLDhBKnrV3DbDZo+/UPagLIt7zqHS3omHD0gqc2lK0SJ HjQsRRxOSKXtOcJ+fhtJDVj/2krMVXbcdv6unEScmzVH3RkDfYZrltxN/0uhICBw BU6bCQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42s6gdrkp3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 08 Nov 2024 04:10:30 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A84ATYw017593 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 8 Nov 2024 04:10:29 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 7 Nov 2024 20:10:24 -0800 From: Taniya Das Date: Fri, 8 Nov 2024 09:39:26 +0530 Subject: [PATCH v3 09/11] dt-bindings: clock: Add Qualcomm QCS615 Video clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241108-qcs615-mm-clockcontroller-v3-9-7d3b2d235fdf@quicinc.com> References: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com> In-Reply-To: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BLVc4XmGobIBokfhrKRK_TXnjUnMtYrx X-Proofpoint-ORIG-GUID: BLVc4XmGobIBokfhrKRK_TXnjUnMtYrx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411080034 Add DT bindings for the Video clock on QCS615 platforms. Add the relevant DT include definitions as well. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,qcs615-videocc.yaml | 64 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,qcs615-videocc.h | 30 ++++++++++ 2 files changed, 94 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3359fb68124341d9673eb860a51= d09a60459745d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on QCS615 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides clocks, resets and power + domains on QCS615 Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,qcs615-videocc.h + +properties: + compatible: + const: qcom,qcs615-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + clock-controller@ab00000 { + compatible =3D "qcom,qcs615-videocc"; + reg =3D <0xab00000 0x10000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcs615-videocc.h b/include/dt-b= indings/clock/qcom,qcs615-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..0ca3efb21103d7e0b09ab9c042b= e761bcbc5960d --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-videocc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_SLEEP_CLK 0 +#define VIDEO_CC_SLEEP_CLK_SRC 1 +#define VIDEO_CC_VCODEC0_AXI_CLK 2 +#define VIDEO_CC_VCODEC0_CORE_CLK 3 +#define VIDEO_CC_VENUS_AHB_CLK 4 +#define VIDEO_CC_VENUS_CLK_SRC 5 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 6 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 7 +#define VIDEO_CC_XO_CLK 8 +#define VIDEO_PLL0 9 + +/* VIDEO_CC power domains */ +#define VCODEC0_GDSC 0 +#define VENUS_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_VCODEC0_BCR 1 +#define VIDEO_CC_VENUS_BCR 2 + +#endif --=20 2.45.2