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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-1-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2535; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=abn+V/VW2R04+ivG5L+16aCpi+lS1tSzUvuSfrCga00=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmOlTL82Q+yU+jTYQJ2nDrxLnq8YKm4nBQrW XWQ3vKXdO6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZjgAKCRCLPIo+Aiko 1aVAB/wMp1GUIzKR0e0Z7EmL6OhYO8pzNKgXmJzLpBJHGsb3lAkcVB8stTyd7yx4NyeObcSp0dN FEXTHPvI4cEqqpzxMjTMzvERHuhHalCM/N4bmNMEg9aBigDEDFFeyVoIOgrOVrYPe1PsFL6ibG7 BxcCRw1Xe4T0Dzdcj5708UB0Ejd54RFOjX7lfeC+JAryOMN05sG3b+S2NJsOHi4fq/Dhk6HGu5T wLyg+ob9chEYbWjZvDgaixAMyFsah9l5WnBj4IFCcWOlbJ1H9d3cTnpnv+W7PG7VxzJFk3b+kNn tUJRuMx5kL6Wa/PvEsa2clV8XVeqacZ/osSRe8CjnyW1wkLD X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The msm_dp_utils_pack_sdp_header() accepts an unlimited-size u32 pointer for the header output, while it expects a two-element array. It performs a sizeof check which is always true on 64-bit platforms (since sizeof(u32*) is 8) and is always falce on 32-bit platforms. It returns an error code which nobody actually checks. Fix the function interface to accept u32[2] and return void, skipping all the checks. Fixes: 55fb8ffc1802 ("drm/msm/dp: add VSC SDP support for YUV420 over DP") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_utils.c | 10 +--------- drivers/gpu/drm/msm/dp/dp_utils.h | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_utils.c b/drivers/gpu/drm/msm/dp/dp_= utils.c index 2a40f07fe2d5e20114a7692d1269bb8fd5bddbbd..4a5ebb0c33b85e3d55eb974d74c= 1f54591301b35 100644 --- a/drivers/gpu/drm/msm/dp/dp_utils.c +++ b/drivers/gpu/drm/msm/dp/dp_utils.c @@ -74,14 +74,8 @@ u8 msm_dp_utils_calculate_parity(u32 data) return parity_byte; } =20 -ssize_t msm_dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32= *header_buff) +void msm_dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 he= ader_buff[2]) { - size_t length; - - length =3D sizeof(header_buff); - if (length < DP_SDP_HEADER_SIZE) - return -ENOSPC; - header_buff[0] =3D FIELD_PREP(HEADER_0_MASK, sdp_header->HB0) | FIELD_PREP(PARITY_0_MASK, msm_dp_utils_calculate_parity(sdp_header->HB0)= ) | FIELD_PREP(HEADER_1_MASK, sdp_header->HB1) | @@ -91,6 +85,4 @@ ssize_t msm_dp_utils_pack_sdp_header(struct dp_sdp_header= *sdp_header, u32 *head FIELD_PREP(PARITY_2_MASK, msm_dp_utils_calculate_parity(sdp_header->HB2)= ) | FIELD_PREP(HEADER_3_MASK, sdp_header->HB3) | FIELD_PREP(PARITY_3_MASK, msm_dp_utils_calculate_parity(sdp_header->HB3)= ); - - return length; } diff --git a/drivers/gpu/drm/msm/dp/dp_utils.h b/drivers/gpu/drm/msm/dp/dp_= utils.h index 88d53157f5b59e352a29075e4e8deb044a6de3bd..2e4f98a863c4cb971e621ac24b8= b58f035236e73 100644 --- a/drivers/gpu/drm/msm/dp/dp_utils.h +++ b/drivers/gpu/drm/msm/dp/dp_utils.h @@ -31,6 +31,6 @@ u8 msm_dp_utils_get_g0_value(u8 data); u8 msm_dp_utils_get_g1_value(u8 data); u8 msm_dp_utils_calculate_parity(u32 data); -ssize_t msm_dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32= *header_buff); +void msm_dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 he= ader_buff[2]); =20 #endif /* _DP_UTILS_H_ */ --=20 2.39.5 From nobody Sun Nov 24 02:24:07 2024 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B422E1BD9E2 for ; Fri, 8 Nov 2024 00:21:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 07 Nov 2024 16:21:43 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ff17900a63sm4195191fa.47.2024.11.07.16.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2024 16:21:43 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 08 Nov 2024 02:21:33 +0200 Subject: [PATCH 02/14] drm/msm/dp: drop msm_dp_panel_dump_regs() and msm_dp_catalog_dump_regs() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-2-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4566; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=AR2ot2ScldeaKrjr/qeTAbSFGVp+4LY+MmiRX3d+ewg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmOYKBgfvb+d+khmE2/qFL9b8EIYfJneeqrr jL0XRP1qqiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZjgAKCRCLPIo+Aiko 1UqCB/9UqsIYfGSTs8f23lHRsCMhL86Oo4W2rAeToZsOGj4vggqbsrTchD5BS0MY37Y1/hS+J5O GCsz81GpFHoHZQJtdaLtEZVLTOSrE553BDARSYVosWT6W1jTafsxubFHe6I8z+GzWUUkJf4yIHK Ov0GcWbCGLTWvC0hHhqZDASPwv3Tj19Y9Xt6m2W5OxMZy803VmL55RTOboq9vEu3NHXil6bYyG0 iNWgF/MeU52rpM68MheZAKRvbVC4AI74HhVBxC8beI7vHzf0kDmH9m1gWVNvr2W7amU/7kMRXWO mXPjOXDTAW/11X3Ay/sbgkwiTc4m8G7z2fLFwrjHW/jfBhMB X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The msm_dp_panel_dump_regs() and msm_dp_catalog_dump_regs() are not called anywhere. If there is a necessity to dump registers, the snapshotting should be used instead. Drop these two functions. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 37 ---------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 1 - drivers/gpu/drm/msm/dp/dp_panel.c | 11 ----------- drivers/gpu/drm/msm/dp/dp_panel.h | 1 - 4 files changed, 50 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index b4c8856fb25d01dd1b30c5ec33ce821aafa9551d..0357dec1acd5773f25707e7ebdf= ca4b1d2b1bb4e 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -276,43 +276,6 @@ int msm_dp_catalog_aux_wait_for_hpd_connect_state(stru= ct msm_dp_catalog *msm_dp_ min(wait_us, 2000), wait_us); } =20 -static void dump_regs(void __iomem *base, int len) -{ - int i; - u32 x0, x4, x8, xc; - u32 addr_off =3D 0; - - len =3D DIV_ROUND_UP(len, 16); - for (i =3D 0; i < len; i++) { - x0 =3D readl_relaxed(base + addr_off); - x4 =3D readl_relaxed(base + addr_off + 0x04); - x8 =3D readl_relaxed(base + addr_off + 0x08); - xc =3D readl_relaxed(base + addr_off + 0x0c); - - pr_info("%08x: %08x %08x %08x %08x", addr_off, x0, x4, x8, xc); - addr_off +=3D 16; - } -} - -void msm_dp_catalog_dump_regs(struct msm_dp_catalog *msm_dp_catalog) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - struct dss_io_data *io =3D &catalog->io; - - pr_info("AHB regs\n"); - dump_regs(io->ahb.base, io->ahb.len); - - pr_info("AUXCLK regs\n"); - dump_regs(io->aux.base, io->aux.len); - - pr_info("LCLK regs\n"); - dump_regs(io->link.base, io->link.len); - - pr_info("P0CLK regs\n"); - dump_regs(io->p0.base, io->p0.len); -} - u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) { struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index e932b17eecbf514070cd8cd0b98ca0fefbe81ab7..62a401d8f75a6af06445a42af65= 7d65e3fe542c5 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -104,7 +104,6 @@ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catal= og *msm_dp_catalog, u32 t u32 sync_start, u32 width_blanking, u32 msm_dp_active); void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp); void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog); -void msm_dp_catalog_dump_regs(struct msm_dp_catalog *msm_dp_catalog); void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, struct drm_display_mode *drm_mode); void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 5d7eaa31bf3176566f40f01ff636bee64e81c64f..7d122496723a32fd591d0942693= 97a9fdd51fe44 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -317,17 +317,6 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct m= sm_dp_panel *msm_dp_panel) return 0; } =20 -void msm_dp_panel_dump_regs(struct msm_dp_panel *msm_dp_panel) -{ - struct msm_dp_catalog *catalog; - struct msm_dp_panel_private *panel; - - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); 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The msm_dp_panel_tpg_config() has never been called. Drop it and the implementation inside dp_catalog.c Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 78 ---------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 3 -- drivers/gpu/drm/msm/dp/dp_panel.c | 28 ------------- drivers/gpu/drm/msm/dp/dp_panel.h | 1 - 4 files changed, 110 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 0357dec1acd5773f25707e7ebdfca4b1d2b1bb4e..9ca2a4ab251106d72219b11c2be= 7049b4a2611d5 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -963,84 +963,6 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_d= p_catalog *msm_dp_catalog) msm_dp_catalog_panel_update_sdp(msm_dp_catalog); } =20 -void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, - struct drm_display_mode *drm_mode) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 hsync_period, vsync_period; - u32 display_v_start, display_v_end; - u32 hsync_start_x, hsync_end_x; - u32 v_sync_width; - u32 hsync_ctl; - u32 display_hctl; - - /* TPG config parameters*/ - hsync_period =3D drm_mode->htotal; - vsync_period =3D drm_mode->vtotal; - - display_v_start =3D ((drm_mode->vtotal - drm_mode->vsync_start) * - hsync_period); - display_v_end =3D ((vsync_period - (drm_mode->vsync_start - - drm_mode->vdisplay)) - * hsync_period) - 1; - - display_v_start +=3D drm_mode->htotal - drm_mode->hsync_start; - display_v_end -=3D (drm_mode->hsync_start - drm_mode->hdisplay); - - hsync_start_x =3D drm_mode->htotal - drm_mode->hsync_start; - hsync_end_x =3D hsync_period - (drm_mode->hsync_start - - drm_mode->hdisplay) - 1; - - v_sync_width =3D drm_mode->vsync_end - drm_mode->vsync_start; - - hsync_ctl =3D (hsync_period << 16) | - (drm_mode->hsync_end - drm_mode->hsync_start); - display_hctl =3D (hsync_end_x << 16) | hsync_start_x; - - - msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * - hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * - hsync_period); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); - drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__); -} - -void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); -} - static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 62a401d8f75a6af06445a42af657d65e3fe542c5..ebac3e6aa6b3d51c7a74fd4318a= e7c595b3bf2e4 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -104,9 +104,6 @@ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catal= og *msm_dp_catalog, u32 t u32 sync_start, u32 width_blanking, u32 msm_dp_active); void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp); void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog); -void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, - struct drm_display_mode *drm_mode); -void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalo= g); =20 struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 7d122496723a32fd591d094269397a9fdd51fe44..7a5656d8702e4f9c6f8e13d0078= 8a5bdbbe3729f 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -242,34 +242,6 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_pa= nel *msm_dp_panel) } } =20 -void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e) -{ - struct msm_dp_catalog *catalog; - struct msm_dp_panel_private *panel; - - if (!msm_dp_panel) { - DRM_ERROR("invalid input\n"); - return; - } - - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - catalog =3D panel->catalog; - - if (!panel->panel_on) { - drm_dbg_dp(panel->drm_dev, - "DP panel not enabled, handle TPG on next on\n"); - return; - } - - if (!enable) { - msm_dp_catalog_panel_tpg_disable(catalog); - return; - } - - drm_dbg_dp(panel->drm_dev, "calling catalog tpg_enable\n"); - msm_dp_catalog_panel_tpg_enable(catalog, &panel->msm_dp_panel.msm_dp_mode= .drm_mode); -} - static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_= panel) { struct msm_dp_catalog *catalog; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 47c1d349be470b60596b64a7bc8c7c39d2e8fdd1..317e2a13d7e917acd78edd2f1c9= 9c4be3de902bd 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -62,7 +62,6 @@ u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp= _panel, u32 mode_max_bp int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, struct drm_connector *connector); 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Thu, 07 Nov 2024 16:21:47 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 08 Nov 2024 02:21:35 +0200 Subject: [PATCH 04/14] drm/msm/dp: pull I/O data out of msm_dp_catalog_private() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-4-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=46698; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=NOw14ZC0Qb5ZvMM1TEGpGir3pe04ryX8n0sQfiGdLiw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmPrwE3+7aWrx1PSO586HxX/jX/VnmVcLySB q9OBBdD3mSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZjwAKCRCLPIo+Aiko 1aMwB/wIJvoV0gNgSOg4bSb0dtkoMwAM7Tv0NgsgE+IROrMJ1poY0AMA4oF5hQtdsghL45/9G4v ZQ/6ClPmtINiaD3EehxgvPCtqMTmpiWpKQIVL8HI/QEpXgxoaG60H+aLz5fccyPWjCISs6qZ4L3 HucYLBNyEa7yKOgngMQeODbQFjlkG424L0MI+sIaaIAekJqb2tKk03TGPX8FJlkzkq497gl5DMJ rW8rn61C9yzjF/vKgLmWXwQxRcGNk1Si9OzJy6TGh9zMzO49tNJA5N+EvKQfbrDPqehraIKJWy/ ySB/bf4OQEy77vBMn1NFHCBdxIM28t3LCqdFftoszPH7opYY X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Having I/O regions inside a msm_dp_catalog_private() results in extra layers of one-line wrappers for accessing the data. Move I/O region base and size to the globally visible struct msm_dp_catalog. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 453 ++++++++++++++------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 12 + 2 files changed, 193 insertions(+), 272 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 9ca2a4ab251106d72219b11c2be7049b4a2611d5..a8193581eaaaed9234a06128357= 7af068ada0ad6 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -63,155 +63,124 @@ #define DP_DEFAULT_P0_OFFSET 0x1000 #define DP_DEFAULT_P0_SIZE 0x0400 =20 -struct dss_io_region { - size_t len; - void __iomem *base; -}; - -struct dss_io_data { - struct dss_io_region ahb; - struct dss_io_region aux; - struct dss_io_region link; - struct dss_io_region p0; -}; - struct msm_dp_catalog_private { struct device *dev; struct drm_device *drm_dev; - struct dss_io_data io; u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX]; struct msm_dp_catalog msm_dp_catalog; }; =20 void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - struct dss_io_data *dss =3D &catalog->io; - - msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_= ahb"); - msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_= aux"); - msm_disp_snapshot_add_block(disp_state, dss->link.len, dss->link.base, "d= p_link"); - msm_disp_snapshot_add_block(disp_state, dss->p0.len, dss->p0.base, "dp_p0= "); + msm_disp_snapshot_add_block(disp_state, msm_dp_catalog->ahb_len, msm_dp_c= atalog->ahb_base, "dp_ahb"); + msm_disp_snapshot_add_block(disp_state, msm_dp_catalog->aux_len, msm_dp_c= atalog->aux_base, "dp_aux"); + msm_disp_snapshot_add_block(disp_state, msm_dp_catalog->link_len, msm_dp_= catalog->link_base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_catalog->p0_len, msm_dp_ca= talog->p0_base, "dp_p0"); } =20 -static inline u32 msm_dp_read_aux(struct msm_dp_catalog_private *catalog, = u32 offset) +static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) { - return readl_relaxed(catalog->io.aux.base + offset); + return readl_relaxed(msm_dp_catalog->aux_base + offset); } =20 -static inline void msm_dp_write_aux(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.aux.base + offset); + writel(data, msm_dp_catalog->aux_base + offset); } =20 -static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog_private *cat= alog, u32 offset) +static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) { - return readl_relaxed(catalog->io.ahb.base + offset); + return readl_relaxed(msm_dp_catalog->ahb_base + offset); } =20 -static inline void msm_dp_write_ahb(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.ahb.base + offset); + writel(data, msm_dp_catalog->ahb_base + offset); } =20 -static inline void msm_dp_write_p0(struct msm_dp_catalog_private *catalog, +static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.p0.base + offset); + writel(data, msm_dp_catalog->p0_base + offset); } =20 -static inline u32 msm_dp_read_p0(struct msm_dp_catalog_private *catalog, +static inline u32 msm_dp_read_p0(struct msm_dp_catalog *msm_dp_catalog, u32 offset) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io.p0.base + offset); + return readl_relaxed(msm_dp_catalog->p0_base + offset); } =20 -static inline u32 msm_dp_read_link(struct msm_dp_catalog_private *catalog,= u32 offset) +static inline u32 msm_dp_read_link(struct msm_dp_catalog *msm_dp_catalog, = u32 offset) { - return readl_relaxed(catalog->io.link.base + offset); + return readl_relaxed(msm_dp_catalog->link_base + offset); } =20 -static inline void msm_dp_write_link(struct msm_dp_catalog_private *catalo= g, +static inline void msm_dp_write_link(struct msm_dp_catalog *msm_dp_catalog, u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io.link.base + offset); + writel(data, msm_dp_catalog->link_base + offset); } =20 /* aux related catalog functions */ u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_aux(catalog, REG_DP_AUX_DATA); + return msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_DATA); } =20 int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u= 32 data) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_aux(catalog, REG_DP_AUX_DATA, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_DATA, data); return 0; } =20 int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, = u32 data) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); return 0; } =20 int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, = bool read) { u32 data; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 if (read) { - data =3D msm_dp_read_aux(catalog, REG_DP_AUX_TRANS_CTRL); + data =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL); data &=3D ~DP_AUX_TRANS_CTRL_GO; - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); } else { - msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, 0); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, 0); } return 0; } =20 int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_c= atalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_read_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); - msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); + msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); return 0; } =20 @@ -230,47 +199,41 @@ int msm_dp_catalog_aux_clear_hw_interrupts(struct msm= _dp_catalog *msm_dp_catalog void msm_dp_catalog_aux_reset(struct msm_dp_catalog *msm_dp_catalog) { u32 aux_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - aux_ctrl =3D msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); =20 aux_ctrl |=3D DP_AUX_CTRL_RESET; - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); usleep_range(1000, 1100); /* h/w recommended delay */ =20 aux_ctrl &=3D ~DP_AUX_CTRL_RESET; - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); } =20 void msm_dp_catalog_aux_enable(struct msm_dp_catalog *msm_dp_catalog, bool= enable) { u32 aux_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - aux_ctrl =3D msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); =20 if (enable) { - msm_dp_write_aux(catalog, REG_DP_TIMEOUT_COUNT, 0xffff); - msm_dp_write_aux(catalog, REG_DP_AUX_LIMITS, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); aux_ctrl |=3D DP_AUX_CTRL_ENABLE; } else { aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; } =20 - msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); } =20 int msm_dp_catalog_aux_wait_for_hpd_connect_state(struct msm_dp_catalog *m= sm_dp_catalog, unsigned long wait_us) { u32 state; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 /* poll for hpd connected status every 2ms and timeout after wait_us */ - return readl_poll_timeout(catalog->io.aux.base + + return readl_poll_timeout(msm_dp_catalog->aux_base + REG_DP_DP_HPD_INT_STATUS, state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, min(wait_us, 2000), wait_us); @@ -278,15 +241,13 @@ int msm_dp_catalog_aux_wait_for_hpd_connect_state(str= uct msm_dp_catalog *msm_dp_ =20 u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); intr &=3D ~DP_INTERRUPT_STATUS1_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS1) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, intr_ack | + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, intr_ack | DP_INTERRUPT_STATUS1_MASK); =20 return intr; @@ -298,20 +259,14 @@ void msm_dp_catalog_ctrl_update_transfer_unit(struct = msm_dp_catalog *msm_dp_cata u32 msm_dp_tu, u32 valid_boundary, u32 valid_boundary2) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(catalog, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2); + msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(msm_dp_catalog, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary= 2); } =20 void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog,= u32 state) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, state); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, state); } =20 void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog= , u32 cfg) @@ -321,13 +276,11 @@ void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_ca= talog *msm_dp_catalog, u32 =20 drm_dbg_dp(catalog->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", cfg); =20 - msm_dp_write_link(catalog, REG_DP_CONFIGURATION_CTRL, cfg); + msm_dp_write_link(msm_dp_catalog, REG_DP_CONFIGURATION_CTRL, cfg); } =20 void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ u32 ln_mapping; =20 @@ -336,7 +289,7 @@ void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_cat= alog *msm_dp_catalog) ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; =20 - msm_dp_write_link(catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); } =20 @@ -344,17 +297,15 @@ void msm_dp_catalog_ctrl_psr_mainlink_enable(struct m= sm_dp_catalog *msm_dp_catal bool enable) { u32 val; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - val =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 if (enable) val |=3D DP_MAINLINK_CTRL_ENABLE; else val &=3D ~DP_MAINLINK_CTRL_ENABLE; =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); } =20 void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catal= og, @@ -370,25 +321,25 @@ void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_= catalog *msm_dp_catalog, * To make sure link reg writes happens before other operation, * msm_dp_write_link() function uses writel() */ - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); =20 mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } else { - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } } =20 @@ -400,7 +351,7 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_cata= log *msm_dp_catalog, struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - misc_val =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + misc_val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -410,16 +361,14 @@ void msm_dp_catalog_ctrl_config_misc(struct msm_dp_ca= talog *msm_dp_catalog, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(catalog->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc_val); } =20 void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog) { u32 mainlink_ctrl, hw_revision; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - mainlink_ctrl =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); =20 hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); if (hw_revision >=3D DP_HW_VERSION_1_2) @@ -427,7 +376,7 @@ void msm_dp_catalog_setup_peripheral_flush(struct msm_d= p_catalog *msm_dp_catalog else mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; =20 - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, @@ -485,9 +434,9 @@ void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catal= og *msm_dp_catalog, nvid *=3D 3; =20 drm_dbg_dp(catalog->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); - msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_MVID, mvid); + msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0); } =20 int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, @@ -505,7 +454,7 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct ms= m_dp_catalog *msm_dp_cata bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; =20 /* Poll for mainlink ready status */ - ret =3D readx_poll_timeout(readl, catalog->io.link.base + + ret =3D readx_poll_timeout(readl, msm_dp_catalog->link_base + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -526,10 +475,7 @@ int msm_dp_catalog_ctrl_set_pattern_state_bit(struct m= sm_dp_catalog *msm_dp_cata */ u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog) { - const struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_cata= log, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_ahb(catalog, REG_DP_HW_VERSION); + return msm_dp_read_ahb(msm_dp_catalog, REG_DP_HW_VERSION); } =20 /** @@ -547,28 +493,24 @@ u32 msm_dp_catalog_hw_revision(const struct msm_dp_ca= talog *msm_dp_catalog) void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog) { u32 sw_reset; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 - sw_reset =3D msm_dp_read_ahb(catalog, REG_DP_SW_RESET); + sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); =20 sw_reset |=3D DP_SW_RESET; - msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); usleep_range(1000, 1100); /* h/w recommended delay */ =20 sw_reset &=3D ~DP_SW_RESET; - msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); } =20 bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log) { u32 data; int ret; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); =20 /* Poll for mainlink ready status */ - ret =3D readl_poll_timeout(catalog->io.link.base + + ret =3D readl_poll_timeout(msm_dp_catalog->link_base + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -583,17 +525,14 @@ bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp= _catalog *msm_dp_catalog) void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, bool enable) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - if (enable) { - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, DP_INTERRUPT_STATUS1_MASK); - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); } else { - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, 0x00); - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); } } =20 @@ -603,73 +542,63 @@ void msm_dp_catalog_hpd_config_intr(struct msm_dp_cat= alog *msm_dp_catalog, struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - u32 config =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + u32 config =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); =20 config =3D (en ? config | intr_mask : config & ~intr_mask); =20 drm_dbg_dp(catalog->drm_dev, "intr_mask=3D%#x config=3D%#x\n", intr_mask, config); - msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, config & DP_DP_HPD_INT_MASK); } =20 void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 reftimer =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); =20 /* Configure REFTIMER and enable it */ reftimer |=3D DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); =20 /* Enable HPD */ - msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); } =20 void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 reftimer =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); =20 reftimer &=3D ~DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); =20 - msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); } =20 -static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog_private *catal= og) +static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog *msm_dp_catalo= g) { /* trigger sdp */ - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); } =20 void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 config; =20 /* enable PSR1 function */ - config =3D msm_dp_read_link(catalog, REG_PSR_CONFIG); + config =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); config |=3D PSR1_SUPPORTED; - msm_dp_write_link(catalog, REG_PSR_CONFIG, config); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, config); =20 - msm_dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); - msm_dp_catalog_enable_sdp(catalog); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); + msm_dp_catalog_enable_sdp(msm_dp_catalog); } =20 void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bo= ol enter) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 cmd; =20 - cmd =3D msm_dp_read_link(catalog, REG_PSR_CMD); + cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); =20 cmd &=3D ~(PSR_ENTER | PSR_EXIT); =20 @@ -678,8 +607,8 @@ void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog = *msm_dp_catalog, bool ent else cmd |=3D PSR_EXIT; =20 - msm_dp_catalog_enable_sdp(catalog); - msm_dp_write_link(catalog, REG_PSR_CMD, cmd); + msm_dp_catalog_enable_sdp(msm_dp_catalog); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); } =20 u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) @@ -688,7 +617,7 @@ u32 msm_dp_catalog_link_is_connected(struct msm_dp_cata= log *msm_dp_catalog) struct msm_dp_catalog_private, msm_dp_catalog); u32 status; =20 - status =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); + status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status); status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; @@ -698,14 +627,12 @@ u32 msm_dp_catalog_link_is_connected(struct msm_dp_ca= talog *msm_dp_catalog) =20 u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); int isr, mask; =20 - isr =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); - msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, + isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, (isr & DP_DP_HPD_INT_MASK)); - mask =3D msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); =20 /* * We only want to return interrupts that are unmasked to the caller. @@ -719,29 +646,25 @@ u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_= catalog *msm_dp_catalog) =20 u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS4); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); intr_ack =3D (intr & DP_INTERRUPT_STATUS4) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); =20 return intr; } =20 int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 intr, intr_ack; =20 - intr =3D msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS2); + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); intr &=3D ~DP_INTERRUPT_STATUS2_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS2) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, intr_ack | DP_INTERRUPT_STATUS2_MASK); =20 return intr; @@ -749,13 +672,10 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_c= atalog *msm_dp_catalog) =20 void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, + msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); usleep_range(1000, 1100); /* h/w recommended delay */ - msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, 0x0); } =20 void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_ca= talog, @@ -766,66 +686,66 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_= dp_catalog *msm_dp_catalog, u32 value =3D 0x0; =20 /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); =20 drm_dbg_dp(catalog->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &=3D ~(1 << 16); - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 0x0000F83E); break; case DP_PHY_TEST_PATTERN_CP2520: - value =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); =20 value =3D DP_HBR2_ERM_PATTERN; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, value); - msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); value |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); break; case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(catalog, REG_DP_STATE_CTRL, + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; default: @@ -837,26 +757,21 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_= dp_catalog *msm_dp_catalog, =20 u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - return msm_dp_read_link(catalog, REG_DP_MAINLINK_READY); + return msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_READY); } =20 /* panel related catalog functions */ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, u32 sync_start, u32 width_blanking, u32 msm_dp_active) { - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); u32 reg; =20 - msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); - msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blank= ing); - msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + msm_dp_write_link(msm_dp_catalog, REG_DP_TOTAL_HOR_VER, total); + msm_dp_write_link(msm_dp_catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_st= art); + msm_dp_write_link(msm_dp_catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, widt= h_blanking); + msm_dp_write_link(msm_dp_catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); =20 - reg =3D msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); + reg =3D msm_dp_read_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG); =20 if (msm_dp_catalog->wide_bus_en) reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; @@ -866,42 +781,36 @@ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_cat= alog *msm_dp_catalog, u32 t =20 DRM_DEBUG_DP("wide_bus_en=3D%d reg=3D%#x\n", msm_dp_catalog->wide_bus_en,= reg); =20 - msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG, reg); return 0; } =20 static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_d= p_catalog, struct dp_sdp *vsc_sdp) { - struct msm_dp_catalog_private *catalog; u32 header[2]; u32 val; int i; =20 - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_1, header[1]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(catalog, MMSS_DP_GENERIC0_2 + i, val); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); } } =20 static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_= catalog) { - struct msm_dp_catalog_private *catalog; u32 hw_revision; =20 - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >=3D DP_HW_VERSION_1_0= ) { - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x01); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x00); } } =20 @@ -912,15 +821,15 @@ void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_d= p_catalog *msm_dp_catalog, =20 catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); =20 - cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); =20 cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); =20 msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp); =20 @@ -930,7 +839,7 @@ void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_= catalog *msm_dp_catalog, drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); =20 msm_dp_catalog_panel_update_sdp(msm_dp_catalog); } @@ -942,15 +851,15 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_= dp_catalog *msm_dp_catalog) =20 catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); =20 - cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); =20 cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -958,7 +867,7 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp= _catalog *msm_dp_catalog) drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); =20 msm_dp_catalog_panel_update_sdp(msm_dp_catalog); } @@ -977,15 +886,15 @@ static void __iomem *msm_dp_ioremap(struct platform_d= evice *pdev, int idx, size_ =20 static int msm_dp_catalog_get_io(struct msm_dp_catalog_private *catalog) { + struct msm_dp_catalog *msm_dp_catalog =3D &catalog->msm_dp_catalog; struct platform_device *pdev =3D to_platform_device(catalog->dev); - struct dss_io_data *dss =3D &catalog->io; =20 - dss->ahb.base =3D msm_dp_ioremap(pdev, 0, &dss->ahb.len); - if (IS_ERR(dss->ahb.base)) - return PTR_ERR(dss->ahb.base); + msm_dp_catalog->ahb_base =3D msm_dp_ioremap(pdev, 0, &msm_dp_catalog->ahb= _len); + if (IS_ERR(msm_dp_catalog->ahb_base)) + return PTR_ERR(msm_dp_catalog->ahb_base); =20 - dss->aux.base =3D msm_dp_ioremap(pdev, 1, &dss->aux.len); - if (IS_ERR(dss->aux.base)) { + msm_dp_catalog->aux_base =3D msm_dp_ioremap(pdev, 1, &msm_dp_catalog->aux= _len); + if (IS_ERR(msm_dp_catalog->aux_base)) { /* * The initial binding had a single reg, but in order to * support variation in the sub-region sizes this was split. @@ -993,34 +902,34 @@ static int msm_dp_catalog_get_io(struct msm_dp_catalo= g_private *catalog) * reg is specified, so fill in the sub-region offsets and * lengths based on this single region. */ - if (PTR_ERR(dss->aux.base) =3D=3D -EINVAL) { - if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + if (PTR_ERR(msm_dp_catalog->aux_base) =3D=3D -EINVAL) { + if (msm_dp_catalog->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE= ) { DRM_ERROR("legacy memory region not large enough\n"); return -EINVAL; } =20 - dss->ahb.len =3D DP_DEFAULT_AHB_SIZE; - dss->aux.base =3D dss->ahb.base + DP_DEFAULT_AUX_OFFSET; - dss->aux.len =3D DP_DEFAULT_AUX_SIZE; - dss->link.base =3D dss->ahb.base + DP_DEFAULT_LINK_OFFSET; - dss->link.len =3D DP_DEFAULT_LINK_SIZE; - dss->p0.base =3D dss->ahb.base + DP_DEFAULT_P0_OFFSET; - dss->p0.len =3D DP_DEFAULT_P0_SIZE; + msm_dp_catalog->ahb_len =3D DP_DEFAULT_AHB_SIZE; + msm_dp_catalog->aux_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_AUX_= OFFSET; + msm_dp_catalog->aux_len =3D DP_DEFAULT_AUX_SIZE; + msm_dp_catalog->link_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_LIN= K_OFFSET; + msm_dp_catalog->link_len =3D DP_DEFAULT_LINK_SIZE; + msm_dp_catalog->p0_base =3D msm_dp_catalog->ahb_base + DP_DEFAULT_P0_OF= FSET; + msm_dp_catalog->p0_len =3D DP_DEFAULT_P0_SIZE; } else { - DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base); - return PTR_ERR(dss->aux.base); + DRM_ERROR("unable to remap aux region: %pe\n", msm_dp_catalog->aux_base= ); + return PTR_ERR(msm_dp_catalog->aux_base); } } else { - dss->link.base =3D msm_dp_ioremap(pdev, 2, &dss->link.len); - if (IS_ERR(dss->link.base)) { - DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); - return PTR_ERR(dss->link.base); + msm_dp_catalog->link_base =3D msm_dp_ioremap(pdev, 2, &msm_dp_catalog->l= ink_len); + if (IS_ERR(msm_dp_catalog->link_base)) { + DRM_ERROR("unable to remap link region: %pe\n", msm_dp_catalog->link_ba= se); + return PTR_ERR(msm_dp_catalog->link_base); } =20 - dss->p0.base =3D msm_dp_ioremap(pdev, 3, &dss->p0.len); - if (IS_ERR(dss->p0.base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); - return PTR_ERR(dss->p0.base); + msm_dp_catalog->p0_base =3D msm_dp_ioremap(pdev, 3, &msm_dp_catalog->p0_= len); + if (IS_ERR(msm_dp_catalog->p0_base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", msm_dp_catalog->p0_base); + return PTR_ERR(msm_dp_catalog->p0_base); } } =20 @@ -1057,7 +966,7 @@ u32 msm_dp_catalog_audio_get_header(struct msm_dp_cata= log *msm_dp_catalog, =20 sdp_map =3D catalog->audio_map; =20 - return msm_dp_read_link(catalog, sdp_map[sdp][header]); + return msm_dp_read_link(msm_dp_catalog, sdp_map[sdp][header]); } =20 void msm_dp_catalog_audio_set_header(struct msm_dp_catalog *msm_dp_catalog, @@ -1076,7 +985,7 @@ void msm_dp_catalog_audio_set_header(struct msm_dp_cat= alog *msm_dp_catalog, =20 sdp_map =3D catalog->audio_map; =20 - msm_dp_write_link(catalog, sdp_map[sdp][header], data); + msm_dp_write_link(msm_dp_catalog, sdp_map[sdp][header], data); } =20 void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *msm_dp_catalog= , u32 select) @@ -1095,7 +1004,7 @@ void msm_dp_catalog_audio_config_acr(struct msm_dp_ca= talog *msm_dp_catalog, u32 drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n", select, acr_ctrl); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); } =20 void msm_dp_catalog_audio_enable(struct msm_dp_catalog *msm_dp_catalog, bo= ol enable) @@ -1109,7 +1018,7 @@ void msm_dp_catalog_audio_enable(struct msm_dp_catalo= g *msm_dp_catalog, bool ena catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - audio_ctrl =3D msm_dp_read_link(catalog, MMSS_DP_AUDIO_CFG); + audio_ctrl =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG); =20 if (enable) audio_ctrl |=3D BIT(0); @@ -1118,7 +1027,7 @@ void msm_dp_catalog_audio_enable(struct msm_dp_catalo= g *msm_dp_catalog, bool ena =20 drm_dbg_dp(catalog->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); =20 - msm_dp_write_link(catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); /* make sure audio engine is disabled */ wmb(); } @@ -1135,7 +1044,7 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - sdp_cfg =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); + sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); /* AUDIO_TIMESTAMP_SDP_EN */ sdp_cfg |=3D BIT(1); /* AUDIO_STREAM_SDP_EN */ @@ -1149,9 +1058,9 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) =20 drm_dbg_dp(catalog->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); =20 - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, sdp_cfg); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); =20 - sdp_cfg2 =3D msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); + sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); /* IFRM_REGSRC -> Do not use reg values */ sdp_cfg2 &=3D ~BIT(0); /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ @@ -1159,7 +1068,7 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_ca= talog *msm_dp_catalog) =20 drm_dbg_dp(catalog->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); =20 - msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); } =20 void msm_dp_catalog_audio_init(struct msm_dp_catalog *msm_dp_catalog) @@ -1214,7 +1123,7 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_cat= alog *msm_dp_catalog, u32 s catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); =20 - mainlink_levels =3D msm_dp_read_link(catalog, REG_DP_MAINLINK_LEVELS); + mainlink_levels =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_LEVE= LS); mainlink_levels &=3D 0xFE0; mainlink_levels |=3D safe_to_exit_level; =20 @@ -1222,5 +1131,5 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_cat= alog *msm_dp_catalog, u32 s "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", mainlink_levels, safe_to_exit_level); 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 65 ---------------------------------= --- drivers/gpu/drm/msm/dp/dp_catalog.h | 66 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 66 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index a8193581eaaaed9234a061283577af068ada0ad6..24bd9167fc2a8a5ff749a1f84e2= eb76347ed8590 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -78,71 +78,6 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_= dp_catalog, struct msm_d msm_disp_snapshot_add_block(disp_state, msm_dp_catalog->p0_len, msm_dp_ca= talog->p0_base, "dp_p0"); } =20 -static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) -{ - return readl_relaxed(msm_dp_catalog->aux_base + offset); -} - -static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure aux reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->aux_base + offset); -} - -static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) -{ - return readl_relaxed(msm_dp_catalog->ahb_base + offset); -} - -static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure phy reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->ahb_base + offset); -} - -static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->p0_base + offset); -} - -static inline u32 msm_dp_read_p0(struct msm_dp_catalog *msm_dp_catalog, - u32 offset) -{ - /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - return readl_relaxed(msm_dp_catalog->p0_base + offset); -} - -static inline u32 msm_dp_read_link(struct msm_dp_catalog *msm_dp_catalog, = u32 offset) -{ - return readl_relaxed(msm_dp_catalog->link_base + offset); -} - -static inline void msm_dp_write_link(struct msm_dp_catalog *msm_dp_catalog, - u32 offset, u32 data) -{ - /* - * To make sure link reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() - */ - writel(data, msm_dp_catalog->link_base + offset); -} - /* aux related catalog functions */ u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) { diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index af54f8850a88f86e3c998cf6b5d1bdb93d42ba94..42ae8dae68bd0639172350e5aef= 0c522c1b02f6f 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -63,6 +63,72 @@ struct msm_dp_catalog { size_t p0_len; }; =20 +/* IO */ +static inline u32 msm_dp_read_aux(struct msm_dp_catalog *msm_dp_catalog, u= 32 offset) +{ + return readl_relaxed(msm_dp_catalog->aux_base + offset); +} + +static inline void msm_dp_write_aux(struct msm_dp_catalog *msm_dp_catalog, + u32 offset, u32 data) +{ + /* + * To make sure aux reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, msm_dp_catalog->aux_base + offset); +} + +static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog *msm_dp_cata= log, u32 offset) +{ + return readl_relaxed(msm_dp_catalog->ahb_base + offset); +} + +static inline void msm_dp_write_ahb(struct msm_dp_catalog *msm_dp_catalog, + u32 offset, u32 data) +{ + /* + * To make sure phy reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, msm_dp_catalog->ahb_base + offset); +} + +static inline void msm_dp_write_p0(struct msm_dp_catalog *msm_dp_catalog, + u32 offset, u32 data) +{ + /* + * To make sure interface reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + writel(data, msm_dp_catalog->p0_base + offset); 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a=openpgp-sha256; l=11775; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=jW0lUdSfq875NJ3uU8R2QI2Fx6RJrk2Ntmeqk7pyzpQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmPGks2/Obhcluk6XqtlvW+z9TkOoeOGAkbQ u5f7qKKEzWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZjwAKCRCLPIo+Aiko 1f85CACtEVDjAns0NNsCj8n7/o6iTQXuS/0vZ0nPJXGrcB7EdyrM1t5qXXHp5phmtkZ27xdG99k z1p7lv/9JGZFs5GCxpQLzwL9iQH7QlZRqPBBFJvvo629OqpRDKXfTPEr6MA+feOe8xFYvvTtUp6 Yu3VCNlHOqDd6PE4vG+YzKCr5L63vyo9fnDPxXZ1wQ8By3hyBQUrdEYaOL+PIA+uV6rBdl++aQy ZO3zEgJZg1EqM5RCXWfcXv2pxEGaqaKFTKTvus6un9RiTKmM3VdGEjIHIzDrQSmzPhPjsje7hWi mhdlWndFlFemUu8SFfBU7dATBRT/8llkBCBysdWaTEx6QjfX X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move all register-level functions to dp_aux.c, inlining one line wrappers during this process. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_aux.c | 98 +++++++++++++++++++++++++++++++--= ---- drivers/gpu/drm/msm/dp/dp_catalog.c | 96 ---------------------------------= --- drivers/gpu/drm/msm/dp/dp_catalog.h | 9 ---- 3 files changed, 84 insertions(+), 119 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index bc8d46abfc619d669dce339477d58fb0c464a3ea..46e8a2e13ac1d1249fbad9b50a6= d64c52d51cf38 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include =20 @@ -45,6 +46,73 @@ struct msm_dp_aux_private { struct drm_dp_aux msm_dp_aux; }; =20 +static int msm_dp_aux_clear_hw_interrupts(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + + msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); + msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); + + return 0; +} + +/* + * NOTE: resetting AUX controller will also clear any pending HPD related = interrupts + */ +static void msm_dp_aux_reset(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 aux_ctrl; + + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + + aux_ctrl |=3D DP_AUX_CTRL_RESET; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); + usleep_range(1000, 1100); /* h/w recommended delay */ + + aux_ctrl &=3D ~DP_AUX_CTRL_RESET; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); +} + +static void msm_dp_aux_enable(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 aux_ctrl; + + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + + msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); + + aux_ctrl |=3D DP_AUX_CTRL_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); +} + +static void msm_dp_aux_disable(struct msm_dp_aux_private *aux) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 aux_ctrl; + + aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); + aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); +} + +static int msm_dp_aux_wait_for_hpd_connect_state(struct msm_dp_aux_private= *aux, + unsigned long wait_us) +{ + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 state; + + /* poll for hpd connected status every 2ms and timeout after wait_us */ + return readl_poll_timeout(msm_dp_catalog->aux_base + + REG_DP_DP_HPD_INT_STATUS, + state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, + min(wait_us, 2000), wait_us); +} + #define MAX_AUX_RETRIES 5 =20 static ssize_t msm_dp_aux_write(struct msm_dp_aux_private *aux, @@ -88,11 +156,11 @@ static ssize_t msm_dp_aux_write(struct msm_dp_aux_priv= ate *aux, /* index =3D 0, write */ if (i =3D=3D 0) reg |=3D DP_AUX_DATA_INDEX_WRITE; - msm_dp_catalog_aux_write_data(aux->catalog, reg); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_DATA, reg); } =20 - msm_dp_catalog_aux_clear_trans(aux->catalog, false); - msm_dp_catalog_aux_clear_hw_interrupts(aux->catalog); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, 0); + msm_dp_aux_clear_hw_interrupts(aux); =20 reg =3D 0; /* Transaction number =3D=3D 1 */ if (!aux->native) { /* i2c */ @@ -106,7 +174,7 @@ static ssize_t msm_dp_aux_write(struct msm_dp_aux_priva= te *aux, } =20 reg |=3D DP_AUX_TRANS_CTRL_GO; - msm_dp_catalog_aux_write_trans(aux->catalog, reg); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, reg); =20 return len; } @@ -139,20 +207,22 @@ static ssize_t msm_dp_aux_cmd_fifo_rx(struct msm_dp_a= ux_private *aux, u32 i, actual_i; u32 len =3D msg->size; =20 - msm_dp_catalog_aux_clear_trans(aux->catalog, true); + data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL); + data &=3D ~DP_AUX_TRANS_CTRL_GO; + msm_dp_write_aux(aux->catalog, REG_DP_AUX_TRANS_CTRL, data); =20 data =3D DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */ data |=3D DP_AUX_DATA_READ; /* read */ =20 - msm_dp_catalog_aux_write_data(aux->catalog, data); + msm_dp_write_aux(aux->catalog, REG_DP_AUX_DATA, data); =20 dp =3D msg->buffer; =20 /* discard first byte */ - data =3D msm_dp_catalog_aux_read_data(aux->catalog); + data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_DATA); =20 for (i =3D 0; i < len; i++) { - data =3D msm_dp_catalog_aux_read_data(aux->catalog); + data =3D msm_dp_read_aux(aux->catalog, REG_DP_AUX_DATA); *dp++ =3D (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff); =20 actual_i =3D (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF; @@ -336,7 +406,7 @@ static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *m= sm_dp_aux, } /* reset aux if link is in connected state */ if (msm_dp_catalog_link_is_connected(aux->catalog)) - msm_dp_catalog_aux_reset(aux->catalog); + msm_dp_aux_reset(aux); } else { aux->retry_cnt =3D 0; switch (aux->aux_error_num) { @@ -403,7 +473,7 @@ irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_au= x) =20 if (isr & DP_INTR_AUX_ERROR) { aux->aux_error_num =3D DP_AUX_ERR_PHY; - msm_dp_catalog_aux_clear_hw_interrupts(aux->catalog); + msm_dp_aux_clear_hw_interrupts(aux); } else if (isr & DP_INTR_NACK_DEFER) { aux->aux_error_num =3D DP_AUX_ERR_NACK_DEFER; } else if (isr & DP_INTR_WRONG_ADDR) { @@ -444,7 +514,7 @@ void msm_dp_aux_reconfig(struct drm_dp_aux *msm_dp_aux) aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); =20 phy_calibrate(aux->phy); - msm_dp_catalog_aux_reset(aux->catalog); + msm_dp_aux_reset(aux); } =20 void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux) @@ -460,7 +530,7 @@ void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux) =20 mutex_lock(&aux->mutex); =20 - msm_dp_catalog_aux_enable(aux->catalog, true); + msm_dp_aux_enable(aux); aux->retry_cnt =3D 0; aux->initted =3D true; =20 @@ -476,7 +546,7 @@ void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux) mutex_lock(&aux->mutex); =20 aux->initted =3D false; - msm_dp_catalog_aux_enable(aux->catalog, false); + msm_dp_aux_disable(aux); =20 mutex_unlock(&aux->mutex); } @@ -517,7 +587,7 @@ static int msm_dp_wait_hpd_asserted(struct drm_dp_aux *= msm_dp_aux, if (ret) return ret; =20 - ret =3D msm_dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog, wait_= us); + ret =3D msm_dp_aux_wait_for_hpd_connect_state(aux, wait_us); pm_runtime_put_sync(aux->dev); =20 return ret; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 24bd9167fc2a8a5ff749a1f84e2eb76347ed8590..bed2c26f883e92319721ed8bd67= 2eb395cbf0544 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -78,102 +78,6 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm= _dp_catalog, struct msm_d msm_disp_snapshot_add_block(disp_state, msm_dp_catalog->p0_len, msm_dp_ca= talog->p0_base, "dp_p0"); } =20 -/* aux related catalog functions */ -u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) -{ - return msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_DATA); -} - -int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u= 32 data) -{ - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_DATA, data); - return 0; -} - -int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, = u32 data) -{ - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); - return 0; -} - -int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, = bool read) -{ - u32 data; - - if (read) { - data =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL); - data &=3D ~DP_AUX_TRANS_CTRL_GO; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, data); - } else { - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_TRANS_CTRL, 0); - } - return 0; -} - -int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_c= atalog) -{ - msm_dp_read_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); - msm_dp_write_aux(msm_dp_catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); - return 0; -} - -/** - * msm_dp_catalog_aux_reset() - reset AUX controller - * - * @msm_dp_catalog: DP catalog structure - * - * return: void - * - * This function reset AUX controller - * - * NOTE: reset AUX controller will also clear any pending HPD related inte= rrupts - *=20 - */ -void msm_dp_catalog_aux_reset(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 aux_ctrl; - - aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); - - aux_ctrl |=3D DP_AUX_CTRL_RESET; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); - usleep_range(1000, 1100); /* h/w recommended delay */ - - aux_ctrl &=3D ~DP_AUX_CTRL_RESET; - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); -} - -void msm_dp_catalog_aux_enable(struct msm_dp_catalog *msm_dp_catalog, bool= enable) -{ - u32 aux_ctrl; - - aux_ctrl =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_AUX_CTRL); - - if (enable) { - msm_dp_write_aux(msm_dp_catalog, REG_DP_TIMEOUT_COUNT, 0xffff); - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_LIMITS, 0xffff); - aux_ctrl |=3D DP_AUX_CTRL_ENABLE; - } else { - aux_ctrl &=3D ~DP_AUX_CTRL_ENABLE; - } - - msm_dp_write_aux(msm_dp_catalog, REG_DP_AUX_CTRL, aux_ctrl); -} - -int msm_dp_catalog_aux_wait_for_hpd_connect_state(struct msm_dp_catalog *m= sm_dp_catalog, - unsigned long wait_us) -{ - u32 state; - - /* poll for hpd connected status every 2ms and timeout after wait_us */ - return readl_poll_timeout(msm_dp_catalog->aux_base + - REG_DP_DP_HPD_INT_STATUS, - state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, - min(wait_us, 2000), wait_us); -} - u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) { u32 intr, intr_ack; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 42ae8dae68bd0639172350e5aef0c522c1b02f6f..fbcaf1fba66e7c5918137f7f809= 2f0749dd4da8c 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -133,15 +133,6 @@ static inline void msm_dp_write_link(struct msm_dp_cat= alog *msm_dp_catalog, void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state); =20 /* AUX APIs */ -u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog); -int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u= 32 data); -int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, = u32 data); -int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, = bool read); -int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_c= atalog); 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Thu, 07 Nov 2024 16:21:55 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 08 Nov 2024 02:21:38 +0200 Subject: [PATCH 07/14] drm/msm/dp: move/inline ctrl register functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-7-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=42508; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=6vs4VVTq5zrMCMjyBGZf0iNwgEaq9XhuFy/96hAkkls=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmPUxq8NxXDM+x4KswvK92vfH8bzDevZNF0c iaUlVSp8qiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZjwAKCRCLPIo+Aiko 1azKB/97Us/HfWPiJEC+Q44cqmAWMF/c4Uh2zq+CdzSWEhnRUqLTOWnCVIx83S1sE7CJHrDgycG ESQCyIJpDokHX9iyGMXXzxLg5u4y2D/fQWFc5gCAiCS45byKAck75cIP+0tR3u3rSjvJvN0dYHH /SKbiD6bFARety0o//T9p9VM0KxUqsyNV8ealtDWvTD4PF738X9MZmnijY1U/gedFAMDNEbhGg8 KtlVUk5TiSNl7dBsG25LTLoExLI4+5tBLfAegWAprrafmUV5mxP8x3NFvzMZsQjno0zdg850TXd LBz1i0xdkcFgSCCuYQfdlqufxKUX+b4uEH2D9OAJu8GiE2i+ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move CTRL-related functions to dp_ctrl.c, inlining one line wrappers during this process. The enable/disable functions have been split to the enable/disable or enter/exit pairs. The IRQ and HPD related functions are left in dp_catalog.c, pending later cleanup. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 389 +------------------------------ drivers/gpu/drm/msm/dp/dp_catalog.h | 22 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 447 ++++++++++++++++++++++++++++++++= ---- 3 files changed, 409 insertions(+), 449 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index bed2c26f883e92319721ed8bd672eb395cbf0544..7c65eba867733cf532831f54639= f23aa5605c35a 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -18,8 +18,6 @@ #define POLLING_SLEEP_US 1000 #define POLLING_TIMEOUT_US 10000 =20 -#define SCRAMBLER_RESET_COUNT_VALUE 0xFC - #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 =20 @@ -93,217 +91,6 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *m= sm_dp_catalog) =20 } =20 -/* controller related catalog functions */ -void msm_dp_catalog_ctrl_update_transfer_unit(struct msm_dp_catalog *msm_d= p_catalog, - u32 msm_dp_tu, u32 valid_boundary, - u32 valid_boundary2) -{ - msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(msm_dp_catalog, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(msm_dp_catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary= 2); -} - -void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog,= u32 state) -{ - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, state); -} - -void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog= , u32 cfg) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - drm_dbg_dp(catalog->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", cfg); - - msm_dp_write_link(msm_dp_catalog, REG_DP_CONFIGURATION_CTRL, cfg); -} - -void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalo= g) -{ - u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ - u32 ln_mapping; - - ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; - ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; - ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; - ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; - - msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, - ln_mapping); -} - -void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog *msm_dp= _catalog, - bool enable) -{ - u32 val; - - val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - - if (enable) - val |=3D DP_MAINLINK_CTRL_ENABLE; - else - val &=3D ~DP_MAINLINK_CTRL_ENABLE; - - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); -} - -void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catal= og, - bool enable) -{ - u32 mainlink_ctrl; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - drm_dbg_dp(catalog->drm_dev, "enable=3D%d\n", enable); - if (enable) { - /* - * To make sure link reg writes happens before other operation, - * msm_dp_write_link() function uses writel() - */ - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - - mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - - mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - - mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - - mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | - DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - } else { - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); - } -} - -void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog, - u32 colorimetry_cfg, - u32 test_bits_depth) -{ - u32 misc_val; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - misc_val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - /* clear bpp bits */ - misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); - misc_val |=3D colorimetry_cfg << DP_MISC0_COLORIMETRY_CFG_SHIFT; - misc_val |=3D test_bits_depth << DP_MISC0_TEST_BITS_DEPTH_SHIFT; - /* Configure clock to synchronous mode */ - misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; - - drm_dbg_dp(catalog->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc_val); -} - -void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog) -{ - u32 mainlink_ctrl, hw_revision; - - mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - - hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); - if (hw_revision >=3D DP_HW_VERSION_1_2) - mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; - else - mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; - - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); -} - -void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, - u32 rate, u32 stream_rate_khz, - bool is_ycbcr_420) -{ - u32 pixel_m, pixel_n; - u32 mvid, nvid, pixel_div =3D 0, dispcc_input_rate; - u32 const nvid_fixed =3D DP_LINK_CONSTANT_N_VALUE; - u32 const link_rate_hbr2 =3D 540000; - u32 const link_rate_hbr3 =3D 810000; - unsigned long den, num; - - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - if (rate =3D=3D link_rate_hbr3) - pixel_div =3D 6; - else if (rate =3D=3D 162000 || rate =3D=3D 270000) - pixel_div =3D 2; - else if (rate =3D=3D link_rate_hbr2) - pixel_div =3D 4; - else - DRM_ERROR("Invalid pixel mux divider\n"); - - dispcc_input_rate =3D (rate * 10) / pixel_div; - - rational_best_approximation(dispcc_input_rate, stream_rate_khz, - (unsigned long)(1 << 16) - 1, - (unsigned long)(1 << 16) - 1, &den, &num); - - den =3D ~(den - num); - den =3D den & 0xFFFF; - pixel_m =3D num; - pixel_n =3D den; - - mvid =3D (pixel_m & 0xFFFF) * 5; - nvid =3D (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); - - if (nvid < nvid_fixed) { - u32 temp; - - temp =3D (nvid_fixed / nvid) * nvid; - mvid =3D (nvid_fixed / nvid) * mvid; - nvid =3D temp; - } - - if (is_ycbcr_420) - mvid /=3D 2; - - if (link_rate_hbr2 =3D=3D rate) - nvid *=3D 2; - - if (link_rate_hbr3 =3D=3D rate) - nvid *=3D 3; - - drm_dbg_dp(catalog->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(msm_dp_catalog, REG_DP_SOFTWARE_NVID, nvid); - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0); -} - -int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, - u32 state_bit) -{ - int bit, ret; - u32 data; - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - bit =3D BIT(state_bit - 1); - drm_dbg_dp(catalog->drm_dev, "hw: bit=3D%d train=3D%d\n", bit, state_bit); - msm_dp_catalog_ctrl_state_ctrl(msm_dp_catalog, bit); - - bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; - - /* Poll for mainlink ready status */ - ret =3D readx_poll_timeout(readl, msm_dp_catalog->link_base + - REG_DP_MAINLINK_READY, - data, data & bit, - POLLING_SLEEP_US, POLLING_TIMEOUT_US); - if (ret < 0) { - DRM_ERROR("set state_bit for link_train=3D%d failed\n", state_bit); - return ret; - } - return 0; -} - /** * msm_dp_catalog_hw_revision() - retrieve DP hw revision * @@ -317,50 +104,6 @@ u32 msm_dp_catalog_hw_revision(const struct msm_dp_cat= alog *msm_dp_catalog) return msm_dp_read_ahb(msm_dp_catalog, REG_DP_HW_VERSION); } =20 -/** - * msm_dp_catalog_ctrl_reset() - reset DP controller - * - * @msm_dp_catalog: DP catalog structure - * - * return: void - * - * This function reset the DP controller - * - * NOTE: reset DP controller will also clear any pending HPD related inter= rupts - *=20 - */ -void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 sw_reset; - - sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); - - sw_reset |=3D DP_SW_RESET; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); - usleep_range(1000, 1100); /* h/w recommended delay */ - - sw_reset &=3D ~DP_SW_RESET; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); -} - -bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log) -{ - u32 data; - int ret; - - /* Poll for mainlink ready status */ - ret =3D readl_poll_timeout(msm_dp_catalog->link_base + - REG_DP_MAINLINK_READY, - data, data & DP_MAINLINK_READY_FOR_VIDEO, - POLLING_SLEEP_US, POLLING_TIMEOUT_US); - if (ret < 0) { - DRM_ERROR("mainlink not ready\n"); - return false; - } - - return true; -} - void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, bool enable) { @@ -413,43 +156,6 @@ void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_cat= alog *msm_dp_catalog) msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); } =20 -static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog *msm_dp_catalo= g) -{ - /* trigger sdp */ - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); -} - -void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 config; - - /* enable PSR1 function */ - config =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); - config |=3D PSR1_SUPPORTED; - msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, config); - - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); - msm_dp_catalog_enable_sdp(msm_dp_catalog); -} - -void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bo= ol enter) -{ - u32 cmd; - - cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); - - cmd &=3D ~(PSR_ENTER | PSR_EXIT); - - if (enter) - cmd |=3D PSR_ENTER; - else - cmd |=3D PSR_EXIT; - - msm_dp_catalog_enable_sdp(msm_dp_catalog); - msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); -} - u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) { struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, @@ -495,6 +201,11 @@ u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(stru= ct msm_dp_catalog *msm_dp_ return intr; } =20 +void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog) +{ + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); +} + int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g) { u32 intr, intr_ack; @@ -509,96 +220,6 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_ca= talog *msm_dp_catalog) return intr; } =20 -void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog) -{ - msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, - DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); - usleep_range(1000, 1100); /* h/w recommended delay */ - msm_dp_write_ahb(msm_dp_catalog, REG_DP_PHY_CTRL, 0x0); -} - -void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_ca= talog, - u32 pattern) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 value =3D 0x0; - - /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); - - drm_dbg_dp(catalog->drm_dev, "pattern: %#x\n", pattern); - switch (pattern) { - case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN1); - break; - case DP_PHY_TEST_PATTERN_ERROR_COUNT: - value &=3D ~(1 << 16); - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - break; - case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_PRBS7); - break; - case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); - /* 00111110000011111000001111100000 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, - 0x3E0F83E0); - /* 00001111100000111110000011111000 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, - 0x0F83E0F8); - /* 1111100000111110 */ - msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, - 0x0000F83E); - break; - case DP_PHY_TEST_PATTERN_CP2520: - value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); - - value =3D DP_HBR2_ERM_PATTERN; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - value |=3D SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); - value |=3D DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); - break; - case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN4); - break; - default: - drm_dbg_dp(catalog->drm_dev, - "No valid test pattern requested: %#x\n", pattern); - break; - } -} - -u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog) -{ - return msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_READY); -} - /* panel related catalog functions */ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, u32 sync_start, u32 width_blanking, u32 msm_dp_active) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index fbcaf1fba66e7c5918137f7f8092f0749dd4da8c..ad3c6bfbd8bb449d7bee92b55b7= 4ddddd1ce4ed0 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -136,37 +136,17 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *m= sm_dp_catalog, struct msm_d u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog); =20 /* DP Controller APIs */ -void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog,= u32 state); -void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog= , u32 config); -void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalo= g); -void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catal= og, bool enable); -void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog *msm_dp= _catalog, bool enable); -void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_c= atalog); -void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog= , u32 cc, u32 tb); -void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog,= u32 rate, - u32 stream_rate_khz, bool is_ycbcr_420); -int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_d= p_catalog, u32 pattern); u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog= ); -void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog); -bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_cata= log); void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,= bool enable); void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, u32 intr_mask, bool en); void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog); void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog= ); -void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog); -void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bo= ol enter); u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog= ); u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og); -void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog); int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g); +void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); -void msm_dp_catalog_ctrl_update_transfer_unit(struct msm_dp_catalog *msm_d= p_catalog, - u32 msm_dp_tu, u32 valid_boundary, - u32 valid_boundary2); -void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_ca= talog, - u32 pattern); -u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_cat= alog); =20 /* DP Panel APIs */ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index bc2ca8133b790fc049e18ab3b37a629558664dd4..6ca2e055717b55c9eb064887948= cf095fbfc1c40 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -8,9 +8,11 @@ #include #include #include +#include #include #include #include +#include =20 #include #include @@ -20,6 +22,9 @@ #include "dp_ctrl.h" #include "dp_link.h" =20 +#define POLLING_SLEEP_US 1000 +#define POLLING_TIMEOUT_US 10000 + #define DP_KHZ_TO_HZ 1000 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms = */ #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /= * 300 ms */ @@ -118,6 +123,114 @@ static int msm_dp_aux_link_configure(struct drm_dp_au= x *aux, return 0; } =20 +/* + * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts + */ +static void msm_dp_ctrl_reset(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 sw_reset; + + sw_reset =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_SW_RESET); + + sw_reset |=3D DP_SW_RESET; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); + usleep_range(1000, 1100); /* h/w recommended delay */ + + sw_reset &=3D ~DP_SW_RESET; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); +} + +static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 val; + + val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + val |=3D DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); +} + +static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *c= trl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 val; + + val =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + val &=3D ~DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, val); +} + +static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 mainlink_ctrl; + + drm_dbg_dp(ctrl->drm_dev, "enable\n"); + + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + + mainlink_ctrl &=3D ~(DP_MAINLINK_CTRL_RESET | + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl |=3D DP_MAINLINK_CTRL_RESET; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_RESET; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + + mainlink_ctrl |=3D (DP_MAINLINK_CTRL_ENABLE | + DP_MAINLINK_FB_BOUNDARY_SEL); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + +static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 mainlink_ctrl; + + drm_dbg_dp(ctrl->drm_dev, "disable\n"); + + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + +static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 mainlink_ctrl, hw_revision; + + mainlink_ctrl =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + + hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); + if (hw_revision >=3D DP_HW_VERSION_1_2) + mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; + else + mainlink_ctrl |=3D DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; + + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + +static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 data; + int ret; + + /* Poll for mainlink ready status */ + ret =3D readl_poll_timeout(msm_dp_catalog->link_base + REG_DP_MAINLINK_RE= ADY, + data, data & DP_MAINLINK_READY_FOR_VIDEO, + POLLING_SLEEP_US, POLLING_TIMEOUT_US); + if (ret < 0) { + DRM_ERROR("mainlink not ready\n"); + return false; + } + + return true; +} + void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -125,7 +238,7 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_c= trl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 reinit_completion(&ctrl->idle_comp); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_ID= LE); =20 if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -170,23 +283,51 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctr= l_private *ctrl) if (ctrl->panel->psr_cap.version) config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; =20 - msm_dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); + drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", config); + + msm_dp_write_link(ctrl->catalog, REG_DP_CONFIGURATION_CTRL, config); +} + +static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ + u32 ln_mapping; + + ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; + ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; + ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; + ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; + + msm_dp_write_link(msm_dp_catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + ln_mapping); } =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) { - u32 cc, tb; + u32 colorimetry_cfg, test_bits_depth, misc_val; =20 - msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog); - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); - msm_dp_catalog_setup_peripheral_flush(ctrl->catalog); + msm_dp_ctrl_lane_mapping(ctrl); + msm_dp_ctrl_mainlink_enable(ctrl); + msm_dp_setup_peripheral_flush(ctrl); =20 msm_dp_ctrl_config_ctrl(ctrl); =20 - tb =3D msm_dp_link_get_test_bits_depth(ctrl->link, - ctrl->panel->msm_dp_mode.bpp); - cc =3D msm_dp_link_get_colorimetry_config(ctrl->link); - msm_dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); + test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); + colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); + + misc_val =3D msm_dp_read_link(ctrl->catalog, REG_DP_MISC1_MISC0); + + /* clear bpp bits */ + misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); + misc_val |=3D colorimetry_cfg << DP_MISC0_COLORIMETRY_CFG_SHIFT; + misc_val |=3D test_bits_depth << DP_MISC0_TEST_BITS_DEPTH_SHIFT; + /* Configure clock to synchronous mode */ + misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; + + drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); + msm_dp_write_link(ctrl->catalog, REG_DP_MISC1_MISC0, misc_val); + msm_dp_panel_timing_cfg(ctrl->panel); } =20 @@ -1003,8 +1144,9 @@ static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_c= trl_private *ctrl) pr_debug("dp_tu=3D0x%x, valid_boundary=3D0x%x, valid_boundary2=3D0x%x\n", msm_dp_tu, valid_boundary, valid_boundary2); =20 - msm_dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, - msm_dp_tu, valid_boundary, valid_boundary2); + msm_dp_write_link(ctrl->catalog, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(ctrl->catalog, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(ctrl->catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2= ); } =20 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) @@ -1114,6 +1256,30 @@ static int msm_dp_ctrl_read_link_status(struct msm_d= p_ctrl_private *ctrl, return ret; } =20 +static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *c= trl, + u32 state_bit) +{ + int bit, ret; + u32 data; + + bit =3D BIT(state_bit - 1); + drm_dbg_dp(ctrl->drm_dev, "hw: bit=3D%d train=3D%d\n", bit, state_bit); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, bit); + + bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; + + /* Poll for mainlink ready status */ + ret =3D readx_poll_timeout(readl, ctrl->catalog->link_base + REG_DP_MAINL= INK_READY, + data, data & bit, + POLLING_SLEEP_US, POLLING_TIMEOUT_US); + if (ret < 0) { + DRM_ERROR("set state_bit for link_train=3D%d failed\n", state_bit); + return ret; + } + + return 0; +} + static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, int *training_step) { @@ -1121,11 +1287,11 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_c= trl_private *ctrl, u8 link_status[DP_LINK_STATUS_SIZE]; int const maximum_retries =3D 4; =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_1; =20 - ret =3D msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); + ret =3D msm_dp_ctrl_set_pattern_state_bit(ctrl, 1); if (ret) return ret; msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | @@ -1228,7 +1394,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctr= l_private *ctrl, int const maximum_retries =3D 5; u8 link_status[DP_LINK_STATUS_SIZE]; =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 *training_step =3D DP_TRAINING_2; =20 @@ -1243,7 +1409,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctr= l_private *ctrl, state_ctrl_bit =3D 2; } =20 - ret =3D msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ct= rl_bit); + ret =3D msm_dp_ctrl_set_pattern_state_bit(ctrl, state_ctrl_bit); if (ret) return ret; =20 @@ -1321,7 +1487,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n"); =20 end: - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 return ret; } @@ -1331,7 +1497,7 @@ static int msm_dp_ctrl_setup_main_link(struct msm_dp_= ctrl_private *ctrl, { int ret =3D 0; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); + msm_dp_ctrl_mainlink_enable(ctrl); =20 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) return ret; @@ -1470,7 +1636,7 @@ void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *m= sm_dp_ctrl, bool enable) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - msm_dp_catalog_ctrl_reset(ctrl->catalog); + msm_dp_ctrl_reset(ctrl); =20 /* * all dp controller programmable registers will not @@ -1481,16 +1647,60 @@ void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl = *msm_dp_ctrl, bool enable) msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); } =20 +static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + /* trigger sdp */ + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x0); +} + +static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 cmd; + + cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); + + cmd &=3D ~(PSR_ENTER | PSR_EXIT); + cmd |=3D PSR_ENTER; + + msm_dp_ctrl_enable_sdp(ctrl); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); +} + +static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 cmd; + + cmd =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CMD); + + cmd &=3D ~(PSR_ENTER | PSR_EXIT); + cmd |=3D PSR_EXIT; + + msm_dp_ctrl_enable_sdp(ctrl); + msm_dp_write_link(msm_dp_catalog, REG_PSR_CMD, cmd); +} + void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) { - u8 cfg; struct msm_dp_ctrl_private *ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 cfg; =20 if (!ctrl->panel->psr_cap.version) return; =20 - msm_dp_catalog_ctrl_config_psr(ctrl->catalog); + /* enable PSR1 function */ + cfg =3D msm_dp_read_link(msm_dp_catalog, REG_PSR_CONFIG); + cfg |=3D PSR1_SUPPORTED; + msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, cfg); + + msm_dp_catalog_ctrl_config_psr_interrupt(msm_dp_catalog); + msm_dp_ctrl_enable_sdp(ctrl); =20 cfg =3D DP_PSR_ENABLE; drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); @@ -1516,29 +1726,37 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp= _ctrl, bool enter) */ if (enter) { reinit_completion(&ctrl->psr_op_comp); - msm_dp_catalog_ctrl_set_psr(ctrl->catalog, true); + msm_dp_ctrl_psr_enter(ctrl); =20 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) { DRM_ERROR("PSR_ENTRY timedout\n"); - msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); + msm_dp_ctrl_psr_exit(ctrl); return; } =20 msm_dp_ctrl_push_idle(msm_dp_ctrl); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); =20 - msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false); + msm_dp_ctrl_psr_mainlink_disable(ctrl); } else { - msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true); + msm_dp_ctrl_psr_mainlink_enable(ctrl); =20 - msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_ctrl_psr_exit(ctrl); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_V= IDEO); msm_dp_ctrl_wait4video_ready(ctrl); - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, 0); } } =20 +static void msm_dp_ctrl_phy_reset(struct msm_dp_ctrl_private *ctrl) +{ + msm_dp_write_ahb(ctrl->catalog, REG_DP_PHY_CTRL, + DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); + usleep_range(1000, 1100); /* h/w recommended delay */ + msm_dp_write_ahb(ctrl->catalog, REG_DP_PHY_CTRL, 0x0); +} + void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; @@ -1547,7 +1765,7 @@ void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); + msm_dp_ctrl_phy_reset(ctrl); phy_init(phy); =20 drm_dbg_dp(ctrl->drm_dev, "phy=3D%p init=3D%d power_on=3D%d\n", @@ -1562,7 +1780,7 @@ void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); + msm_dp_ctrl_phy_reset(ctrl); phy_exit(phy); drm_dbg_dp(ctrl->drm_dev, "phy=3D%p init=3D%d power_on=3D%d\n", phy, phy->init_count, phy->power_count); @@ -1573,7 +1791,7 @@ static int msm_dp_ctrl_reinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) struct phy *phy =3D ctrl->phy; int ret =3D 0; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); ctrl->phy_opts.dp.lanes =3D ctrl->link->link_params.num_lanes; phy_configure(phy, &ctrl->phy_opts); /* @@ -1604,9 +1822,9 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) =20 phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_catalog_ctrl_reset(ctrl->catalog); + msm_dp_ctrl_reset(ctrl); =20 dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -1638,13 +1856,97 @@ static int msm_dp_ctrl_link_maintenance(struct msm_= dp_ctrl_private *ctrl) =20 msm_dp_ctrl_clear_training_pattern(ctrl); =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VI= DEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); end: return ret; } =20 +#define SCRAMBLER_RESET_COUNT_VALUE 0xFC + +static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, + u32 pattern) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 value =3D 0x0; + + /* Make sure to clear the current pattern before starting a new one */ + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, 0x0); + + drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); + switch (pattern) { + case DP_PHY_TEST_PATTERN_D10_2: + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN1); + break; + + case DP_PHY_TEST_PATTERN_ERROR_COUNT: + value &=3D ~(1 << 16); + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + value |=3D SCRAMBLER_RESET_COUNT_VALUE; + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + break; + + case DP_PHY_TEST_PATTERN_PRBS7: + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_PRBS7); + break; + + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); + /* 00111110000011111000001111100000 */ + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + 0x3E0F83E0); + /* 00001111100000111110000011111000 */ + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + 0x0F83E0F8); + /* 1111100000111110 */ + msm_dp_write_link(msm_dp_catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + 0x0000F83E); + break; + + case DP_PHY_TEST_PATTERN_CP2520: + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + value &=3D ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); + + value =3D DP_HBR2_ERM_PATTERN; + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + value |=3D SCRAMBLER_RESET_COUNT_VALUE; + msm_dp_write_link(msm_dp_catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + value =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL); + value |=3D DP_MAINLINK_CTRL_ENABLE; + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, value); + break; + + case DP_PHY_TEST_PATTERN_SEL_MASK: + msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_CTRL, + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(msm_dp_catalog, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN4); + break; + + default: + drm_dbg_dp(ctrl->drm_dev, + "No valid test pattern requested: %#x\n", pattern); + break; + } +} + static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *= ctrl) { bool success =3D false; @@ -1659,11 +1961,11 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struc= t msm_dp_ctrl_private *ctrl) DRM_ERROR("Failed to set v/p levels\n"); return false; } - msm_dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); + msm_dp_ctrl_send_phy_pattern(ctrl, pattern_requested); msm_dp_ctrl_update_vx_px(ctrl); msm_dp_link_send_test_response(ctrl->link); =20 - pattern_sent =3D msm_dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); + pattern_sent =3D msm_dp_read_link(ctrl->catalog, REG_DP_MAINLINK_READY); =20 switch (pattern_sent) { case MR_LINK_TRAINING1: @@ -1942,6 +2244,63 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ct= rl_private *ctrl) return msm_dp_ctrl_setup_main_link(ctrl, &training_step); } =20 +static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, + u32 rate, u32 stream_rate_khz, + bool is_ycbcr_420) +{ + u32 pixel_m, pixel_n; + u32 mvid, nvid, pixel_div =3D 0, dispcc_input_rate; + u32 const nvid_fixed =3D DP_LINK_CONSTANT_N_VALUE; + u32 const link_rate_hbr2 =3D 540000; + u32 const link_rate_hbr3 =3D 810000; + unsigned long den, num; + + if (rate =3D=3D link_rate_hbr3) + pixel_div =3D 6; + else if (rate =3D=3D 162000 || rate =3D=3D 270000) + pixel_div =3D 2; + else if (rate =3D=3D link_rate_hbr2) + pixel_div =3D 4; + else + DRM_ERROR("Invalid pixel mux divider\n"); + + dispcc_input_rate =3D (rate * 10) / pixel_div; + + rational_best_approximation(dispcc_input_rate, stream_rate_khz, + (unsigned long)(1 << 16) - 1, + (unsigned long)(1 << 16) - 1, &den, &num); + + den =3D ~(den - num); + den =3D den & 0xFFFF; + pixel_m =3D num; + pixel_n =3D den; + + mvid =3D (pixel_m & 0xFFFF) * 5; + nvid =3D (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); + + if (nvid < nvid_fixed) { + u32 temp; + + temp =3D (nvid_fixed / nvid) * nvid; + mvid =3D (nvid_fixed / nvid) * mvid; + nvid =3D temp; + } + + if (is_ycbcr_420) + mvid /=3D 2; + + if (link_rate_hbr2 =3D=3D rate) + nvid *=3D 2; + + if (link_rate_hbr3 =3D=3D rate) + nvid *=3D 3; + + drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); + msm_dp_write_link(ctrl->catalog, REG_DP_SOFTWARE_MVID, mvid); + msm_dp_write_link(ctrl->catalog, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_p0(ctrl->catalog, MMSS_DP_DSC_DTO, 0x0); +} + int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) { int ret =3D 0; @@ -2007,20 +2366,20 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train =20 msm_dp_ctrl_configure_source_params(ctrl); =20 - msm_dp_catalog_ctrl_config_msa(ctrl->catalog, + msm_dp_ctrl_config_msa(ctrl, ctrl->link->link_params.rate, pixel_rate_orig, ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 - msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl->catalog, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VI= DEO); =20 ret =3D msm_dp_ctrl_wait4video_ready(ctrl); if (ret) return ret; =20 - mainlink_ready =3D msm_dp_catalog_ctrl_mainlink_ready(ctrl->catalog); + mainlink_ready =3D msm_dp_ctrl_mainlink_ready(ctrl); drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); =20 @@ -2041,7 +2400,7 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *= msm_dp_ctrl) /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 if (ctrl->stream_clks_on) { clk_disable_unprepare(ctrl->pixel_clk); @@ -2069,7 +2428,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 @@ -2092,9 +2451,9 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) =20 msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); =20 - msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_catalog_ctrl_reset(ctrl->catalog); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-8-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13699; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=MTfEFFP/YbgFD6Q1EMt0bPgAfYwHBAnPO/xY6iNsytQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmP5BnpPW8F4Q8abGp0tLLh0/E1WTuuBwoEd W3AftzNYKiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZjwAKCRCLPIo+Aiko 1Q9+B/4jhzy6SRxT38CQUPjduKqxDMj7G1y0hmqoOp+U7ixcCQM30bqXXOyJ52Pu+zWitG9DwqC VK6OSsgnVwmq/tAu/VHkWKKL0peJwI4OSeWhnR2YGcup4W3QaFZ4TG1GmrPXFE3J2UZU6O86tFa XBQeCreYJvhNysRhV+88koinZXVcd6BZq1lwyf1RL69pnDArpGzH/ZOXuvOKyzt+kC84Agf4iRM ydy6r8GMO8t/UUfQ13PUt1oTgbWXYvukmH0X02Am+V3jYPCfRMBrMdYzHwxEM36ve0MK0R6A7tX Eso9nGBT9eHrXlZXFc1lfpbFLy6do6EHnWaDOIpYtsCRYR32 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move panel-related functions to dp_panel.c, following up the cleanup done by the rest of the submodules. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_catalog.c | 114 --------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 6 -- drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 +- drivers/gpu/drm/msm/dp/dp_panel.c | 114 ++++++++++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/dp/dp_panel.h | 3 + 5 files changed, 113 insertions(+), 128 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 7c65eba867733cf532831f54639f23aa5605c35a..9c12484589dc38951a3f1cb4bb3= 3eb9aa5822d87 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -21,8 +21,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 =20 -#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) - #define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_XFER_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -220,118 +218,6 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_c= atalog *msm_dp_catalog) return intr; } =20 -/* panel related catalog functions */ -int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, - u32 sync_start, u32 width_blanking, u32 msm_dp_active) -{ - u32 reg; - - msm_dp_write_link(msm_dp_catalog, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(msm_dp_catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_st= art); - msm_dp_write_link(msm_dp_catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, widt= h_blanking); - msm_dp_write_link(msm_dp_catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); - - reg =3D msm_dp_read_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG); - - if (msm_dp_catalog->wide_bus_en) - reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; - else - reg &=3D ~DP_INTF_CONFIG_DATABUS_WIDEN; - - - DRM_DEBUG_DP("wide_bus_en=3D%d reg=3D%#x\n", msm_dp_catalog->wide_bus_en,= reg); - - msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG, reg); - return 0; -} - -static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_d= p_catalog, struct dp_sdp *vsc_sdp) -{ - u32 header[2]; - u32 val; - int i; - - msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); - - for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { - val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | - (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); - } -} - -static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_= catalog) -{ - u32 hw_revision; - - hw_revision =3D msm_dp_catalog_hw_revision(msm_dp_catalog); - if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >=3D DP_HW_VERSION_1_0= ) { - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x01); - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x00); - } -} - -void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp) -{ - struct msm_dp_catalog_private *catalog; - u32 cfg, cfg2, misc; - - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); - - cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); - - msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp); - - /* indicates presence of VSC (BIT(6) of MISC1) */ - misc |=3D DP_MISC1_VSC_SDP; - - drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D1\n"); - - pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); - - msm_dp_catalog_panel_update_sdp(msm_dp_catalog); -} - -void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog) -{ - struct msm_dp_catalog_private *catalog; - u32 cfg, cfg2, misc; - - catalog =3D container_of(msm_dp_catalog, struct msm_dp_catalog_private, m= sm_dp_catalog); - - cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); - - cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); - - cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); - - /* switch back to MSA */ - misc &=3D ~DP_MISC1_VSC_SDP; - - drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=3D0\n"); - - pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); - - msm_dp_catalog_panel_update_sdp(msm_dp_catalog); -} - static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index ad3c6bfbd8bb449d7bee92b55b74ddddd1ce4ed0..8b63f53e960092666f08b95f556= aefe210f4a1e0 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -148,12 +148,6 @@ int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_ca= talog *msm_dp_catalog); void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); =20 -/* DP Panel APIs */ -int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,= u32 total, - u32 sync_start, u32 width_blanking, u32 msm_dp_active); -void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_cat= alog, struct dp_sdp *vsc_sdp); -void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_ca= talog); - struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 /* DP Audio APIs */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 6ca2e055717b55c9eb064887948cf095fbfc1c40..cde667bf8eeec95035b2feb3661= 686c99acf5b7d 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2395,7 +2395,7 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *= msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); + msm_dp_panel_disable_vsc_sdp(ctrl->panel); =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); @@ -2449,7 +2449,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); + msm_dp_panel_disable_vsc_sdp(ctrl->panel); =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 7a5656d8702e4f9c6f8e13d00788a5bdbbe3729f..7903606fc9c249b4ec21949fe51= 240df90492103 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -4,6 +4,7 @@ */ =20 #include "dp_panel.h" +#include "dp_reg.h" #include "dp_utils.h" =20 #include @@ -11,6 +12,8 @@ #include #include =20 +#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) + #define DP_MAX_NUM_DP_LANES 4 #define DP_LINK_RATE_HBR2 540000 /* kbytes */ =20 @@ -242,10 +245,97 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_p= anel *msm_dp_panel) } } =20 +static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) +{ + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 header[2]; + u32 val; + int i; + + msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); + + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]); + + for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { + val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | + (vsc_sdp->db[i + 3] << 24)); + msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val); + } +} + +static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) +{ + u32 hw_revision; + + hw_revision =3D msm_dp_catalog_hw_revision(panel->catalog); + if (hw_revision >=3D DP_HW_VERSION_1_0 && + hw_revision < DP_HW_VERSION_1_2) { + msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, 0x0); + } +} + +void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct= dp_sdp *vsc_sdp) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 cfg, cfg2, misc; + + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + + cfg |=3D GEN0_SDP_EN; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 |=3D GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + + msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); + + /* indicates presence of VSC (BIT(6) of MISC1) */ + misc |=3D DP_MISC1_VSC_SDP; + + drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); + + pr_debug("misc settings =3D 0x%x\n", misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + + msm_dp_panel_update_sdp(panel); +} + +void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_panel_private *panel =3D + container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + struct msm_dp_catalog *msm_dp_catalog =3D panel->catalog; + u32 cfg, cfg2, misc; + + cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + misc =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0); + + cfg &=3D ~GEN0_SDP_EN; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2); + + /* switch back to MSA */ + misc &=3D ~DP_MISC1_VSC_SDP; + + drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); + + pr_debug("misc settings =3D 0x%x\n", misc); + msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc); + + msm_dp_panel_update_sdp(panel); +} + static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_= panel) { - struct msm_dp_catalog *catalog; - struct msm_dp_panel_private *panel; struct msm_dp_display_mode *msm_dp_mode; struct drm_dp_vsc_sdp vsc_sdp_data; struct dp_sdp vsc_sdp; @@ -256,8 +346,6 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct ms= m_dp_panel *msm_dp_panel) return -EINVAL; } =20 - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - catalog =3D panel->catalog; msm_dp_mode =3D &msm_dp_panel->msm_dp_mode; =20 memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); @@ -284,7 +372,7 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct ms= m_dp_panel *msm_dp_panel) return len; } =20 - msm_dp_catalog_panel_enable_vsc_sdp(catalog, &vsc_sdp); + msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp); =20 return 0; } @@ -299,6 +387,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel) u32 sync_start; u32 msm_dp_active; u32 total; + u32 reg; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); catalog =3D panel->catalog; @@ -344,7 +433,20 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_d= p_panel) =20 msm_dp_active =3D data; =20 - msm_dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blankin= g, msm_dp_active); + msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); + msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); + msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blank= ing); + msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + + reg =3D msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); + if (catalog->wide_bus_en) + reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; + else + reg &=3D ~DP_INTF_CONFIG_DATABUS_WIDEN; + + drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", catalog->wide_= bus_en, reg); + + msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 317e2a13d7e917acd78edd2f1c99c4be3de902bd..332ac79594e71157e2b087dc526= 8c50a87993d83 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -63,6 +63,9 @@ int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_pa= nel, struct drm_connector *connector); void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); 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Thu, 07 Nov 2024 16:22:01 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 08 Nov 2024 02:21:40 +0200 Subject: [PATCH 09/14] drm/msm/dp: use msm_dp_utils_pack_sdp_header() for audio packets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-9-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11581; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=2xr4AL7j+40V0HqRu7/QUTdkPIotaD3OUYFdYvPlgFw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmPbcqrHin1BWlLlxr1h1IaIZdYs1YeD2J4Q ejcoscvZEOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZjwAKCRCLPIo+Aiko 1QQhCACMrfq2itfjx1n+8mF2IL9fvMTtXuCwZ6k573KjtRpe76G0m6LUeccPCUOYHIqONH2id1n AnEItx/hfWuf6iMDeEA9HDwd+rsxTc/7FLVWNBOEU+0hgeov1nYP5w8iZU9j0l39syGthWKxv+E bJVzT6jnwmPhMQFrLrDxzDa1hAqDIVso0Ao5Sk9fULwG2BwCJ4RK/ZxDMnGQiE2Byx2vZqKHYab WsJMptFzIV8pwTy/eFuEWjohmDXemeq1ICHb/NWovwydxkdG7wQcIzA8SQhXCaaNcqRRYn0AOp2 cvLFpO2Uz9RWzANcN2Ucr+bhW4appMgpqOVkH1C8cbzyfEfW X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Use msm_dp_utils_pack_sdp_header() and call msm_dp_write_link() directly to program audio packet data. Use 0 as Packet ID, as it was not programmed earlier. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_audio.c | 288 +++++++++-------------------------= ---- 1 file changed, 66 insertions(+), 222 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index 74e01a5dd4195d5e0e04250663886f1116f25711..481fb266fffbec5dd96422f4fb7= af8af36acb634 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -14,6 +14,7 @@ #include "dp_catalog.h" #include "dp_audio.h" #include "dp_panel.h" +#include "dp_reg.h" #include "dp_display.h" #include "dp_utils.h" =20 @@ -28,251 +29,94 @@ struct msm_dp_audio_private { struct msm_dp_audio msm_dp_audio; }; =20 -static u32 msm_dp_audio_get_header(struct msm_dp_catalog *catalog, - enum msm_dp_catalog_audio_sdp_type sdp, - enum msm_dp_catalog_audio_header_type header) -{ - return msm_dp_catalog_audio_get_header(catalog, sdp, header); -} - -static void msm_dp_audio_set_header(struct msm_dp_catalog *catalog, - u32 data, - enum msm_dp_catalog_audio_sdp_type sdp, - enum msm_dp_catalog_audio_header_type header) -{ - msm_dp_catalog_audio_set_header(catalog, sdp, header, data); -} - static void msm_dp_audio_stream_sdp(struct msm_dp_audio_private *audio) { struct msm_dp_catalog *catalog =3D audio->catalog; - u32 value, new_value; - u8 parity_byte; - - /* Config header and parity byte 1 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_1); - - new_value =3D 0x02; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_1_BIT) - | (parity_byte << PARITY_BYTE_1_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 1: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_1); - - /* Config header and parity byte 2 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_2); - new_value =3D value; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_2_BIT) - | (parity_byte << PARITY_BYTE_2_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 2: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_2); - - /* Config header and parity byte 3 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_3); - - new_value =3D audio->channels - 1; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_3_BIT) - | (parity_byte << PARITY_BYTE_3_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 3: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_3); + struct dp_sdp_header sdp_hdr =3D { + .HB0 =3D 0x00, + .HB1 =3D 0x02, + .HB2 =3D 0x00, + .HB3 =3D audio->channels - 1, + }; + u32 header[2]; + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); + + msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_STREAM_1, header[1]); } =20 static void msm_dp_audio_timestamp_sdp(struct msm_dp_audio_private *audio) { struct msm_dp_catalog *catalog =3D audio->catalog; - u32 value, new_value; - u8 parity_byte; - - /* Config header and parity byte 1 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_1); - - new_value =3D 0x1; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_1_BIT) - | (parity_byte << PARITY_BYTE_1_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 1: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_1); - - /* Config header and parity byte 2 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_2); - - new_value =3D 0x17; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_2_BIT) - | (parity_byte << PARITY_BYTE_2_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 2: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_2); - - /* Config header and parity byte 3 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_3); - - new_value =3D (0x0 | (0x11 << 2)); - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_3_BIT) - | (parity_byte << PARITY_BYTE_3_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 3: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_3); + struct dp_sdp_header sdp_hdr =3D { + .HB0 =3D 0x00, + .HB1 =3D 0x01, + .HB2 =3D 0x17, + .HB3 =3D 0x0 | (0x11 << 2), + }; + u32 header[2]; + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); + + msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]); } =20 static void msm_dp_audio_infoframe_sdp(struct msm_dp_audio_private *audio) { struct msm_dp_catalog *catalog =3D audio->catalog; - u32 value, new_value; - u8 parity_byte; - - /* Config header and parity byte 1 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_1); - - new_value =3D 0x84; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_1_BIT) - | (parity_byte << PARITY_BYTE_1_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 1: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_1); - - /* Config header and parity byte 2 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_2); - - new_value =3D 0x1b; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_2_BIT) - | (parity_byte << PARITY_BYTE_2_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 2: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_2); - - /* Config header and parity byte 3 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_3); - - new_value =3D (0x0 | (0x11 << 2)); - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_3_BIT) - | (parity_byte << PARITY_BYTE_3_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 3: value =3D 0x%x, parity_byte =3D 0x%x\n", - new_value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_3); + struct dp_sdp_header sdp_hdr =3D { + .HB0 =3D 0x00, + .HB1 =3D 0x84, + .HB2 =3D 0x1b, + .HB3 =3D 0x0 | (0x11 << 2), + }; + u32 header[2]; + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); + + msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_INFOFRAME_1, header[1]); } =20 static void msm_dp_audio_copy_management_sdp(struct msm_dp_audio_private *= audio) { struct msm_dp_catalog *catalog =3D audio->catalog; - u32 value, new_value; - u8 parity_byte; - - /* Config header and parity byte 1 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_1); - - new_value =3D 0x05; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_1_BIT) - | (parity_byte << PARITY_BYTE_1_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 1: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_1); - - /* Config header and parity byte 2 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_2); - - new_value =3D 0x0F; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_2_BIT) - | (parity_byte << PARITY_BYTE_2_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 2: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_2); - - /* Config header and parity byte 3 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_3); - - new_value =3D 0x0; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_3_BIT) - | (parity_byte << PARITY_BYTE_3_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 3: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_3); + struct dp_sdp_header sdp_hdr =3D { + .HB0 =3D 0x00, + .HB1 =3D 0x05, + .HB2 =3D 0x0f, + .HB3 =3D 0x00, + }; + u32 header[2]; + + msm_dp_utils_pack_sdp_header(&sdp_hdr, header); + + msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[0]); + msm_dp_write_link(catalog, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[1]); } =20 static void msm_dp_audio_isrc_sdp(struct msm_dp_audio_private *audio) { struct msm_dp_catalog *catalog =3D audio->catalog; - u32 value, new_value; - u8 parity_byte; - - /* Config header and parity byte 1 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_1); - - new_value =3D 0x06; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_1_BIT) - | (parity_byte << PARITY_BYTE_1_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 1: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_1); - - /* Config header and parity byte 2 */ - value =3D msm_dp_audio_get_header(catalog, - DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_2); - - new_value =3D 0x0F; - parity_byte =3D msm_dp_utils_calculate_parity(new_value); - value |=3D ((new_value << HEADER_BYTE_2_BIT) - | (parity_byte << PARITY_BYTE_2_BIT)); - drm_dbg_dp(audio->drm_dev, - "Header Byte 2: value =3D 0x%x, parity_byte =3D 0x%x\n", - value, parity_byte); - msm_dp_audio_set_header(catalog, value, - DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_2); 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The dp_audio.c now writes them using msm_dp_write_link() directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_audio.c | 2 - drivers/gpu/drm/msm/dp/dp_catalog.c | 76 ---------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 24 ------------ 3 files changed, 102 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index 481fb266fffbec5dd96422f4fb7af8af36acb634..63bdd57948401451426364796e6= 08643c1ebfebe 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -405,8 +405,6 @@ struct msm_dp_audio *msm_dp_audio_get(struct platform_d= evice *pdev, =20 msm_dp_audio =3D &audio->msm_dp_audio; =20 - msm_dp_catalog_audio_init(catalog); - return msm_dp_audio; error: return ERR_PTR(rc); diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 9c12484589dc38951a3f1cb4bb33eb9aa5822d87..5071c86fd219cb1c933b32104a3= 96982c5cc8ace 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -62,7 +62,6 @@ struct msm_dp_catalog_private { struct device *dev; struct drm_device *drm_dev; - u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX]; struct msm_dp_catalog msm_dp_catalog; }; =20 @@ -300,40 +299,6 @@ struct msm_dp_catalog *msm_dp_catalog_get(struct devic= e *dev) return &catalog->msm_dp_catalog; } =20 -u32 msm_dp_catalog_audio_get_header(struct msm_dp_catalog *msm_dp_catalog, - enum msm_dp_catalog_audio_sdp_type sdp, - enum msm_dp_catalog_audio_header_type header) -{ - struct msm_dp_catalog_private *catalog; - u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX]; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - sdp_map =3D catalog->audio_map; - - return msm_dp_read_link(msm_dp_catalog, sdp_map[sdp][header]); -} - -void msm_dp_catalog_audio_set_header(struct msm_dp_catalog *msm_dp_catalog, - enum msm_dp_catalog_audio_sdp_type sdp, - enum msm_dp_catalog_audio_header_type header, - u32 data) -{ - struct msm_dp_catalog_private *catalog; - u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX]; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - sdp_map =3D catalog->audio_map; - - msm_dp_write_link(msm_dp_catalog, sdp_map[sdp][header], data); -} - void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *msm_dp_catalog= , u32 select) { struct msm_dp_catalog_private *catalog; @@ -417,47 +382,6 @@ void msm_dp_catalog_audio_config_sdp(struct msm_dp_cat= alog *msm_dp_catalog) msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); } =20 -void msm_dp_catalog_audio_init(struct msm_dp_catalog *msm_dp_catalog) -{ - struct msm_dp_catalog_private *catalog; - - static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] =3D { - { - MMSS_DP_AUDIO_STREAM_0, - MMSS_DP_AUDIO_STREAM_1, - MMSS_DP_AUDIO_STREAM_1, - }, - { - MMSS_DP_AUDIO_TIMESTAMP_0, - MMSS_DP_AUDIO_TIMESTAMP_1, - MMSS_DP_AUDIO_TIMESTAMP_1, - }, - { - MMSS_DP_AUDIO_INFOFRAME_0, - MMSS_DP_AUDIO_INFOFRAME_1, - MMSS_DP_AUDIO_INFOFRAME_1, - }, - { - MMSS_DP_AUDIO_COPYMANAGEMENT_0, - MMSS_DP_AUDIO_COPYMANAGEMENT_1, - MMSS_DP_AUDIO_COPYMANAGEMENT_1, - }, - { - MMSS_DP_AUDIO_ISRC_0, - MMSS_DP_AUDIO_ISRC_1, - MMSS_DP_AUDIO_ISRC_1, - }, - }; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - catalog->audio_map =3D sdp_map; -} - void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *msm_dp_catalog,= u32 safe_to_exit_level) { struct msm_dp_catalog_private *catalog; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 8b63f53e960092666f08b95f556aefe210f4a1e0..24f1cf4ed5150c4e0e808805886= 41a01bb6a1596 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -31,22 +31,6 @@ #define DP_HW_VERSION_1_0 0x10000000 #define DP_HW_VERSION_1_2 0x10020000 =20 -enum msm_dp_catalog_audio_sdp_type { - DP_AUDIO_SDP_STREAM, - DP_AUDIO_SDP_TIMESTAMP, - DP_AUDIO_SDP_INFOFRAME, - DP_AUDIO_SDP_COPYMANAGEMENT, - DP_AUDIO_SDP_ISRC, - DP_AUDIO_SDP_MAX, -}; - -enum msm_dp_catalog_audio_header_type { - DP_AUDIO_SDP_HEADER_1, - DP_AUDIO_SDP_HEADER_2, - DP_AUDIO_SDP_HEADER_3, - DP_AUDIO_SDP_HEADER_MAX, -}; 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a=openpgp-sha256; l=8606; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=CJNeGuR1/hi3WdAk96FubFXJd9V4K8sajDyAH3cIEjU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmQeBbtYi7rdedJFb/81mfZJGHDrLlk9stC7 4/2bOapZWKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZkAAKCRCLPIo+Aiko 1QYkB/9rDbCubMBn3heGWbrNxPet0AQvpG5JDcMUCKY+A2fLmhT50dnyI5FG7aaiKlly/VMv2ng tTYFVEtg4t/ESTsAcIuc6LOrxxyU4MffokBo7j8shuZd+uwTzNdU1KKAlb3UJDDMDHgFDi4BPln L3t86jimpIlb7CAxHDQOOzoI4cFdxd1ecJwyCtV11y/6xEzSpRV/cQm9KBPDs+8HmsTe8KXxLwz fera0F7J53nL3vEA5D0KbtMWA2sTH98BK64VSXHiXhyf/ScF8VeYzDypgipj1UnUogvgVf6PXu0 SDw51FWsiiTgeKL1ljjUC0aXWdu29osm5Esgd1ZooR1GWr70 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move audio-related functions to dp_audio.c, following up the cleanup done by the rest of the submodules. Inline functions with simple register access patterns. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_audio.c | 72 +++++++++++++++++++++---- drivers/gpu/drm/msm/dp/dp_catalog.c | 105 --------------------------------= ---- drivers/gpu/drm/msm/dp/dp_catalog.h | 6 --- 3 files changed, 63 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index 63bdd57948401451426364796e608643c1ebfebe..63c4cd88edef07c54b2eb54d5b6= ee494ee94723d 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -119,9 +119,41 @@ static void msm_dp_audio_isrc_sdp(struct msm_dp_audio_= private *audio) msm_dp_write_link(catalog, MMSS_DP_AUDIO_ISRC_1, header[1]); } =20 +static void msm_dp_audio_config_sdp(struct msm_dp_audio_private *audio) +{ + struct msm_dp_catalog *msm_dp_catalog =3D audio->catalog; + u32 sdp_cfg, sdp_cfg2; + + sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); + /* AUDIO_TIMESTAMP_SDP_EN */ + sdp_cfg |=3D BIT(1); + /* AUDIO_STREAM_SDP_EN */ + sdp_cfg |=3D BIT(2); + /* AUDIO_COPY_MANAGEMENT_SDP_EN */ + sdp_cfg |=3D BIT(5); + /* AUDIO_ISRC_SDP_EN */ + sdp_cfg |=3D BIT(6); + /* AUDIO_INFOFRAME_SDP_EN */ + sdp_cfg |=3D BIT(20); + + drm_dbg_dp(audio->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); + + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); + + sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); + /* IFRM_REGSRC -> Do not use reg values */ + sdp_cfg2 &=3D ~BIT(0); + /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ + sdp_cfg2 &=3D ~BIT(1); + + drm_dbg_dp(audio->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); + + msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); +} + static void msm_dp_audio_setup_sdp(struct msm_dp_audio_private *audio) { - msm_dp_catalog_audio_config_sdp(audio->catalog); + msm_dp_audio_config_sdp(audio); =20 msm_dp_audio_stream_sdp(audio); msm_dp_audio_timestamp_sdp(audio); @@ -132,8 +164,7 @@ static void msm_dp_audio_setup_sdp(struct msm_dp_audio_= private *audio) =20 static void msm_dp_audio_setup_acr(struct msm_dp_audio_private *audio) { - u32 select =3D 0; - struct msm_dp_catalog *catalog =3D audio->catalog; + u32 select, acr_ctrl; =20 switch (audio->msm_dp_audio.bw_code) { case DP_LINK_BW_1_62: @@ -154,13 +185,17 @@ static void msm_dp_audio_setup_acr(struct msm_dp_audi= o_private *audio) break; } =20 - msm_dp_catalog_audio_config_acr(catalog, select); + acr_ctrl =3D select << 4 | BIT(31) | BIT(8) | BIT(14); + + drm_dbg_dp(audio->drm_dev, "select: %#x, acr_ctrl: %#x\n", + select, acr_ctrl); + + msm_dp_write_link(audio->catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); } =20 static void msm_dp_audio_safe_to_exit_level(struct msm_dp_audio_private *a= udio) { - struct msm_dp_catalog *catalog =3D audio->catalog; - u32 safe_to_exit_level =3D 0; + u32 safe_to_exit_level, mainlink_levels; =20 switch (audio->msm_dp_audio.lane_count) { case 1: @@ -180,14 +215,33 @@ static void msm_dp_audio_safe_to_exit_level(struct ms= m_dp_audio_private *audio) break; } =20 - msm_dp_catalog_audio_sfe_level(catalog, safe_to_exit_level); + mainlink_levels =3D msm_dp_read_link(audio->catalog, REG_DP_MAINLINK_LEVE= LS); + mainlink_levels &=3D 0xFE0; + mainlink_levels |=3D safe_to_exit_level; + + drm_dbg_dp(audio->drm_dev, + "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", + mainlink_levels, safe_to_exit_level); + + msm_dp_write_link(audio->catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels= ); } =20 static void msm_dp_audio_enable(struct msm_dp_audio_private *audio, bool e= nable) { - struct msm_dp_catalog *catalog =3D audio->catalog; + u32 audio_ctrl; + + audio_ctrl =3D msm_dp_read_link(audio->catalog, MMSS_DP_AUDIO_CFG); + + if (enable) + audio_ctrl |=3D BIT(0); + else + audio_ctrl &=3D ~BIT(0); + + drm_dbg_dp(audio->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); =20 - msm_dp_catalog_audio_enable(catalog, enable); + msm_dp_write_link(audio->catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); + /* make sure audio engine is disabled */ + wmb(); } =20 static struct msm_dp_audio_private *msm_dp_audio_get_data(struct platform_= device *pdev) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 5071c86fd219cb1c933b32104a396982c5cc8ace..60ba6e0a204f536fd050591e891= add17d286fb2d 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -298,108 +298,3 @@ struct msm_dp_catalog *msm_dp_catalog_get(struct devi= ce *dev) =20 return &catalog->msm_dp_catalog; } - -void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *msm_dp_catalog= , u32 select) -{ - struct msm_dp_catalog_private *catalog; - u32 acr_ctrl; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - acr_ctrl =3D select << 4 | BIT(31) | BIT(8) | BIT(14); - - drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n", - select, acr_ctrl); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); -} - -void msm_dp_catalog_audio_enable(struct msm_dp_catalog *msm_dp_catalog, bo= ol enable) -{ - struct msm_dp_catalog_private *catalog; - u32 audio_ctrl; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - audio_ctrl =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG); - - if (enable) - audio_ctrl |=3D BIT(0); - else - audio_ctrl &=3D ~BIT(0); - - drm_dbg_dp(catalog->drm_dev, "dp_audio_cfg =3D 0x%x\n", audio_ctrl); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); - /* make sure audio engine is disabled */ - wmb(); -} - -void msm_dp_catalog_audio_config_sdp(struct msm_dp_catalog *msm_dp_catalog) -{ - struct msm_dp_catalog_private *catalog; - u32 sdp_cfg =3D 0; - u32 sdp_cfg2 =3D 0; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - sdp_cfg =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG); - /* AUDIO_TIMESTAMP_SDP_EN */ - sdp_cfg |=3D BIT(1); - /* AUDIO_STREAM_SDP_EN */ - sdp_cfg |=3D BIT(2); - /* AUDIO_COPY_MANAGEMENT_SDP_EN */ - sdp_cfg |=3D BIT(5); - /* AUDIO_ISRC_SDP_EN */ - sdp_cfg |=3D BIT(6); - /* AUDIO_INFOFRAME_SDP_EN */ - sdp_cfg |=3D BIT(20); - - drm_dbg_dp(catalog->drm_dev, "sdp_cfg =3D 0x%x\n", sdp_cfg); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, sdp_cfg); - - sdp_cfg2 =3D msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2); - /* IFRM_REGSRC -> Do not use reg values */ - sdp_cfg2 &=3D ~BIT(0); - /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ - sdp_cfg2 &=3D ~BIT(1); - - drm_dbg_dp(catalog->drm_dev, "sdp_cfg2 =3D 0x%x\n", sdp_cfg2); - - msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); -} - -void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *msm_dp_catalog,= u32 safe_to_exit_level) -{ - struct msm_dp_catalog_private *catalog; - u32 mainlink_levels; - - if (!msm_dp_catalog) - return; - - catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - mainlink_levels =3D msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_LEVE= LS); - mainlink_levels &=3D 0xFE0; - mainlink_levels |=3D safe_to_exit_level; - - drm_dbg_dp(catalog->drm_dev, - "mainlink_level =3D 0x%x, safe_to_exit_level =3D 0x%x\n", - mainlink_levels, safe_to_exit_level); - - msm_dp_write_link(msm_dp_catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels= ); -} diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 24f1cf4ed5150c4e0e80880588641a01bb6a1596..e2fdccc332f874458709593c68a= 1d1a46b6cc406 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -134,10 +134,4 @@ u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(stru= ct msm_dp_catalog *msm_dp_ =20 struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); 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Thu, 07 Nov 2024 16:22:08 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 08 Nov 2024 02:21:43 +0200 Subject: [PATCH 12/14] drm/msm/dp: move more AUX functions to dp_aux.c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-12-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14070; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=+g9SNORbUVqTNMWLsJKHyxMmmD7Ice6ep+SokQX8YuI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmQcahJoRYJXF4rGBEDoYzqCVcGX2WVZXT0g Dbpi8m/S1yJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZkAAKCRCLPIo+Aiko 1VjUCACzTuPIUZj0V2D96LiTDtRACKz9LksFbND0WmBL94jAXHYpPFu+9qkJIrThUKBdCrm6JNn 4c9og09lVDWE2HdiGVKL78qqnIvbKxzdikXZgOypsEWIXWEZe7TfBY4X6bsKaKE8rkmtub1uOx1 zh1Pt3efQ3ekZ9/CA12J5vV/+3clL7gC1TJZAtZ3ItO9gI2Ac5vWKH8h7rsDdUdZMF68/SFnmd8 eQjSAVF1I9silrW6RLPJoh/y5gi0DbHz3k0ZPLcCWwKJT8HvS+Xrmuc+9K/87uXI2f4GK0jwxCb uJqkNymVuSKWK0OLA/20M1RMQ4xahL4IBxsHLTBVlhr/zK+c X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move several misnamed functions accessing AUX bus to dp_aux.c, further cleaning up dp_catalog submodule. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_aux.c | 88 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_aux.h | 7 +++ drivers/gpu/drm/msm/dp/dp_catalog.c | 75 +------------------------------ drivers/gpu/drm/msm/dp/dp_catalog.h | 6 --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 18 ++++---- drivers/gpu/drm/msm/dp/dp_panel.c | 2 +- 7 files changed, 107 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index 46e8a2e13ac1d1249fbad9b50a6d64c52d51cf38..7228955019b31f80257b86a470c= 9ef305b2549a0 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -405,7 +405,7 @@ static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *m= sm_dp_aux, phy_calibrate(aux->phy); } /* reset aux if link is in connected state */ - if (msm_dp_catalog_link_is_connected(aux->catalog)) + if (msm_dp_aux_is_link_connected(msm_dp_aux)) msm_dp_aux_reset(aux); } else { aux->retry_cnt =3D 0; @@ -593,6 +593,92 @@ static int msm_dp_wait_hpd_asserted(struct drm_dp_aux = *msm_dp_aux, return ret; } =20 +void msm_dp_aux_hpd_enable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp= _aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + /* Configure REFTIMER and enable it */ + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg |=3D DP_DP_HPD_REFTIMER_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + + /* Enable HPD */ + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); +} + +void msm_dp_aux_hpd_disable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp= _aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); + reg &=3D ~DP_DP_HPD_REFTIMER_ENABLE; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reg); + + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); +} + +void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp= _aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg |=3D DP_DP_HPD_INT_MASK; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + reg & DP_DP_HPD_INT_MASK); +} + +void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp= _aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 reg; + + reg =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + reg &=3D ~DP_DP_HPD_INT_MASK; + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, + reg & DP_DP_HPD_INT_MASK); +} + +u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp= _aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + int isr, mask; + + isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, + (isr & DP_DP_HPD_INT_MASK)); + mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); + + /* + * We only want to return interrupts that are unmasked to the caller. + * However, the interrupt status field also contains other + * informational bits about the HPD state status, so we only mask + * out the part of the register that tells us about which interrupts + * are pending. + */ + return isr & (mask | ~DP_DP_HPD_INT_MASK); +} + +u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux) +{ + struct msm_dp_aux_private *aux =3D container_of(msm_dp_aux, struct msm_dp= _aux_private, msm_dp_aux); + struct msm_dp_catalog *msm_dp_catalog =3D aux->catalog; + u32 status; + + status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); + status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; + status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; + + return status; +} + struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, struct phy *phy, bool is_edp) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_au= x.h index 39c5b4c8596ab28d822493a6b4d479f5f786cdee..624395a41ed0a75ead4826e78d0= 5ca21e8fb8967 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -17,6 +17,13 @@ void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_reconfig(struct drm_dp_aux *msm_dp_aux); =20 +void msm_dp_aux_hpd_enable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_disable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_intr_enable(struct drm_dp_aux *msm_dp_aux); +void msm_dp_aux_hpd_intr_disable(struct drm_dp_aux *msm_dp_aux); +u32 msm_dp_aux_get_hpd_intr_status(struct drm_dp_aux *msm_dp_aux); +u32 msm_dp_aux_is_link_connected(struct drm_dp_aux *msm_dp_aux); + struct phy; struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalo= g *catalog, struct phy *phy, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 60ba6e0a204f536fd050591e891add17d286fb2d..754b30e35039618453df9ce863c= 0d2561fce2fda 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -81,8 +81,8 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm= _dp_catalog) intr &=3D ~DP_INTERRUPT_STATUS1_MASK; intr_ack =3D (intr & DP_INTERRUPT_STATUS1) << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, intr_ack | - DP_INTERRUPT_STATUS1_MASK); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + intr_ack | DP_INTERRUPT_STATUS1_MASK); =20 return intr; =20 @@ -115,77 +115,6 @@ void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_cata= log *msm_dp_catalog, } } =20 -void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, - u32 intr_mask, bool en) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - - u32 config =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); - - config =3D (en ? config | intr_mask : config & ~intr_mask); - - drm_dbg_dp(catalog->drm_dev, "intr_mask=3D%#x config=3D%#x\n", - intr_mask, config); - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK, - config & DP_DP_HPD_INT_MASK); -} - -void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); - - /* Configure REFTIMER and enable it */ - reftimer |=3D DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - - /* Enable HPD */ - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_E= N); -} - -void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 reftimer =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER); - - reftimer &=3D ~DP_DP_HPD_REFTIMER_ENABLE; - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_CTRL, 0); -} - -u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) -{ - struct msm_dp_catalog_private *catalog =3D container_of(msm_dp_catalog, - struct msm_dp_catalog_private, msm_dp_catalog); - u32 status; - - status =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); - drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status); - status >>=3D DP_DP_HPD_STATE_STATUS_BITS_SHIFT; - status &=3D DP_DP_HPD_STATE_STATUS_BITS_MASK; - - return status; -} - -u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og) -{ - int isr, mask; - - isr =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_STATUS); - msm_dp_write_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_ACK, - (isr & DP_DP_HPD_INT_MASK)); - mask =3D msm_dp_read_aux(msm_dp_catalog, REG_DP_DP_HPD_INT_MASK); - - /* - * We only want to return interrupts that are unmasked to the caller. - * However, the interrupt status field also contains other - * informational bits about the HPD state status, so we only mask - * out the part of the register that tells us about which interrupts - * are pending. - */ - return isr & (mask | ~DP_DP_HPD_INT_MASK); -} - u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) { u32 intr, intr_ack; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index e2fdccc332f874458709593c68a1d1a46b6cc406..830d9164188c0f7520809a99fa4= 09b473bbfbfa4 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -122,12 +122,6 @@ u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *= msm_dp_catalog); /* DP Controller APIs */ u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog= ); void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,= bool enable); -void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, - u32 intr_mask, bool en); -void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog); -void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog= ); -u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog= ); -u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catal= og); int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g); void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index cde667bf8eeec95035b2feb3661686c99acf5b7d..5f32ee2fa0438cd12726540a59a= b4849d47ee8c2 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2162,7 +2162,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) break; } else if (training_step =3D=3D DP_TRAINING_1) { /* link train_1 failed */ - if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) + if (!msm_dp_aux_is_link_connected(ctrl->aux)) break; =20 msm_dp_ctrl_read_link_status(ctrl, link_status); @@ -2187,7 +2187,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) } } else if (training_step =3D=3D DP_TRAINING_2) { /* link train_2 failed */ - if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) + if (!msm_dp_aux_is_link_connected(ctrl->aux)) break; =20 msm_dp_ctrl_read_link_status(ctrl, link_status); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index aba925aab7ad7c6652e81004043864c1cb3ac370..72a46e9e319486bc4ec1f5c842d= 733bd55ce0a67 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1145,7 +1145,7 @@ static irqreturn_t msm_dp_display_irq_handler(int irq= , void *dev_id) return IRQ_NONE; } =20 - hpd_isr_status =3D msm_dp_catalog_hpd_get_intr_status(dp->catalog); + hpd_isr_status =3D msm_dp_aux_get_hpd_intr_status(dp->aux); =20 if (hpd_isr_status & 0x0F) { drm_dbg_dp(dp->drm_dev, "type=3D%d isr=3D0x%x\n", @@ -1360,7 +1360,7 @@ static int msm_dp_pm_runtime_suspend(struct device *d= ev) =20 if (dp->msm_dp_display.is_edp) { msm_dp_display_host_phy_exit(dp); - msm_dp_catalog_ctrl_hpd_disable(dp->catalog); + msm_dp_aux_hpd_disable(dp->aux); } msm_dp_display_host_deinit(dp); =20 @@ -1381,7 +1381,7 @@ static int msm_dp_pm_runtime_resume(struct device *de= v) */ msm_dp_display_host_init(dp); if (dp->msm_dp_display.is_edp) { - msm_dp_catalog_ctrl_hpd_enable(dp->catalog); + msm_dp_aux_hpd_enable(dp->aux); msm_dp_display_host_phy_init(dp); } =20 @@ -1668,10 +1668,8 @@ void msm_dp_bridge_hpd_enable(struct drm_bridge *bri= dge) return; } =20 - msm_dp_catalog_ctrl_hpd_enable(dp->catalog); - - /* enable HDP interrupts */ - msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, true); + msm_dp_aux_hpd_enable(dp->aux); + msm_dp_aux_hpd_intr_enable(dp->aux); =20 msm_dp_display->internal_hpd =3D true; mutex_unlock(&dp->event_mutex); @@ -1684,9 +1682,9 @@ void msm_dp_bridge_hpd_disable(struct drm_bridge *bri= dge) struct msm_dp_display_private *dp =3D container_of(msm_dp_display, struct= msm_dp_display_private, msm_dp_display); =20 mutex_lock(&dp->event_mutex); - /* disable HDP interrupts */ - msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false); - msm_dp_catalog_ctrl_hpd_disable(dp->catalog); + + msm_dp_aux_hpd_intr_disable(dp->aux); + msm_dp_aux_hpd_disable(dp->aux); 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a=openpgp-sha256; l=3781; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=+MBwJhJ+kWsOd4zG8stBduLkJa3ofaC7qfvHFVuut/U=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmQ9emA0NkGmbuBJO5bIw1pGCdfRbWpJGcGv U6PeakRvW2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZkAAKCRCLPIo+Aiko 1YmnB/49tkHi3iF28qy6bExEcNimP6jsHsacWo0NUj1XuyiFiP3oYDLQGvFLZu6s2PVL23RU5JE 9JsdhEpt5pG7SZ6KjqSq7PmnFiVVxp36o1q3JISx2UBwZrYrASwGaxkOp0Hq/neGeAulv0kxuVw zAgk0d2PPqsxnPfELVHoUGbjIzYapnTA9JdRxtTAziRCJax6tem27cmRrL6X719xDSc+Lzx3R/1 ixy49WLJ5DcCfUvEyfIvFeiyUnY5j7JugfHm/R4mHFOsRn3Pb277Ew+mUhvl7XEOxZa5WcsA+un 4ltybwYS/VxOvjhtMxdGtM4/9ClixltO+HR2cIos04m2fnnk X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A All other submodules pass arguments directly. Drop struct msm_dp_panel_in that is used to wrap dp_panel's submodule args and pass all data to msm_dp_panel_get() directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 9 +-------- drivers/gpu/drm/msm/dp/dp_panel.c | 15 ++++++++------- drivers/gpu/drm/msm/dp/dp_panel.h | 10 ++-------- 3 files changed, 11 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 72a46e9e319486bc4ec1f5c842d733bd55ce0a67..8f8fa0cb8af67383ecfce026ee8= 840f70b82e6da 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -722,9 +722,6 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) { int rc =3D 0; struct device *dev =3D &dp->msm_dp_display.pdev->dev; - struct msm_dp_panel_in panel_in =3D { - .dev =3D dev, - }; struct phy *phy; =20 phy =3D devm_phy_get(dev, "dp"); @@ -765,11 +762,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displ= ay_private *dp) goto error_link; } =20 - panel_in.aux =3D dp->aux; - panel_in.catalog =3D dp->catalog; - panel_in.link =3D dp->link; - - dp->panel =3D msm_dp_panel_get(&panel_in); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->catalog); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 58045d9a52e9a4d39362c3de623fa34acd5784ec..6e6dc3169e9c2f84273e5991006= 02583550f521c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -549,25 +549,26 @@ static int msm_dp_panel_parse_dt(struct msm_dp_panel = *msm_dp_panel) return 0; } =20 -struct msm_dp_panel *msm_dp_panel_get(struct msm_dp_panel_in *in) +struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, + struct msm_dp_link *link, struct msm_dp_catalog *catalog) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; int ret; =20 - if (!in->dev || !in->catalog || !in->aux || !in->link) { + if (!dev || !catalog || !aux || !link) { DRM_ERROR("invalid input\n"); return ERR_PTR(-EINVAL); } =20 - panel =3D devm_kzalloc(in->dev, sizeof(*panel), GFP_KERNEL); + panel =3D devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); if (!panel) return ERR_PTR(-ENOMEM); =20 - panel->dev =3D in->dev; - panel->aux =3D in->aux; - panel->catalog =3D in->catalog; - panel->link =3D in->link; + panel->dev =3D dev; + panel->aux =3D aux; + panel->catalog =3D catalog; + panel->link =3D link; =20 msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 332ac79594e71157e2b087dc5268c50a87993d83..482ead77e7c01e6d611dbdce37f= 82a8dfbc4e3e4 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -21,13 +21,6 @@ struct msm_dp_display_mode { bool out_fmt_is_yuv_420; }; =20 -struct msm_dp_panel_in { - struct device *dev; - struct drm_dp_aux *aux; - struct msm_dp_link *link; - struct msm_dp_catalog *catalog; -}; - struct msm_dp_panel_psr { u8 version; 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Thu, 07 Nov 2024 16:22:14 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 08 Nov 2024 02:21:45 +0200 Subject: [PATCH 14/14] drm/msm/dp: move interrupt handling to dp_ctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241108-fd-dp-audio-fixup-v1-14-40c8eeb60cf5@linaro.org> References: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> In-Reply-To: <20241108-fd-dp-audio-fixup-v1-0-40c8eeb60cf5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Paloma Arellano Cc: Douglas Anderson , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=19325; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=8C6rPsQS4FU2y6sH3qMMieCj3tGAmPNo6Yihp1+d1r4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnLVmQkYk6c0ZiUnTKgQof3u+G22gNfKqNIXAh4 q6Ks/lARCOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZy1ZkAAKCRCLPIo+Aiko 1e8pCACnvh45sjNS6SbVO3WM9kU0Gl+R37QKXA6UPVYSvbyiSdJ+zSPn+3GBJtzz0LnpqGR7JeJ Tpd2JOM4vxHRZKdNV897wtIEBliZp/PrSLR/PXcqVoao1PcYZG6D/ocW4Q+oDC7JbhMzm7ETC96 SSzyi9XkSIyL/2ORS/RH7j0XHz9Gt7Y37HcxJdaGThg16qyJ9X/P3o87PxftkS/ZqRvQ2ElJrFo 53Bss+9DPeHsQ9D55MRHD79nBYuFRXgyckXA6ZolHh6Sl1QppTLzvnPvH6x1t/d9aAZJ+W5swYJ ihj6otkCCEfKZF69NLR926UdUtJwZYslIk626neYKgvhVvIR X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A It makes it easier to keep all interrupts-related code in dp_ctrl submodule. Move all functions to dp_ctrl.c. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_aux.c | 9 +-- drivers/gpu/drm/msm/dp/dp_aux.h | 2 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 95 ------------------------ drivers/gpu/drm/msm/dp/dp_catalog.h | 24 ------ drivers/gpu/drm/msm/dp/dp_ctrl.c | 142 ++++++++++++++++++++++++++++++--= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 5 +- drivers/gpu/drm/msm/dp/dp_display.c | 9 +-- drivers/gpu/drm/msm/dp/dp_reg.h | 17 +++++ 8 files changed, 145 insertions(+), 158 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_au= x.c index 7228955019b31f80257b86a470c9ef305b2549a0..1ae0bf9e4f51a98a01bf9eb5c36= 323e1743b5ab4 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -439,9 +439,8 @@ static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *m= sm_dp_aux, return ret; } =20 -irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux) +irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux, u32 isr) { - u32 isr; struct msm_dp_aux_private *aux; =20 if (!msm_dp_aux) { @@ -451,12 +450,6 @@ irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_a= ux) =20 aux =3D container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); =20 - isr =3D msm_dp_catalog_aux_get_irq(aux->catalog); - - /* no interrupts pending, return immediately */ - if (!isr) - return IRQ_NONE; - if (!aux->cmd_busy) { DRM_ERROR("Unexpected DP AUX IRQ %#010x when not busy\n", isr); return IRQ_NONE; diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_au= x.h index 624395a41ed0a75ead4826e78d05ca21e8fb8967..83908c93b6a1baa6c4eb83a346b= 4498704008ca5 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -11,7 +11,7 @@ =20 int msm_dp_aux_register(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_unregister(struct drm_dp_aux *msm_dp_aux); -irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux); +irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux, u32 isr); void msm_dp_aux_enable_xfers(struct drm_dp_aux *msm_dp_aux, bool enabled); void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux); void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux); diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 754b30e35039618453df9ce863c0d2561fce2fda..e7c421b50127c6ef3b5ddbb0e35= 54570d169e544 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -15,41 +15,6 @@ #include "dp_catalog.h" #include "dp_reg.h" =20 -#define POLLING_SLEEP_US 1000 -#define POLLING_TIMEOUT_US 10000 - -#define DP_INTERRUPT_STATUS_ACK_SHIFT 1 -#define DP_INTERRUPT_STATUS_MASK_SHIFT 2 - -#define DP_INTERRUPT_STATUS1 \ - (DP_INTR_AUX_XFER_DONE| \ - DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ - DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \ - DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \ - DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR) - -#define DP_INTERRUPT_STATUS1_ACK \ - (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_ACK_SHIFT) -#define DP_INTERRUPT_STATUS1_MASK \ - (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_MASK_SHIFT) - -#define DP_INTERRUPT_STATUS2 \ - (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \ - DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED) - -#define DP_INTERRUPT_STATUS2_ACK \ - (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_ACK_SHIFT) -#define DP_INTERRUPT_STATUS2_MASK \ - (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT) - -#define DP_INTERRUPT_STATUS4 \ - (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \ - PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT) - -#define DP_INTERRUPT_MASK4 \ - (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ - PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) - #define DP_DEFAULT_AHB_OFFSET 0x0000 #define DP_DEFAULT_AHB_SIZE 0x0200 #define DP_DEFAULT_AUX_OFFSET 0x0200 @@ -73,21 +38,6 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_= dp_catalog, struct msm_d msm_disp_snapshot_add_block(disp_state, msm_dp_catalog->p0_len, msm_dp_ca= talog->p0_base, "dp_p0"); } =20 -u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) -{ - u32 intr, intr_ack; - - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); - intr &=3D ~DP_INTERRUPT_STATUS1_MASK; - intr_ack =3D (intr & DP_INTERRUPT_STATUS1) - << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, - intr_ack | DP_INTERRUPT_STATUS1_MASK); - - return intr; - -} - /** * msm_dp_catalog_hw_revision() - retrieve DP hw revision * @@ -101,51 +51,6 @@ u32 msm_dp_catalog_hw_revision(const struct msm_dp_cata= log *msm_dp_catalog) return msm_dp_read_ahb(msm_dp_catalog, REG_DP_HW_VERSION); } =20 -void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, - bool enable) -{ - if (enable) { - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, - DP_INTERRUPT_STATUS1_MASK); - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, - DP_INTERRUPT_STATUS2_MASK); - } else { - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); - } -} - -u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog) -{ - u32 intr, intr_ack; - - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); - intr_ack =3D (intr & DP_INTERRUPT_STATUS4) - << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); - - return intr; -} - -void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog) -{ - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); -} - -int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g) -{ - u32 intr, intr_ack; - - intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); - intr &=3D ~DP_INTERRUPT_STATUS2_MASK; - intr_ack =3D (intr & DP_INTERRUPT_STATUS2) - << DP_INTERRUPT_STATUS_ACK_SHIFT; - msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, - intr_ack | DP_INTERRUPT_STATUS2_MASK); - - return intr; -} - static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,= size_t *len) { struct resource *res; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 830d9164188c0f7520809a99fa409b473bbfbfa4..c57792b134357933aa3c1f4d278= f1c1a309688cf 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -11,23 +11,6 @@ #include "dp_utils.h" #include "disp/msm_disp_snapshot.h" =20 -/* interrupts */ -#define DP_INTR_HPD BIT(0) -#define DP_INTR_AUX_XFER_DONE BIT(3) -#define DP_INTR_WRONG_ADDR BIT(6) -#define DP_INTR_TIMEOUT BIT(9) -#define DP_INTR_NACK_DEFER BIT(12) -#define DP_INTR_WRONG_DATA_CNT BIT(15) -#define DP_INTR_I2C_NACK BIT(18) -#define DP_INTR_I2C_DEFER BIT(21) -#define DP_INTR_PLL_UNLOCKED BIT(24) -#define DP_INTR_AUX_ERROR BIT(27) - -#define DP_INTR_READY_FOR_VIDEO BIT(0) -#define DP_INTR_IDLE_PATTERN_SENT BIT(3) -#define DP_INTR_FRAME_END BIT(6) -#define DP_INTR_CRC_UPDATED BIT(9) - #define DP_HW_VERSION_1_0 0x10000000 #define DP_HW_VERSION_1_2 0x10020000 =20 @@ -116,15 +99,8 @@ static inline void msm_dp_write_link(struct msm_dp_cata= log *msm_dp_catalog, /* Debug module */ void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct= msm_disp_state *disp_state); =20 -/* AUX APIs */ -u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog); - /* DP Controller APIs */ u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog= ); -void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog,= bool enable); -int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalo= g); -void msm_dp_catalog_ctrl_config_psr_interrupt(struct msm_dp_catalog *msm_d= p_catalog); -u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *m= sm_dp_catalog); =20 struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 5f32ee2fa0438cd12726540a59ab4849d47ee8c2..f978b599bf14c8fc418f0f2dfe4= 0ca911f8957fe 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -30,6 +30,38 @@ #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /= * 300 ms */ #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) =20 +#define DP_INTERRUPT_STATUS_ACK_SHIFT 1 +#define DP_INTERRUPT_STATUS_MASK_SHIFT 2 + +#define DP_INTERRUPT_STATUS1 \ + (DP_INTR_AUX_XFER_DONE| \ + DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ + DP_INTR_NACK_DEFER | DP_INTR_WRONG_DATA_CNT | \ + DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER | \ + DP_INTR_PLL_UNLOCKED | DP_INTR_AUX_ERROR) + +#define DP_INTERRUPT_STATUS1_ACK \ + (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_ACK_SHIFT) +#define DP_INTERRUPT_STATUS1_MASK \ + (DP_INTERRUPT_STATUS1 << DP_INTERRUPT_STATUS_MASK_SHIFT) + +#define DP_INTERRUPT_STATUS2 \ + (DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \ + DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED) + +#define DP_INTERRUPT_STATUS2_ACK \ + (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_ACK_SHIFT) +#define DP_INTERRUPT_STATUS2_MASK \ + (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT) + +#define DP_INTERRUPT_STATUS4 \ + (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \ + PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT) + +#define DP_INTERRUPT_MASK4 \ + (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ + PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) + #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) =20 @@ -126,8 +158,10 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux= *aux, /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ -static void msm_dp_ctrl_reset(struct msm_dp_ctrl_private *ctrl) +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl) { + struct msm_dp_ctrl_private *ctrl =3D + container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; u32 sw_reset; =20 @@ -141,6 +175,79 @@ static void msm_dp_ctrl_reset(struct msm_dp_ctrl_priva= te *ctrl) msm_dp_write_ahb(msm_dp_catalog, REG_DP_SW_RESET, sw_reset); } =20 +static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS); + intr &=3D ~DP_INTERRUPT_STATUS1_MASK; + intr_ack =3D (intr & DP_INTERRUPT_STATUS1) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + intr_ack | DP_INTERRUPT_STATUS1_MASK); + + return intr; + +} + +static u32 msm_dp_ctrl_get_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2); + intr &=3D ~DP_INTERRUPT_STATUS2_MASK; + intr_ack =3D (intr & DP_INTERRUPT_STATUS2) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, + intr_ack | DP_INTERRUPT_STATUS2_MASK); + + return intr; +} + +void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl =3D + container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, + DP_INTERRUPT_STATUS1_MASK); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, + DP_INTERRUPT_STATUS2_MASK); +} + +void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl =3D + container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS, 0x00); + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS2, 0x00); +} + +static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4); + intr_ack =3D (intr & DP_INTERRUPT_STATUS4) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_STATUS4, intr_ack); + + return intr; +} + +static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *c= trl) +{ + struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; + + msm_dp_write_ahb(msm_dp_catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); +} + static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) { struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; @@ -1630,23 +1737,6 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struct= msm_dp_ctrl_private *ctrl) return ret; } =20 -void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enab= le) -{ - struct msm_dp_ctrl_private *ctrl; - - ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); - - msm_dp_ctrl_reset(ctrl); - - /* - * all dp controller programmable registers will not - * be reset to default value after DP_SW_RESET - * therefore interrupt mask bits have to be updated - * to enable/disable interrupts - */ - msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); -} - static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) { struct msm_dp_catalog *msm_dp_catalog =3D ctrl->catalog; @@ -1699,7 +1789,7 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_d= p_ctrl) cfg |=3D PSR1_SUPPORTED; msm_dp_write_link(msm_dp_catalog, REG_PSR_CONFIG, cfg); =20 - msm_dp_catalog_ctrl_config_psr_interrupt(msm_dp_catalog); + msm_dp_ctrl_config_psr_interrupt(ctrl); msm_dp_ctrl_enable_sdp(ctrl); =20 cfg =3D DP_PSR_ENABLE; @@ -1824,7 +1914,7 @@ static int msm_dp_ctrl_deinitialize_mainlink(struct m= sm_dp_ctrl_private *ctrl) =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); @@ -2453,7 +2543,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) =20 msm_dp_ctrl_mainlink_disable(ctrl); =20 - msm_dp_ctrl_reset(ctrl); + msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 if (ctrl->stream_clks_on) { clk_disable_unprepare(ctrl->pixel_clk); @@ -2480,7 +2570,7 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_d= p_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 if (ctrl->panel->psr_cap.version) { - isr =3D msm_dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog); + isr =3D msm_dp_ctrl_get_psr_interrupt(ctrl); =20 if (isr) complete(&ctrl->psr_op_comp); @@ -2495,8 +2585,7 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_d= p_ctrl) drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); } =20 - isr =3D msm_dp_catalog_ctrl_get_interrupt(ctrl->catalog); - + isr =3D msm_dp_ctrl_get_interrupt(ctrl); =20 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); @@ -2510,6 +2599,11 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_= dp_ctrl) ret =3D IRQ_HANDLED; } =20 + /* DP aux isr */ + isr =3D msm_dp_ctrl_get_aux_interrupt(ctrl); + if (isr) + ret |=3D msm_dp_aux_isr(ctrl->aux, isr); + return ret; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index b7abfedbf5749c25877a0b8ba3af3d8ed4b23d67..10a4b7cf0335a584b4db67baca8= 82620d7bab74c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -30,7 +30,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, s= truct msm_dp_link *link struct msm_dp_catalog *catalog, struct phy *phy); =20 -void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enab= le); +void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_irq_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); @@ -41,4 +41,7 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ct= rl); int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl); =20 +void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); + #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 8f8fa0cb8af67383ecfce026ee8840f70b82e6da..af39dc5e52cbe93c5b4d082dbdc= bff5c4890036f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -440,7 +440,8 @@ static void msm_dp_display_host_init(struct msm_dp_disp= lay_private *dp) dp->phy_initialized); =20 msm_dp_ctrl_core_clk_enable(dp->ctrl); - msm_dp_ctrl_reset_irq_ctrl(dp->ctrl, true); + msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_enable_irq(dp->ctrl); msm_dp_aux_init(dp->aux); dp->core_initialized =3D true; } @@ -451,7 +452,8 @@ static void msm_dp_display_host_deinit(struct msm_dp_di= splay_private *dp) dp->msm_dp_display.connector_type, dp->core_initialized, dp->phy_initialized); =20 - msm_dp_ctrl_reset_irq_ctrl(dp->ctrl, false); + msm_dp_ctrl_reset(dp->ctrl); + msm_dp_ctrl_disable_irq(dp->ctrl); msm_dp_aux_deinit(dp->aux); msm_dp_ctrl_core_clk_disable(dp->ctrl); dp->core_initialized =3D false; @@ -1165,9 +1167,6 @@ static irqreturn_t msm_dp_display_irq_handler(int irq= , void *dev_id) /* DP controller isr */ ret |=3D msm_dp_ctrl_isr(dp->ctrl); =20 - /* DP aux isr */ - ret |=3D msm_dp_aux_isr(dp->aux); - return ret; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 3835c7f5cb984406f8fc52ea765ef2315e0d175b..d17e077ded73251624b5fb1bfbd= 8f213b4a86d65 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -21,8 +21,25 @@ =20 #define REG_DP_CLK_CTRL (0x00000018) #define REG_DP_CLK_ACTIVE (0x0000001C) + #define REG_DP_INTR_STATUS (0x00000020) +#define DP_INTR_HPD BIT(0) +#define DP_INTR_AUX_XFER_DONE BIT(3) +#define DP_INTR_WRONG_ADDR BIT(6) +#define DP_INTR_TIMEOUT BIT(9) +#define DP_INTR_NACK_DEFER BIT(12) +#define DP_INTR_WRONG_DATA_CNT BIT(15) +#define DP_INTR_I2C_NACK BIT(18) +#define DP_INTR_I2C_DEFER BIT(21) +#define DP_INTR_PLL_UNLOCKED BIT(24) +#define DP_INTR_AUX_ERROR BIT(27) + #define REG_DP_INTR_STATUS2 (0x00000024) +#define DP_INTR_READY_FOR_VIDEO BIT(0) +#define DP_INTR_IDLE_PATTERN_SENT BIT(3) +#define DP_INTR_FRAME_END BIT(6) +#define DP_INTR_CRC_UPDATED BIT(9) + #define REG_DP_INTR_STATUS3 (0x00000028) =20 #define REG_DP_INTR_STATUS4 (0x0000002C) --=20 2.39.5